From 51ddd2c01e0636f713417f30379b876e85558f61 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sun, 13 Dec 2009 09:47:02 -0800 Subject: [PATCH] Define bit_XXX and index_XXX. This patch defines bit_XXX and index_XXX and use them to check processor feature in assembly code. It can prevent typos in processor feature check. --- ChangeLog | 19 +++++++++++++++++++ sysdeps/x86_64/multiarch/init-arch.h | 14 ++++++++++++++ sysdeps/x86_64/multiarch/rawmemchr.S | 4 ++-- sysdeps/x86_64/multiarch/strchr.S | 4 ++-- sysdeps/x86_64/multiarch/strcmp.S | 6 +++--- sysdeps/x86_64/multiarch/strcpy.S | 4 ++-- sysdeps/x86_64/multiarch/strcspn.S | 4 ++-- sysdeps/x86_64/multiarch/strlen.S | 4 ++-- sysdeps/x86_64/multiarch/strrchr.S | 4 ++-- sysdeps/x86_64/multiarch/strspn.S | 4 ++-- 10 files changed, 50 insertions(+), 17 deletions(-) diff --git a/ChangeLog b/ChangeLog index db93544..45b9d2d 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,22 @@ +2009-12-09 H.J. Lu + + * sysdeps/x86_64/multiarch/init-arch.h: Include + if __ASSEMBLER__ is defined. + (bit_SSSE3): New. Defined for __ASSEMBLER__. + (bit_SSE4_2): Likewise. + (index_SSSE3): Likewise. + (index_SSE4_2): Likewise. + * sysdeps/x86_64/multiarch/rawmemchr.S: Include + instead of . Use bit_XXX and index_XXX to + check processor feature. + * sysdeps/x86_64/multiarch/strchr.S: Likewise. + * sysdeps/x86_64/multiarch/strcmp.S: Likewise. + * sysdeps/x86_64/multiarch/strcpy.S: Likewise. + * sysdeps/x86_64/multiarch/strcspn.S: Likewise. + * sysdeps/x86_64/multiarch/strlen.S: Likewise. + * sysdeps/x86_64/multiarch/strrchr.S: Likewise. + * sysdeps/x86_64/multiarch/strspn.S: Likewise. + 2009-12-08 Kaz Kojima * sysdeps/sh/elf/initfini.c: Update according to generic/initfini.c. diff --git a/sysdeps/x86_64/multiarch/init-arch.h b/sysdeps/x86_64/multiarch/init-arch.h index 9b12831..9e8915f 100644 --- a/sysdeps/x86_64/multiarch/init-arch.h +++ b/sysdeps/x86_64/multiarch/init-arch.h @@ -16,6 +16,18 @@ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. */ +#ifdef __ASSEMBLER__ + +#include + +#define bit_SSSE3 (1 << 9) +#define bit_SSE4_2 (1 << 20) + +#define index_SSSE3 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET +#define index_SSE4_2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET + +#else /* __ASSEMBLER__ */ + #include enum @@ -71,3 +83,5 @@ extern const struct cpu_features *__get_cpu_features (void) #define HAS_POPCOUNT HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, 23) #define HAS_SSE4_2 HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, 20) #define HAS_FMA HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, 12) + +#endif /* __ASSEMBLER__ */ diff --git a/sysdeps/x86_64/multiarch/rawmemchr.S b/sysdeps/x86_64/multiarch/rawmemchr.S index 08fd876..2a8a690 100644 --- a/sysdeps/x86_64/multiarch/rawmemchr.S +++ b/sysdeps/x86_64/multiarch/rawmemchr.S @@ -18,7 +18,7 @@ 02111-1307 USA. */ #include -#include +#include /* Define multiple versions only for the definition in lib. */ @@ -30,7 +30,7 @@ ENTRY(rawmemchr) jne 1f call __init_cpu_features 1: leaq __rawmemchr_sse2(%rip), %rax - testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip) + testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) jz 2f leaq __rawmemchr_sse42(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/multiarch/strchr.S b/sysdeps/x86_64/multiarch/strchr.S index b35566d..27eead9 100644 --- a/sysdeps/x86_64/multiarch/strchr.S +++ b/sysdeps/x86_64/multiarch/strchr.S @@ -18,7 +18,7 @@ 02111-1307 USA. */ #include -#include +#include /* Define multiple versions only for the definition in libc. */ @@ -30,7 +30,7 @@ ENTRY(strchr) jne 1f call __init_cpu_features 1: leaq __strchr_sse2(%rip), %rax - testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip) + testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) jz 2f leaq __strchr_sse42(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/multiarch/strcmp.S b/sysdeps/x86_64/multiarch/strcmp.S index 05adf1e..1d93919 100644 --- a/sysdeps/x86_64/multiarch/strcmp.S +++ b/sysdeps/x86_64/multiarch/strcmp.S @@ -19,7 +19,7 @@ 02111-1307 USA. */ #include -#include +#include #ifdef USE_AS_STRNCMP /* Since the counter, %r11, is unsigned, we branch to strcmp_exitz @@ -64,10 +64,10 @@ ENTRY(STRCMP) call __init_cpu_features 1: leaq STRCMP_SSE42(%rip), %rax - testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip) + testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) jnz 2f leaq STRCMP_SSSE3(%rip), %rax - testl $(1<<9), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip) + testl $bit_SSSE3, __cpu_features+CPUID_OFFSET+index_SSSE3(%rip) jnz 2f leaq STRCMP_SSE2(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/multiarch/strcpy.S b/sysdeps/x86_64/multiarch/strcpy.S index 7e400a9..02fa8d0 100644 --- a/sysdeps/x86_64/multiarch/strcpy.S +++ b/sysdeps/x86_64/multiarch/strcpy.S @@ -19,7 +19,7 @@ 02111-1307 USA. */ #include -#include +#include #if !defined (USE_AS_STPCPY) && !defined (USE_AS_STRNCPY) # ifndef STRCPY @@ -63,7 +63,7 @@ ENTRY(STRCPY) jne 1f call __init_cpu_features 1: leaq STRCPY_SSE2(%rip), %rax - testl $(1<<9), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip) + testl $bit_SSSE3, __cpu_features+CPUID_OFFSET+index_SSSE3(%rip) jz 2f leaq STRCPY_SSSE3(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/multiarch/strcspn.S b/sysdeps/x86_64/multiarch/strcspn.S index cc75ab7..f00d52c 100644 --- a/sysdeps/x86_64/multiarch/strcspn.S +++ b/sysdeps/x86_64/multiarch/strcspn.S @@ -23,7 +23,7 @@ #ifdef HAVE_SSE4_SUPPORT #include -#include +#include #ifdef USE_AS_STRPBRK #define STRCSPN_SSE42 __strpbrk_sse42 @@ -49,7 +49,7 @@ ENTRY(STRCSPN) jne 1f call __init_cpu_features 1: leaq STRCSPN_SSE2(%rip), %rax - testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip) + testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) jz 2f leaq STRCSPN_SSE42(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/multiarch/strlen.S b/sysdeps/x86_64/multiarch/strlen.S index 4342c6c..509f9c9 100644 --- a/sysdeps/x86_64/multiarch/strlen.S +++ b/sysdeps/x86_64/multiarch/strlen.S @@ -19,7 +19,7 @@ 02111-1307 USA. */ #include -#include +#include /* Define multiple versions only for the definition in libc and for @@ -33,7 +33,7 @@ ENTRY(strlen) jne 1f call __init_cpu_features 1: leaq __strlen_sse2(%rip), %rax - testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip) + testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) jz 2f leaq __strlen_sse42(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/multiarch/strrchr.S b/sysdeps/x86_64/multiarch/strrchr.S index f6665f3..0d17fdb 100644 --- a/sysdeps/x86_64/multiarch/strrchr.S +++ b/sysdeps/x86_64/multiarch/strrchr.S @@ -18,7 +18,7 @@ 02111-1307 USA. */ #include -#include +#include /* Define multiple versions only for the definition in libc and for @@ -32,7 +32,7 @@ ENTRY(strrchr) jne 1f call __init_cpu_features 1: leaq __strrchr_sse2(%rip), %rax - testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip) + testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) jz 2f leaq __strrchr_sse42(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/multiarch/strspn.S b/sysdeps/x86_64/multiarch/strspn.S index 4183a2c..1c56626 100644 --- a/sysdeps/x86_64/multiarch/strspn.S +++ b/sysdeps/x86_64/multiarch/strspn.S @@ -23,7 +23,7 @@ #ifdef HAVE_SSE4_SUPPORT #include -#include +#include /* Define multiple versions only for the definition in libc. */ #ifndef NOT_IN_libc @@ -34,7 +34,7 @@ ENTRY(strspn) jne 1f call __init_cpu_features 1: leaq __strspn_sse2(%rip), %rax - testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip) + testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip) jz 2f leaq __strspn_sse42(%rip), %rax 2: ret -- 2.7.4