From 51d8e67e88d1b673c20a61ef4fac201bc15ae664 Mon Sep 17 00:00:00 2001 From: Thomas Johnson Date: Thu, 22 Jul 2021 16:26:46 -0700 Subject: [PATCH] [ARC] Add tablegen definition for the Find Leading Set (FLS) instruction Differential Revision: https://reviews.llvm.org/D106602 --- llvm/lib/Target/ARC/ARCInstrInfo.td | 5 +++++ llvm/test/MC/Disassembler/ARC/misc.txt | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.td b/llvm/lib/Target/ARC/ARCInstrInfo.td index 0813f53..ea3e416 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.td +++ b/llvm/lib/Target/ARC/ARCInstrInfo.td @@ -241,6 +241,8 @@ multiclass ArcBinaryEXT5Inst mincode, string opasm> : multiclass ArcUnaryGEN4Inst mincode, string opasm> : ArcUnaryInst<0b00100, mincode, opasm>; +multiclass ArcUnaryEXT5Inst mincode, string opasm> : + ArcUnaryInst<0b00101, mincode, opasm>; // Pattern generation for different instruction variants. multiclass MultiPat; defm SEXB : ArcUnaryGEN4Inst<0b000101, "sexb">; defm SEXH : ArcUnaryGEN4Inst<0b000110, "sexh">; +// Extension unary instruction definitions. +defm FLS : ArcUnaryEXT5Inst<0b010011, "fls">; + // General Unary Instruction fragments. def : Pat<(sext_inreg i32:$a, i8), (SEXB_rr i32:$a)>; def : Pat<(sext_inreg i32:$a, i16), (SEXH_rr i32:$a)>; diff --git a/llvm/test/MC/Disassembler/ARC/misc.txt b/llvm/test/MC/Disassembler/ARC/misc.txt index 16e5f09..f314b2a 100644 --- a/llvm/test/MC/Disassembler/ARC/misc.txt +++ b/llvm/test/MC/Disassembler/ARC/misc.txt @@ -60,3 +60,9 @@ # CHECK: seteq %fp, %fp, -1 0xb8 0x23 0xff 0x3f + +# CHECK: fls %r0, %r0 +0x2f 0x28 0x13 0x00 + +# CHECK: fls.f %r0, %r0 +0x2f 0x28 0x13 0x80 -- 2.7.4