From 519b0e3e9d6db21922d9a59c467d8b8709323a40 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Fri, 21 Aug 2020 06:13:56 -0500 Subject: [PATCH] [PowerPC] Pre-commit FISel with PC-Rel test Our handling of PC-Relative addressing is currently broken with Fast ISel in 3 ways: - FISel emits calls without handling all the PC-Rel intricacies - FISel materializes FP constants through the TOC - FISel materializes GV's through the TOC As it would be unnecessarily tedious to implement all the handling for PC-Rel in Fast ISel, we will turn off FISel for anything that generates references to the TOC. --- llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll b/llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll new file mode 100644 index 0000000..13fa8a8 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll @@ -0,0 +1,73 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O0 -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -fast-isel -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ +; RUN: FileCheck %s + +%struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] } +%struct._IO_marker = type { %struct._IO_marker*, %struct._IO_FILE*, i32 } + +@.str = private unnamed_addr constant [25 x i8] c"Breaking the TOC for FP\0A\00", align 1 +@.str.1 = private unnamed_addr constant [25 x i8] c"Breaking the TOC for GV\0A\00", align 1 +@stdout = external global %struct._IO_FILE*, align 8 + +; Function Attrs: noinline nounwind optnone +define internal void @loadFP(double* %d) #0 { +; CHECK-LABEL: loadFP: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -112(r1) +; CHECK-NEXT: std r3, 104(r1) +; CHECK-NEXT: paddi r3, 0, .L.str@PCREL, 1 +; CHECK-NEXT: bl printf@notoc +; CHECK-NEXT: addis r4, r2, .LCPI0_0@toc@ha +; CHECK-NEXT: lfd f0, .LCPI0_0@toc@l(r4) +; CHECK-NEXT: ld r4, 104(r1) +; CHECK-NEXT: stfd f0, 0(r4) +; CHECK-NEXT: addi r1, r1, 112 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +entry: + %d.addr = alloca double*, align 8 + store double* %d, double** %d.addr, align 8 + %call = call signext i32 (i8*, ...) @printf(i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i64 0, i64 0)) + %0 = load double*, double** %d.addr, align 8 + store double 4.990000e+00, double* %0, align 8 + ret void +} + +declare signext i32 @printf(i8*, ...) + +; Function Attrs: noinline nounwind optnone +define internal void @loadGV() #0 { +; CHECK-LABEL: loadGV: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -112(r1) +; CHECK-NEXT: paddi r3, 0, .L.str.1@PCREL, 1 +; CHECK-NEXT: bl printf@notoc +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: ld r4, 0(r4) +; CHECK-NEXT: li r5, 97 +; CHECK-NEXT: extsw r5, r5 +; CHECK-NEXT: std r3, 104(r1) # 8-byte Folded Spill +; CHECK-NEXT: mr r3, r5 +; CHECK-NEXT: bl _IO_putc +; CHECK-NEXT: nop +; CHECK-NEXT: addi r1, r1, 112 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +entry: + %call = call signext i32 (i8*, ...) @printf(i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str.1, i64 0, i64 0)) + %0 = load %struct._IO_FILE*, %struct._IO_FILE** @stdout, align 8 + %call1 = call signext i32 @_IO_putc(i32 signext 97, %struct._IO_FILE* %0) + ret void +} + +declare signext i32 @_IO_putc(i32 signext, %struct._IO_FILE*) + +attributes #0 = { noinline nounwind optnone } -- 2.7.4