From 512431b3575eb5f2c27d8795c5e2191047ebb5ed Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 26 Oct 2011 22:41:07 -0700 Subject: [PATCH] i965/fs: Use the actual hardware g0 register for texel offset setup. The idea here is to set up the message header with the Sampler State pointer which the hardware provides as part of the PS Thread Payload in register g0. Unfortunately, the existing code fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)) actually references "virtual GRF 0" rather than the hardware g0. This is just some arbitrary GRF temporary which will get register allocated. So, we ended up setting up the header with garbage. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 2f95014..15009dc 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1086,7 +1086,7 @@ fs_visitor::visit(ir_texture *ir) /* Explicitly set up the message header by copying g0 to msg reg m1. */ emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), - fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); + fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD))); /* Then set the offset bits in DWord 2 of the message header. */ emit(BRW_OPCODE_MOV, -- 2.7.4