From 51153256b05cfb1bc93c518f51de7c3960188fa0 Mon Sep 17 00:00:00 2001 From: Qi Duan Date: Thu, 29 Jun 2017 14:55:15 +0800 Subject: [PATCH] UART: setting clk81 gate and clock source by dts PD#146725: UART: setting clk81 gate and clock source by dts [1/1] Change-Id: I5d1bacb9d59db250372100fc93263b1f0412027f Signed-off-by: Qi Duan --- arch/arm64/boot/dts/amlogic/axg_a113d_skt.dts | 12 +++++++---- arch/arm64/boot/dts/amlogic/axg_s400.dts | 12 +++++++---- arch/arm64/boot/dts/amlogic/axg_s420.dts | 12 +++++++---- drivers/amlogic/uart/meson_uart.c | 30 ++++++++++++++++++--------- 4 files changed, 44 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/axg_a113d_skt.dts b/arch/arm64/boot/dts/amlogic/axg_a113d_skt.dts index dcb4746..1d05b03 100644 --- a/arch/arm64/boot/dts/amlogic/axg_a113d_skt.dts +++ b/arch/arm64/boot/dts/amlogic/axg_a113d_skt.dts @@ -359,8 +359,10 @@ reg = <0x0 0xffd24000 0x0 0x18>; interrupts = <0 26 1>; status = "disable"; - clocks = <&xtal>; - clock-names = "clk_uart"; + clocks = <&xtal + &clkc CLKID_UART0>; + clock-names = "clk_uart", + "clk_gate"; fifosize = < 128 >; pinctrl-names = "default"; pinctrl-0 = <&a_uart_pins>; @@ -371,8 +373,10 @@ reg = <0x0 0xffd23000 0x0 0x18>; interrupts = <0 75 1>; status = "disable"; - clocks = <&xtal>; - clock-names = "clk_uart"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; fifosize = < 64 >; pinctrl-names = "default"; pinctrl-0 = <&b_uart_pins>; diff --git a/arch/arm64/boot/dts/amlogic/axg_s400.dts b/arch/arm64/boot/dts/amlogic/axg_s400.dts index 61603c6..e592c4a 100644 --- a/arch/arm64/boot/dts/amlogic/axg_s400.dts +++ b/arch/arm64/boot/dts/amlogic/axg_s400.dts @@ -366,8 +366,10 @@ reg = <0x0 0xffd24000 0x0 0x18>; interrupts = <0 26 1>; status = "okay"; - clocks = <&xtal>; - clock-names = "clk_uart"; + clocks = <&xtal + &clkc CLKID_UART0>; + clock-names = "clk_uart", + "clk_gate"; fifosize = < 128 >; pinctrl-names = "default"; pinctrl-0 = <&a_uart_pins>; @@ -378,8 +380,10 @@ reg = <0x0 0xffd23000 0x0 0x18>; interrupts = <0 75 1>; status = "disable"; - clocks = <&xtal>; - clock-names = "clk_uart"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; fifosize = < 64 >; pinctrl-names = "default"; pinctrl-0 = <&b_uart_pins>; diff --git a/arch/arm64/boot/dts/amlogic/axg_s420.dts b/arch/arm64/boot/dts/amlogic/axg_s420.dts index f39f960..832c330 100644 --- a/arch/arm64/boot/dts/amlogic/axg_s420.dts +++ b/arch/arm64/boot/dts/amlogic/axg_s420.dts @@ -280,8 +280,10 @@ reg = <0x0 0xffd24000 0x0 0x18>; interrupts = <0 26 1>; status = "okay"; - clocks = <&xtal>; - clock-names = "clk_uart"; + clocks = <&xtal + &clkc CLKID_UART0>; + clock-names = "clk_uart", + "clk_gate"; fifosize = < 128 >; pinctrl-names = "default"; pinctrl-0 = <&a_uart_pins>; @@ -292,8 +294,10 @@ reg = <0x0 0xffd23000 0x0 0x18>; interrupts = <0 75 1>; status = "disable"; - clocks = <&xtal>; - clock-names = "clk_uart"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; fifosize = < 64 >; pinctrl-names = "default"; pinctrl-0 = <&b_uart_pins>; diff --git a/drivers/amlogic/uart/meson_uart.c b/drivers/amlogic/uart/meson_uart.c index cefedfa..a691d4d 100644 --- a/drivers/amlogic/uart/meson_uart.c +++ b/drivers/amlogic/uart/meson_uart.c @@ -550,14 +550,15 @@ static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) dev_info(&pdev->dev, "ttyS%d use xtal(24M) %d change %ld to %ld\n", port->line, port->uartclk, mup->baud, baud); - val = (port->uartclk) / baud - 1; + val = (port->uartclk + baud / 2) / baud - 1; val |= (AML_UART_BAUD_USE|AML_UART_BAUD_XTAL |AML_UART_BAUD_XTAL_TICK); } else { dev_info(&pdev->dev, "ttyS%d use xtal(8M) %d change %ld to %ld\n", port->line, port->uartclk, mup->baud, baud); - val = (port->uartclk / 3) / baud - 1; + val = ((port->uartclk / 3) + baud / 2) / baud - 1; + val &= (~AML_UART_BAUD_XTAL_TICK); val |= (AML_UART_BAUD_USE|AML_UART_BAUD_XTAL); } } else { @@ -565,6 +566,7 @@ static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) port->line, port->uartclk, mup->baud, baud); val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1; + val &= (~(AML_UART_BAUD_XTAL|AML_UART_BAUD_XTAL_TICK)); val |= AML_UART_BAUD_USE; } writel(val, port->membase + AML_UART_REG5); @@ -1069,18 +1071,26 @@ static int meson_uart_probe(struct platform_device *pdev) spin_lock_init(&mup->wr_lock); port = &mup->port; #ifdef CONFIG_AMLOGIC_CLK + clk = devm_clk_get(&pdev->dev, "clk_gate"); + if (IS_ERR(clk)) { + pr_err("%s: clock gate not found\n", dev_name(&pdev->dev)); + /* return PTR_ERR(clk); */ + } else { + ret = clk_prepare_enable(clk); + if (ret) { + pr_err("uart: clock failed to prepare+enable: %d\n", + ret); + clk_put(clk); + /* return ret; */ + } + } clk = devm_clk_get(&pdev->dev, "clk_uart"); if (IS_ERR(clk)) { - pr_err("%s: clock not found\n", dev_name(&pdev->dev)); + pr_err("%s: clock source not found\n", dev_name(&pdev->dev)); /* return PTR_ERR(clk); */ } - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("uart: clock failed to prepare+enable: %d\n", ret); - clk_put(clk); - /* return ret; */ - } + port->uartclk = clk_get_rate(clk); #endif port->fifosize = 64; @@ -1094,7 +1104,7 @@ static int meson_uart_probe(struct platform_device *pdev) xtal_tick_en = of_read_ulong(prop, 1); } xtal_tick_en = 0; - port->uartclk = 24000000; + port->iotype = UPIO_MEM; port->mapbase = res_mem->start; port->irq = res_irq->start; -- 2.7.4