From 50cf18700e1128ac3ee3d0b015c5decced19066e Mon Sep 17 00:00:00 2001 From: Louis Le Gall Date: Thu, 6 Oct 2011 16:18:35 +0100 Subject: [PATCH] intel_sst: Allow automatic DMA LLI for I2S SSP The DMA LLI stall after first block if the CSR2 register in LPE Shim are not configured properly. The LPE Shim register are not accessible from SSP I2S driver, only by SST driver. Modification will not impact other component, change will be done for SSP0 and SSP1. Change-Id: I502931a1bef9809bbd35c39845416af6d80843fb Signed-off-by: Louis Le Gall --- drivers/staging/intel_sst/intel_sst.c | 5 +++++ drivers/staging/intel_sst/intel_sst_common.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/staging/intel_sst/intel_sst.c b/drivers/staging/intel_sst/intel_sst.c index 8b6d022..987f1d5 100644 --- a/drivers/staging/intel_sst/intel_sst.c +++ b/drivers/staging/intel_sst/intel_sst.c @@ -325,6 +325,7 @@ static int __devinit intel_sst_probe(struct pci_dev *pci, } } else if (sst_drv_ctx->pci_id == SST_MFLD_PCI_ID) { u32 csr; + u32 csr2; u32 clkctl; /*allocate mem for fw context save during suspend*/ @@ -348,6 +349,10 @@ static int __devinit intel_sst_probe(struct pci_dev *pci, clkctl |= ((1<<16)|(1<<17)); sst_shim_write(sst_drv_ctx->shim, SST_CLKCTL, clkctl); + /* set SSP0 & SSP1 disable DMA Finish*/ + csr2 = sst_shim_read(sst_drv_ctx->shim, SST_CSR2); + csr2 |= BIT(1)|BIT(2); + sst_shim_write(sst_drv_ctx->shim, SST_CSR2, csr2); } sst_drv_ctx->lpe_stalled = 0; pci_set_drvdata(pci, sst_drv_ctx); diff --git a/drivers/staging/intel_sst/intel_sst_common.h b/drivers/staging/intel_sst/intel_sst_common.h index 5a070b6..686308c 100644 --- a/drivers/staging/intel_sst/intel_sst_common.h +++ b/drivers/staging/intel_sst/intel_sst_common.h @@ -70,6 +70,7 @@ enum sst_states { #define SST_ISRD 0x20 /* dummy register for shim workaround */ #define SST_SHIM_SIZE 0X44 #define SST_CLKCTL 0x78 +#define SST_CSR2 0x80 #define SPI_MODE_ENABLE_BASE_ADDR 0xffae4000 #define FW_SIGNATURE_SIZE 4 -- 2.7.4