From 505eb498bd78f560354b2f36d3b2ae77115d58ab Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Fri, 19 Aug 2016 19:17:28 +0000 Subject: [PATCH] [Hexagon] Allow i1 values for 'r' constraint in inline-asm llvm-svn: 279302 --- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 5 +++-- llvm/test/CodeGen/Hexagon/inline-asm-i1.ll | 10 ++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/Hexagon/inline-asm-i1.ll diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 6ba9a31..218f5c3 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2987,9 +2987,10 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( switch (VT.SimpleTy) { default: llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type"); - case MVT::i32: - case MVT::i16: + case MVT::i1: case MVT::i8: + case MVT::i16: + case MVT::i32: case MVT::f32: return std::make_pair(0U, &Hexagon::IntRegsRegClass); case MVT::i64: diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll b/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll new file mode 100644 index 0000000..c88c30e --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll @@ -0,0 +1,10 @@ +target triple = "hexagon" + +define hidden void @fred() #0 { +entry: + %0 = call { i32, i32 } asm sideeffect " $0 = usr\0A $1 = $2\0A $0 = insert($1, #1, #16)\0Ausr = $0 \0A", "=&r,=&r,r"(i1 undef) #1 + ret void +} + +attributes #0 = { nounwind "target-cpu"="hexagonv60" } +attributes #1 = { nounwind } -- 2.7.4