From 5002863ab0d6d16e6f948e712554c48593770341 Mon Sep 17 00:00:00 2001
From: Sid Manning <sidneym@quicinc.com>
Date: Mon, 6 Apr 2020 12:40:19 -0500
Subject: [PATCH] Support bfdname "elf32-hexagon".

Add support and update testcases.

Differential Revision: https://reviews.llvm.org/D77579
---
 llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test | 6 ++++++
 llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test   | 7 +++++++
 llvm/tools/llvm-objcopy/CopyConfig.cpp                     | 1 +
 3 files changed, 14 insertions(+)

diff --git a/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test b/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
index 1ca911a..f7073f0 100644
--- a/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
@@ -30,11 +30,15 @@
 # RUN: llvm-objcopy -I binary -O elf32-sparcel %t.txt %t.sparcel.o
 # RUN: llvm-readobj --file-headers %t.sparcel.o | FileCheck %s --check-prefixes=CHECK,LE,SPARCEL,32
 
+# RUN: llvm-objcopy -I binary -O elf32-hexagon %t.txt %t.hexagon.o
+# RUN: llvm-readobj --file-headers %t.hexagon.o | FileCheck %s --check-prefixes=CHECK,LE,HEXAGON,32
+
 # CHECK: Format:
 # 32-SAME:      elf32-
 # 64-SAME:      elf64-
 # AARCH64-SAME: littleaarch64
 # ARM-SAME:     littlearm
+# HEXAGON-SAME: hexagon
 # I386-SAME:    i386
 # MIPS-SAME:    mips{{$}}
 # RISCV32-SAME: riscv{{$}}
@@ -47,6 +51,7 @@
 
 # AARCH64-NEXT: Arch: aarch64
 # ARM-NEXT:     Arch: arm
+# HEXAGON-NEXT: Arch: hexagon
 # I386-NEXT:    Arch: i386
 # MIPS-NEXT:    Arch: mips{{$}}
 # PPC-NEXT:     Arch: powerpc{{$}}
@@ -79,6 +84,7 @@
 ## We fill in the field regardless of -B.
 # AARCH64-NEXT:   Machine: EM_AARCH64 (0xB7)
 # ARM-NEXT:       Machine: EM_ARM (0x28)
+# HEXAGON-NEXT:   Machine: EM_HEXAGON (0xA4)
 # I386-NEXT:      Machine: EM_386 (0x3)
 # MIPS-NEXT:      Machine: EM_MIPS (0x8)
 # PPC-NEXT:       Machine: EM_PPC (0x14)
diff --git a/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test b/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
index f2c3739..e4ab2dd 100644
--- a/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
@@ -105,6 +105,10 @@
 # RUN: llvm-readobj --file-headers %t.elf32_sparcel.o | FileCheck %s --check-prefixes=CHECK,LE,SPARCEL,32,SYSV
 # RUN: llvm-readobj --file-headers %t.elf32_sparcel.dwo | FileCheck %s --check-prefixes=CHECK,LE,SPARCEL,32,SYSV
 
+# RUN: llvm-objcopy %t.o -O elf32-hexagon %t.elf32_hexagon.o --split-dwo=%t.elf32_hexagon.dwo
+# RUN: llvm-readobj --file-headers %t.elf32_hexagon.o | FileCheck %s --check-prefixes=CHECK,LE,HEXAGON,32,SYSV
+# RUN: llvm-readobj --file-headers %t.elf32_hexagon.dwo | FileCheck %s --check-prefixes=CHECK,LE,HEXAGON,32,SYSV
+
 !ELF
 FileHeader:
   Class:           ELFCLASS32
@@ -139,6 +143,7 @@ Symbols:
 # IAMCU-SAME:   iamcu
 # AARCH-SAME:   aarch64
 # ARM-SAME:     littlearm
+# HEXAGON-SAME: hexagon
 # MIPS-SAME:    mips
 # PPC-SAME:     powerpc{{$}}
 # PPC64BE-SAME: powerpc{{$}}
@@ -153,6 +158,7 @@ Symbols:
 # IAMCU-NEXT:    Arch: i386
 # AARCH-NEXT:    Arch: aarch64
 # ARM-NEXT:      Arch: arm
+# HEXAGON-NEXT:  Arch: hexagon
 # MIPSBE-NEXT:   Arch: mips{{$}}
 # MIPSLE-NEXT:   Arch: mipsel{{$}}
 # MIPS64BE-NEXT: Arch: mips64{{$}}
@@ -181,6 +187,7 @@ Symbols:
 
 # AARCH:   Machine: EM_AARCH64 (0xB7)
 # ARM:     Machine: EM_ARM (0x28)
+# HEXAGON: Machine: EM_HEXAGON (0xA4)
 # I386:    Machine: EM_386 (0x3)
 # IAMCU:   Machine: EM_IAMCU (0x6)
 # MIPS:    Machine: EM_MIPS (0x8)
diff --git a/llvm/tools/llvm-objcopy/CopyConfig.cpp b/llvm/tools/llvm-objcopy/CopyConfig.cpp
index 69d6180..df2fbbb 100644
--- a/llvm/tools/llvm-objcopy/CopyConfig.cpp
+++ b/llvm/tools/llvm-objcopy/CopyConfig.cpp
@@ -273,6 +273,7 @@ static const StringMap<MachineInfo> TargetMap{
     // SPARC
     {"elf32-sparc", {ELF::EM_SPARC, false, false}},
     {"elf32-sparcel", {ELF::EM_SPARC, false, true}},
+    {"elf32-hexagon", {ELF::EM_HEXAGON, false, true}},
 };
 
 static Expected<TargetInfo>
-- 
2.7.4