From 4fd9a3e7eba036eac5a972b268c38f3ed811e74d Mon Sep 17 00:00:00 2001 From: samin Date: Sat, 14 May 2022 19:04:01 +0800 Subject: [PATCH] dt-bingings:riscv_timer: timebase-frequency is 4M. JH7110 SOC riscv_timer frequency is 4M. FPGA is 2M. Signed-off-by: samin --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 4 ++-- arch/riscv/boot/dts/starfive/jh7110-fpga.dts | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 21945dd..265efea 100755 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -25,10 +25,10 @@ }; cpus { - timebase-frequency = <2000000>; + timebase-frequency = <4000000>; }; - memory@80000000 { + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0x1 0x0>; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110-fpga.dts b/arch/riscv/boot/dts/starfive/jh7110-fpga.dts index 9212525..18f27bb 100755 --- a/arch/riscv/boot/dts/starfive/jh7110-fpga.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-fpga.dts @@ -11,6 +11,10 @@ / { model = "StarFive JH7110 FPGA"; compatible = "starfive,jh7110-fpga", "starfive,jh7110"; + + cpus { + timebase-frequency = <2000000>; + }; }; &timer { -- 2.7.4