From 4f727ecefefbd180de10e25b3e74c03dce3f1e75 Mon Sep 17 00:00:00 2001 From: Le Ma Date: Wed, 29 Aug 2018 16:50:20 +0800 Subject: [PATCH] drm/amdgpu: add sdma 4.2.2 header files for Arcturus SDMA is the system DMA block. Signed-off-by: Le Ma Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- .../include/asic_reg/sdma0/sdma0_4_2_2_offset.h | 1051 +++++++ .../include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h | 3002 ++++++++++++++++++++ .../include/asic_reg/sdma1/sdma1_4_2_2_offset.h | 1043 +++++++ .../include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h | 2956 +++++++++++++++++++ .../include/asic_reg/sdma2/sdma2_4_2_2_offset.h | 1043 +++++++ .../include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h | 2956 +++++++++++++++++++ .../include/asic_reg/sdma3/sdma3_4_2_2_offset.h | 1043 +++++++ .../include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h | 2956 +++++++++++++++++++ .../include/asic_reg/sdma4/sdma4_4_2_2_offset.h | 1043 +++++++ .../include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h | 2956 +++++++++++++++++++ .../include/asic_reg/sdma5/sdma5_4_2_2_offset.h | 1043 +++++++ .../include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h | 2956 +++++++++++++++++++ .../include/asic_reg/sdma6/sdma6_4_2_2_offset.h | 1043 +++++++ .../include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h | 2956 +++++++++++++++++++ .../include/asic_reg/sdma7/sdma7_4_2_2_offset.h | 1043 +++++++ .../include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h | 2956 +++++++++++++++++++ 16 files changed, 32046 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h new file mode 100644 index 0000000..ff5df90 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h @@ -0,0 +1,1051 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_2_2_OFFSET_HEADER +#define _sdma0_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma0_sdma0dec +// base address: 0x4980 +#define mmSDMA0_UCODE_ADDR 0x0000 +#define mmSDMA0_UCODE_ADDR_BASE_IDX 0 +#define mmSDMA0_UCODE_DATA 0x0001 +#define mmSDMA0_UCODE_DATA_BASE_IDX 0 +#define mmSDMA0_VM_CNTL 0x0004 +#define mmSDMA0_VM_CNTL_BASE_IDX 0 +#define mmSDMA0_VM_CTX_LO 0x0005 +#define mmSDMA0_VM_CTX_LO_BASE_IDX 0 +#define mmSDMA0_VM_CTX_HI 0x0006 +#define mmSDMA0_VM_CTX_HI_BASE_IDX 0 +#define mmSDMA0_ACTIVE_FCN_ID 0x0007 +#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmSDMA0_VM_CTX_CNTL 0x0008 +#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 +#define mmSDMA0_VIRT_RESET_REQ 0x0009 +#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 +#define mmSDMA0_VF_ENABLE 0x000a +#define mmSDMA0_VF_ENABLE_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE0 0x000f +#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE1 0x0010 +#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE2 0x0011 +#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE3 0x0012 +#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 +#define mmSDMA0_MMHUB_CNTL 0x0013 +#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define mmSDMA0_POWER_CNTL 0x001a +#define mmSDMA0_POWER_CNTL_BASE_IDX 0 +#define mmSDMA0_CLK_CTRL 0x001b +#define mmSDMA0_CLK_CTRL_BASE_IDX 0 +#define mmSDMA0_CNTL 0x001c +#define mmSDMA0_CNTL_BASE_IDX 0 +#define mmSDMA0_CHICKEN_BITS 0x001d +#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 +#define mmSDMA0_GB_ADDR_CONFIG 0x001e +#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 +#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define mmSDMA0_RB_RPTR_FETCH 0x0022 +#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 +#define mmSDMA0_IB_OFFSET_FETCH 0x0023 +#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 +#define mmSDMA0_PROGRAM 0x0024 +#define mmSDMA0_PROGRAM_BASE_IDX 0 +#define mmSDMA0_STATUS_REG 0x0025 +#define mmSDMA0_STATUS_REG_BASE_IDX 0 +#define mmSDMA0_STATUS1_REG 0x0026 +#define mmSDMA0_STATUS1_REG_BASE_IDX 0 +#define mmSDMA0_RD_BURST_CNTL 0x0027 +#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 +#define mmSDMA0_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 +#define mmSDMA0_UCODE_CHECKSUM 0x0029 +#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 +#define mmSDMA0_F32_CNTL 0x002a +#define mmSDMA0_F32_CNTL_BASE_IDX 0 +#define mmSDMA0_FREEZE 0x002b +#define mmSDMA0_FREEZE_BASE_IDX 0 +#define mmSDMA0_PHASE0_QUANTUM 0x002c +#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 +#define mmSDMA0_PHASE1_QUANTUM 0x002d +#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 +#define mmSDMA_POWER_GATING 0x002e +#define mmSDMA_POWER_GATING_BASE_IDX 0 +#define mmSDMA_PGFSM_CONFIG 0x002f +#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 +#define mmSDMA_PGFSM_WRITE 0x0030 +#define mmSDMA_PGFSM_WRITE_BASE_IDX 0 +#define mmSDMA_PGFSM_READ 0x0031 +#define mmSDMA_PGFSM_READ_BASE_IDX 0 +#define mmSDMA0_EDC_CONFIG 0x0032 +#define mmSDMA0_EDC_CONFIG_BASE_IDX 0 +#define mmSDMA0_BA_THRESHOLD 0x0033 +#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 +#define mmSDMA0_ID 0x0034 +#define mmSDMA0_ID_BASE_IDX 0 +#define mmSDMA0_VERSION 0x0035 +#define mmSDMA0_VERSION_BASE_IDX 0 +#define mmSDMA0_EDC_COUNTER 0x0036 +#define mmSDMA0_EDC_COUNTER_BASE_IDX 0 +#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define mmSDMA0_STATUS2_REG 0x0038 +#define mmSDMA0_STATUS2_REG_BASE_IDX 0 +#define mmSDMA0_ATOMIC_CNTL 0x0039 +#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 +#define mmSDMA0_ATOMIC_PREOP_LO 0x003a +#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 +#define mmSDMA0_ATOMIC_PREOP_HI 0x003b +#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 +#define mmSDMA0_UTCL1_CNTL 0x003c +#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 +#define mmSDMA0_UTCL1_WATERMK 0x003d +#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_STATUS 0x003e +#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_STATUS 0x003f +#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV0 0x0040 +#define mmSDMA0_UTCL1_INV0_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV1 0x0041 +#define mmSDMA0_UTCL1_INV1_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV2 0x0042 +#define mmSDMA0_UTCL1_INV2_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 +#define mmSDMA0_UTCL1_TIMEOUT 0x0047 +#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 +#define mmSDMA0_UTCL1_PAGE 0x0048 +#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 +#define mmSDMA0_POWER_CNTL_IDLE 0x0049 +#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 +#define mmSDMA0_RELAX_ORDERING_LUT 0x004a +#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 +#define mmSDMA0_CHICKEN_BITS_2 0x004b +#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 +#define mmSDMA0_STATUS3_REG 0x004c +#define mmSDMA0_STATUS3_REG_BASE_IDX 0 +#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PHASE2_QUANTUM 0x004f +#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 +#define mmSDMA0_ERROR_LOG 0x0050 +#define mmSDMA0_ERROR_LOG_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG0 0x0051 +#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG1 0x0052 +#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG2 0x0053 +#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG3 0x0054 +#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 +#define mmSDMA0_F32_COUNTER 0x0055 +#define mmSDMA0_F32_COUNTER_BASE_IDX 0 +#define mmSDMA0_UNBREAKABLE 0x0056 +#define mmSDMA0_UNBREAKABLE_BASE_IDX 0 +#define mmSDMA0_PERFMON_CNTL 0x0057 +#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 +#define mmSDMA0_CRD_CNTL 0x005b +#define mmSDMA0_CRD_CNTL_BASE_IDX 0 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmSDMA0_ULV_CNTL 0x005e +#define mmSDMA0_ULV_CNTL_BASE_IDX 0 +#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 +#define mmSDMA0_GFX_RB_CNTL 0x0080 +#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_RB_BASE 0x0081 +#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 +#define mmSDMA0_GFX_RB_BASE_HI 0x0082 +#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR 0x0083 +#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR 0x0085 +#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_IB_CNTL 0x008a +#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_IB_RPTR 0x008b +#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_GFX_IB_OFFSET 0x008c +#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_GFX_IB_BASE_LO 0x008d +#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_GFX_IB_BASE_HI 0x008e +#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_GFX_IB_SIZE 0x008f +#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_GFX_SKIP_CNTL 0x0090 +#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL 0x0092 +#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 +#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_STATUS 0x00a8 +#define mmSDMA0_GFX_STATUS_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_GFX_WATERMARK 0x00aa +#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_GFX_PREEMPT 0x00b0 +#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 +#define mmSDMA0_GFX_DUMMY_REG 0x00b1 +#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_CNTL 0x00d8 +#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_BASE 0x00d9 +#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_BASE_HI 0x00da +#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR 0x00db +#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR 0x00dd +#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_CNTL 0x00e2 +#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_RPTR 0x00e3 +#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_SIZE 0x00e7 +#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL 0x00ea +#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 +#define mmSDMA0_PAGE_STATUS 0x0100 +#define mmSDMA0_PAGE_STATUS_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_PAGE_WATERMARK 0x0102 +#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_PAGE_PREEMPT 0x0108 +#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 +#define mmSDMA0_PAGE_DUMMY_REG 0x0109 +#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_CNTL 0x0130 +#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_BASE 0x0131 +#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR 0x0133 +#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR 0x0135 +#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_CNTL 0x013a +#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_RPTR 0x013b +#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_OFFSET 0x013c +#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_BASE_LO 0x013d +#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_BASE_HI 0x013e +#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_SIZE 0x013f +#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL 0x0142 +#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC0_STATUS 0x0158 +#define mmSDMA0_RLC0_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC0_WATERMARK 0x015a +#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC0_PREEMPT 0x0160 +#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC0_DUMMY_REG 0x0161 +#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_CNTL 0x0188 +#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_BASE 0x0189 +#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_BASE_HI 0x018a +#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR 0x018b +#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR 0x018d +#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_CNTL 0x0192 +#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_RPTR 0x0193 +#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_OFFSET 0x0194 +#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_SIZE 0x0197 +#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL 0x019a +#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC1_STATUS 0x01b0 +#define mmSDMA0_RLC1_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC1_WATERMARK 0x01b2 +#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC1_PREEMPT 0x01b8 +#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_CNTL 0x01e0 +#define mmSDMA0_RLC2_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_BASE 0x01e1 +#define mmSDMA0_RLC2_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_RPTR 0x01e3 +#define mmSDMA0_RLC2_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_WPTR 0x01e5 +#define mmSDMA0_RLC2_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_CNTL 0x01ea +#define mmSDMA0_RLC2_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_RPTR 0x01eb +#define mmSDMA0_RLC2_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_OFFSET 0x01ec +#define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_SIZE 0x01ef +#define mmSDMA0_RLC2_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC2_DOORBELL 0x01f2 +#define mmSDMA0_RLC2_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC2_STATUS 0x0208 +#define mmSDMA0_RLC2_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC2_WATERMARK 0x020a +#define mmSDMA0_RLC2_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC2_PREEMPT 0x0210 +#define mmSDMA0_RLC2_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC2_DUMMY_REG 0x0211 +#define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_CNTL 0x0238 +#define mmSDMA0_RLC3_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_BASE 0x0239 +#define mmSDMA0_RLC3_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_BASE_HI 0x023a +#define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_RPTR 0x023b +#define mmSDMA0_RLC3_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_WPTR 0x023d +#define mmSDMA0_RLC3_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_CNTL 0x0242 +#define mmSDMA0_RLC3_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_RPTR 0x0243 +#define mmSDMA0_RLC3_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_OFFSET 0x0244 +#define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_SIZE 0x0247 +#define mmSDMA0_RLC3_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC3_DOORBELL 0x024a +#define mmSDMA0_RLC3_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC3_STATUS 0x0260 +#define mmSDMA0_RLC3_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC3_WATERMARK 0x0262 +#define mmSDMA0_RLC3_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC3_PREEMPT 0x0268 +#define mmSDMA0_RLC3_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC3_DUMMY_REG 0x0269 +#define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_CNTL 0x0290 +#define mmSDMA0_RLC4_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_BASE 0x0291 +#define mmSDMA0_RLC4_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_RPTR 0x0293 +#define mmSDMA0_RLC4_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_WPTR 0x0295 +#define mmSDMA0_RLC4_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_CNTL 0x029a +#define mmSDMA0_RLC4_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_RPTR 0x029b +#define mmSDMA0_RLC4_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_OFFSET 0x029c +#define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_BASE_LO 0x029d +#define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_BASE_HI 0x029e +#define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_SIZE 0x029f +#define mmSDMA0_RLC4_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC4_DOORBELL 0x02a2 +#define mmSDMA0_RLC4_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC4_STATUS 0x02b8 +#define mmSDMA0_RLC4_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC4_WATERMARK 0x02ba +#define mmSDMA0_RLC4_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC4_PREEMPT 0x02c0 +#define mmSDMA0_RLC4_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_CNTL 0x02e8 +#define mmSDMA0_RLC5_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_BASE 0x02e9 +#define mmSDMA0_RLC5_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_RPTR 0x02eb +#define mmSDMA0_RLC5_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_WPTR 0x02ed +#define mmSDMA0_RLC5_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_CNTL 0x02f2 +#define mmSDMA0_RLC5_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_RPTR 0x02f3 +#define mmSDMA0_RLC5_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_SIZE 0x02f7 +#define mmSDMA0_RLC5_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC5_DOORBELL 0x02fa +#define mmSDMA0_RLC5_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC5_STATUS 0x0310 +#define mmSDMA0_RLC5_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC5_WATERMARK 0x0312 +#define mmSDMA0_RLC5_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC5_PREEMPT 0x0318 +#define mmSDMA0_RLC5_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC5_DUMMY_REG 0x0319 +#define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_CNTL 0x0340 +#define mmSDMA0_RLC6_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_BASE 0x0341 +#define mmSDMA0_RLC6_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_RPTR 0x0343 +#define mmSDMA0_RLC6_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_WPTR 0x0345 +#define mmSDMA0_RLC6_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_CNTL 0x034a +#define mmSDMA0_RLC6_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_RPTR 0x034b +#define mmSDMA0_RLC6_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_OFFSET 0x034c +#define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_BASE_LO 0x034d +#define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_BASE_HI 0x034e +#define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_SIZE 0x034f +#define mmSDMA0_RLC6_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC6_DOORBELL 0x0352 +#define mmSDMA0_RLC6_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC6_STATUS 0x0368 +#define mmSDMA0_RLC6_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC6_WATERMARK 0x036a +#define mmSDMA0_RLC6_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC6_PREEMPT 0x0370 +#define mmSDMA0_RLC6_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC6_DUMMY_REG 0x0371 +#define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_CNTL 0x0398 +#define mmSDMA0_RLC7_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_BASE 0x0399 +#define mmSDMA0_RLC7_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_BASE_HI 0x039a +#define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_RPTR 0x039b +#define mmSDMA0_RLC7_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_WPTR 0x039d +#define mmSDMA0_RLC7_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_CNTL 0x03a2 +#define mmSDMA0_RLC7_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_RPTR 0x03a3 +#define mmSDMA0_RLC7_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_SIZE 0x03a7 +#define mmSDMA0_RLC7_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC7_DOORBELL 0x03aa +#define mmSDMA0_RLC7_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC7_STATUS 0x03c0 +#define mmSDMA0_RLC7_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC7_WATERMARK 0x03c2 +#define mmSDMA0_RLC7_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC7_PREEMPT 0x03c8 +#define mmSDMA0_RLC7_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h new file mode 100644 index 0000000..9feb67b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h @@ -0,0 +1,3002 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_2_2_SH_MASK_HEADER +#define _sdma0_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma0_sdma0dec +//SDMA0_UCODE_ADDR +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA0_UCODE_DATA +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_VM_CNTL +#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA0_VM_CTX_LO +#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_VM_CTX_HI +#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_ACTIVE_FCN_ID +#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA0_VM_CTX_CNTL +#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA0_VIRT_RESET_REQ +#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA0_VF_ENABLE +#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA0_CONTEXT_REG_TYPE0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA0_CONTEXT_REG_TYPE1 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA0_CONTEXT_REG_TYPE2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA0_CONTEXT_REG_TYPE3 +#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_PUB_REG_TYPE0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE2 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE3 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA0_MMHUB_CNTL +#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA0_CONTEXT_GROUP_BOUNDARY +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_POWER_CNTL +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L +//SDMA0_CLK_CTRL +#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA0_CNTL +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA0_CHICKEN_BITS +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA0_GB_ADDR_CONFIG +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_GB_ADDR_CONFIG_READ +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_RB_RPTR_FETCH_HI +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA0_RB_RPTR_FETCH +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA0_IB_OFFSET_FETCH +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA0_PROGRAM +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA0_STATUS_REG +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA0_STATUS1_REG +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA0_RD_BURST_CNTL +#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA0_HBM_PAGE_CONFIG +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA0_UCODE_CHECKSUM +#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA0_F32_CNTL +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L +//SDMA0_FREEZE +#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA0_PHASE0_QUANTUM +#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_PHASE1_QUANTUM +#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA_POWER_GATING +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 +#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L +#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L +//SDMA_PGFSM_CONFIG +#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL +#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L +#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L +#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L +#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L +#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L +#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L +#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L +//SDMA_PGFSM_WRITE +#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL +//SDMA_PGFSM_READ +#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL +//SDMA0_EDC_CONFIG +#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA0_BA_THRESHOLD +#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA0_ID +#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA0_VERSION +#define SDMA0_VERSION__MINVER__SHIFT 0x0 +#define SDMA0_VERSION__MAJVER__SHIFT 0x8 +#define SDMA0_VERSION__REV__SHIFT 0x10 +#define SDMA0_VERSION__MINVER_MASK 0x0000007FL +#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA0_VERSION__REV_MASK 0x003F0000L +//SDMA0_EDC_COUNTER +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA0_EDC_COUNTER_CLEAR +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA0_STATUS2_REG +#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA0_ATOMIC_CNTL +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA0_ATOMIC_PREOP_LO +#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_ATOMIC_PREOP_HI +#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_CNTL +#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA0_UTCL1_WATERMK +#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA0_UTCL1_RD_STATUS +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA0_UTCL1_WR_STATUS +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA0_UTCL1_INV0 +#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA0_UTCL1_INV1 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_INV2 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK1 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_WR_XNACK0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_WR_XNACK1 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_TIMEOUT +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA0_UTCL1_PAGE +#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA0_POWER_CNTL_IDLE +#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA0_RELAX_ORDERING_LUT +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA0_CHICKEN_BITS_2 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA0_STATUS3_REG +#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA0_PHYSICAL_ADDR_LO +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA0_PHYSICAL_ADDR_HI +#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA0_PHASE2_QUANTUM +#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_ERROR_LOG +#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA0_PUB_DUMMY_REG0 +#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG1 +#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG2 +#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG3 +#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA0_F32_COUNTER +#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA0_UNBREAKABLE +#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA0_PERFMON_CNTL +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA0_PERFCOUNTER0_RESULT +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER1_RESULT +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA0_CRD_CNTL +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA0_GPU_IOV_VIOLATION_LOG +#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA0_ULV_CNTL +#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA0_EA_DBIT_ADDR_DATA +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_EA_DBIT_ADDR_INDEX +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA0_GPU_IOV_VIOLATION_LOG2 +#define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA0_GFX_RB_CNTL +#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_GFX_RB_BASE +#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_BASE_HI +#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_GFX_RB_RPTR +#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_HI +#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR +#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_HI +#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_CNTL +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_GFX_RB_RPTR_ADDR_HI +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_ADDR_LO +#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_IB_CNTL +#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_GFX_IB_RPTR +#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_OFFSET +#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_BASE_LO +#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_GFX_IB_BASE_HI +#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SIZE +#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_GFX_SKIP_CNTL +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_GFX_CONTEXT_STATUS +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_GFX_DOORBELL +#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_GFX_CONTEXT_CNTL +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA0_GFX_STATUS +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_GFX_DOORBELL_LOG +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_GFX_WATERMARK +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_GFX_DOORBELL_OFFSET +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_GFX_CSA_ADDR_LO +#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_CSA_ADDR_HI +#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SUB_REMAIN +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_GFX_PREEMPT +#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_GFX_DUMMY_REG +#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_RB_AQL_CNTL +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_GFX_MINOR_PTR_UPDATE +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_GFX_MIDCMD_DATA0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA1 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA2 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA3 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA4 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA5 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA6 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA7 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA8 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_CNTL +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_PAGE_RB_CNTL +#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_PAGE_RB_BASE +#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_BASE_HI +#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_PAGE_RB_RPTR +#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_RPTR_HI +#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR +#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_HI +#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_CNTL +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_PAGE_RB_RPTR_ADDR_HI +#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_RPTR_ADDR_LO +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_IB_CNTL +#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_PAGE_IB_RPTR +#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_PAGE_IB_OFFSET +#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_PAGE_IB_BASE_LO +#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_PAGE_IB_BASE_HI +#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_IB_SIZE +#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_PAGE_SKIP_CNTL +#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_PAGE_CONTEXT_STATUS +#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_PAGE_DOORBELL +#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_PAGE_STATUS +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_PAGE_DOORBELL_LOG +#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_PAGE_WATERMARK +#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_PAGE_DOORBELL_OFFSET +#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_PAGE_CSA_ADDR_LO +#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_CSA_ADDR_HI +#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_IB_SUB_REMAIN +#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_PAGE_PREEMPT +#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_PAGE_DUMMY_REG +#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_RB_AQL_CNTL +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_PAGE_MINOR_PTR_UPDATE +#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_PAGE_MIDCMD_DATA0 +#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA1 +#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA2 +#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA3 +#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA4 +#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA5 +#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA6 +#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA7 +#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA8 +#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_CNTL +#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC0_RB_CNTL +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC0_RB_BASE +#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_BASE_HI +#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC0_RB_RPTR +#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_HI +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR +#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_HI +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_CNTL +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC0_RB_RPTR_ADDR_HI +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_ADDR_LO +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_IB_CNTL +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC0_IB_RPTR +#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_OFFSET +#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_BASE_LO +#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC0_IB_BASE_HI +#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SIZE +#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC0_SKIP_CNTL +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC0_CONTEXT_STATUS +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC0_DOORBELL +#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC0_STATUS +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC0_DOORBELL_LOG +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC0_WATERMARK +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC0_DOORBELL_OFFSET +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC0_CSA_ADDR_LO +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_CSA_ADDR_HI +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SUB_REMAIN +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC0_PREEMPT +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC0_DUMMY_REG +#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_RB_AQL_CNTL +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC0_MINOR_PTR_UPDATE +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC0_MIDCMD_DATA0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA1 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA2 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA3 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA4 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA5 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA6 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA7 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA8 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_CNTL +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC1_RB_CNTL +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC1_RB_BASE +#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_BASE_HI +#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC1_RB_RPTR +#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_HI +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR +#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_HI +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_CNTL +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC1_RB_RPTR_ADDR_HI +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_ADDR_LO +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_IB_CNTL +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC1_IB_RPTR +#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_OFFSET +#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_BASE_LO +#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC1_IB_BASE_HI +#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SIZE +#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC1_SKIP_CNTL +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC1_CONTEXT_STATUS +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC1_DOORBELL +#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC1_STATUS +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC1_DOORBELL_LOG +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC1_WATERMARK +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC1_DOORBELL_OFFSET +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC1_CSA_ADDR_LO +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_CSA_ADDR_HI +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SUB_REMAIN +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC1_PREEMPT +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC1_DUMMY_REG +#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_RB_AQL_CNTL +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC1_MINOR_PTR_UPDATE +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC1_MIDCMD_DATA0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA1 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA2 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA3 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA4 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA5 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA6 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA7 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA8 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_CNTL +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC2_RB_CNTL +#define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC2_RB_BASE +#define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_BASE_HI +#define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC2_RB_RPTR +#define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_RPTR_HI +#define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR +#define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_HI +#define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_POLL_CNTL +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC2_RB_RPTR_ADDR_HI +#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_RPTR_ADDR_LO +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC2_IB_CNTL +#define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC2_IB_RPTR +#define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC2_IB_OFFSET +#define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC2_IB_BASE_LO +#define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC2_IB_BASE_HI +#define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_IB_SIZE +#define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC2_SKIP_CNTL +#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC2_CONTEXT_STATUS +#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC2_DOORBELL +#define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC2_STATUS +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC2_DOORBELL_LOG +#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC2_WATERMARK +#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC2_DOORBELL_OFFSET +#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC2_CSA_ADDR_LO +#define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC2_CSA_ADDR_HI +#define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_IB_SUB_REMAIN +#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC2_PREEMPT +#define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC2_DUMMY_REG +#define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC2_RB_AQL_CNTL +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC2_MINOR_PTR_UPDATE +#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC2_MIDCMD_DATA0 +#define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA1 +#define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA2 +#define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA3 +#define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA4 +#define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA5 +#define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA6 +#define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA7 +#define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA8 +#define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_CNTL +#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC3_RB_CNTL +#define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC3_RB_BASE +#define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_BASE_HI +#define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC3_RB_RPTR +#define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_RPTR_HI +#define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR +#define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_HI +#define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_POLL_CNTL +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC3_RB_RPTR_ADDR_HI +#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_RPTR_ADDR_LO +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC3_IB_CNTL +#define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC3_IB_RPTR +#define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC3_IB_OFFSET +#define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC3_IB_BASE_LO +#define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC3_IB_BASE_HI +#define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_IB_SIZE +#define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC3_SKIP_CNTL +#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC3_CONTEXT_STATUS +#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC3_DOORBELL +#define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC3_STATUS +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC3_DOORBELL_LOG +#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC3_WATERMARK +#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC3_DOORBELL_OFFSET +#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC3_CSA_ADDR_LO +#define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC3_CSA_ADDR_HI +#define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_IB_SUB_REMAIN +#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC3_PREEMPT +#define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC3_DUMMY_REG +#define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC3_RB_AQL_CNTL +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC3_MINOR_PTR_UPDATE +#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC3_MIDCMD_DATA0 +#define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA1 +#define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA2 +#define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA3 +#define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA4 +#define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA5 +#define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA6 +#define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA7 +#define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA8 +#define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_CNTL +#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC4_RB_CNTL +#define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC4_RB_BASE +#define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_BASE_HI +#define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC4_RB_RPTR +#define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_RPTR_HI +#define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR +#define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_HI +#define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_POLL_CNTL +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC4_RB_RPTR_ADDR_HI +#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_RPTR_ADDR_LO +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC4_IB_CNTL +#define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC4_IB_RPTR +#define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC4_IB_OFFSET +#define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC4_IB_BASE_LO +#define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC4_IB_BASE_HI +#define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_IB_SIZE +#define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC4_SKIP_CNTL +#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC4_CONTEXT_STATUS +#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC4_DOORBELL +#define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC4_STATUS +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC4_DOORBELL_LOG +#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC4_WATERMARK +#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC4_DOORBELL_OFFSET +#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC4_CSA_ADDR_LO +#define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC4_CSA_ADDR_HI +#define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_IB_SUB_REMAIN +#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC4_PREEMPT +#define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC4_DUMMY_REG +#define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC4_RB_AQL_CNTL +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC4_MINOR_PTR_UPDATE +#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC4_MIDCMD_DATA0 +#define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA1 +#define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA2 +#define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA3 +#define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA4 +#define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA5 +#define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA6 +#define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA7 +#define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA8 +#define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_CNTL +#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC5_RB_CNTL +#define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC5_RB_BASE +#define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_BASE_HI +#define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC5_RB_RPTR +#define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_RPTR_HI +#define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR +#define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_HI +#define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_POLL_CNTL +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC5_RB_RPTR_ADDR_HI +#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_RPTR_ADDR_LO +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC5_IB_CNTL +#define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC5_IB_RPTR +#define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC5_IB_OFFSET +#define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC5_IB_BASE_LO +#define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC5_IB_BASE_HI +#define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_IB_SIZE +#define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC5_SKIP_CNTL +#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC5_CONTEXT_STATUS +#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC5_DOORBELL +#define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC5_STATUS +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC5_DOORBELL_LOG +#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC5_WATERMARK +#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC5_DOORBELL_OFFSET +#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC5_CSA_ADDR_LO +#define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC5_CSA_ADDR_HI +#define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_IB_SUB_REMAIN +#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC5_PREEMPT +#define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC5_DUMMY_REG +#define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC5_RB_AQL_CNTL +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC5_MINOR_PTR_UPDATE +#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC5_MIDCMD_DATA0 +#define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA1 +#define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA2 +#define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA3 +#define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA4 +#define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA5 +#define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA6 +#define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA7 +#define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA8 +#define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_CNTL +#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC6_RB_CNTL +#define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC6_RB_BASE +#define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_BASE_HI +#define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC6_RB_RPTR +#define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_RPTR_HI +#define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR +#define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_HI +#define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_POLL_CNTL +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC6_RB_RPTR_ADDR_HI +#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_RPTR_ADDR_LO +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC6_IB_CNTL +#define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC6_IB_RPTR +#define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC6_IB_OFFSET +#define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC6_IB_BASE_LO +#define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC6_IB_BASE_HI +#define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_IB_SIZE +#define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC6_SKIP_CNTL +#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC6_CONTEXT_STATUS +#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC6_DOORBELL +#define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC6_STATUS +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC6_DOORBELL_LOG +#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC6_WATERMARK +#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC6_DOORBELL_OFFSET +#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC6_CSA_ADDR_LO +#define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC6_CSA_ADDR_HI +#define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_IB_SUB_REMAIN +#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC6_PREEMPT +#define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC6_DUMMY_REG +#define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC6_RB_AQL_CNTL +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC6_MINOR_PTR_UPDATE +#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC6_MIDCMD_DATA0 +#define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA1 +#define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA2 +#define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA3 +#define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA4 +#define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA5 +#define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA6 +#define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA7 +#define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA8 +#define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_CNTL +#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC7_RB_CNTL +#define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC7_RB_BASE +#define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_BASE_HI +#define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC7_RB_RPTR +#define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_RPTR_HI +#define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR +#define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_HI +#define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_POLL_CNTL +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC7_RB_RPTR_ADDR_HI +#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_RPTR_ADDR_LO +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC7_IB_CNTL +#define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC7_IB_RPTR +#define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC7_IB_OFFSET +#define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC7_IB_BASE_LO +#define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC7_IB_BASE_HI +#define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_IB_SIZE +#define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC7_SKIP_CNTL +#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC7_CONTEXT_STATUS +#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC7_DOORBELL +#define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC7_STATUS +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC7_DOORBELL_LOG +#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC7_WATERMARK +#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC7_DOORBELL_OFFSET +#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC7_CSA_ADDR_LO +#define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC7_CSA_ADDR_HI +#define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_IB_SUB_REMAIN +#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC7_PREEMPT +#define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC7_DUMMY_REG +#define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC7_RB_AQL_CNTL +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC7_MINOR_PTR_UPDATE +#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC7_MIDCMD_DATA0 +#define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA1 +#define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA2 +#define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA3 +#define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA4 +#define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA5 +#define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA6 +#define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA7 +#define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA8 +#define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_CNTL +#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h new file mode 100644 index 0000000..681233a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma1_4_2_2_OFFSET_HEADER +#define _sdma1_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma1_sdma1dec +// base address: 0x6180 +#define mmSDMA1_UCODE_ADDR 0x0000 +#define mmSDMA1_UCODE_ADDR_BASE_IDX 0 +#define mmSDMA1_UCODE_DATA 0x0001 +#define mmSDMA1_UCODE_DATA_BASE_IDX 0 +#define mmSDMA1_VM_CNTL 0x0004 +#define mmSDMA1_VM_CNTL_BASE_IDX 0 +#define mmSDMA1_VM_CTX_LO 0x0005 +#define mmSDMA1_VM_CTX_LO_BASE_IDX 0 +#define mmSDMA1_VM_CTX_HI 0x0006 +#define mmSDMA1_VM_CTX_HI_BASE_IDX 0 +#define mmSDMA1_ACTIVE_FCN_ID 0x0007 +#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmSDMA1_VM_CTX_CNTL 0x0008 +#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 +#define mmSDMA1_VIRT_RESET_REQ 0x0009 +#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 +#define mmSDMA1_VF_ENABLE 0x000a +#define mmSDMA1_VF_ENABLE_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE0 0x000f +#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE1 0x0010 +#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE2 0x0011 +#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE3 0x0012 +#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 +#define mmSDMA1_MMHUB_CNTL 0x0013 +#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 +#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define mmSDMA1_POWER_CNTL 0x001a +#define mmSDMA1_POWER_CNTL_BASE_IDX 0 +#define mmSDMA1_CLK_CTRL 0x001b +#define mmSDMA1_CLK_CTRL_BASE_IDX 0 +#define mmSDMA1_CNTL 0x001c +#define mmSDMA1_CNTL_BASE_IDX 0 +#define mmSDMA1_CHICKEN_BITS 0x001d +#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 +#define mmSDMA1_GB_ADDR_CONFIG 0x001e +#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 +#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define mmSDMA1_RB_RPTR_FETCH 0x0022 +#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 +#define mmSDMA1_IB_OFFSET_FETCH 0x0023 +#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 +#define mmSDMA1_PROGRAM 0x0024 +#define mmSDMA1_PROGRAM_BASE_IDX 0 +#define mmSDMA1_STATUS_REG 0x0025 +#define mmSDMA1_STATUS_REG_BASE_IDX 0 +#define mmSDMA1_STATUS1_REG 0x0026 +#define mmSDMA1_STATUS1_REG_BASE_IDX 0 +#define mmSDMA1_RD_BURST_CNTL 0x0027 +#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 +#define mmSDMA1_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 +#define mmSDMA1_UCODE_CHECKSUM 0x0029 +#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 +#define mmSDMA1_F32_CNTL 0x002a +#define mmSDMA1_F32_CNTL_BASE_IDX 0 +#define mmSDMA1_FREEZE 0x002b +#define mmSDMA1_FREEZE_BASE_IDX 0 +#define mmSDMA1_PHASE0_QUANTUM 0x002c +#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 +#define mmSDMA1_PHASE1_QUANTUM 0x002d +#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 +#define mmSDMA1_EDC_CONFIG 0x0032 +#define mmSDMA1_EDC_CONFIG_BASE_IDX 0 +#define mmSDMA1_BA_THRESHOLD 0x0033 +#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 +#define mmSDMA1_ID 0x0034 +#define mmSDMA1_ID_BASE_IDX 0 +#define mmSDMA1_VERSION 0x0035 +#define mmSDMA1_VERSION_BASE_IDX 0 +#define mmSDMA1_EDC_COUNTER 0x0036 +#define mmSDMA1_EDC_COUNTER_BASE_IDX 0 +#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define mmSDMA1_STATUS2_REG 0x0038 +#define mmSDMA1_STATUS2_REG_BASE_IDX 0 +#define mmSDMA1_ATOMIC_CNTL 0x0039 +#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 +#define mmSDMA1_ATOMIC_PREOP_LO 0x003a +#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 +#define mmSDMA1_ATOMIC_PREOP_HI 0x003b +#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 +#define mmSDMA1_UTCL1_CNTL 0x003c +#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 +#define mmSDMA1_UTCL1_WATERMK 0x003d +#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_STATUS 0x003e +#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_STATUS 0x003f +#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV0 0x0040 +#define mmSDMA1_UTCL1_INV0_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV1 0x0041 +#define mmSDMA1_UTCL1_INV1_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV2 0x0042 +#define mmSDMA1_UTCL1_INV2_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 +#define mmSDMA1_UTCL1_TIMEOUT 0x0047 +#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 +#define mmSDMA1_UTCL1_PAGE 0x0048 +#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 +#define mmSDMA1_POWER_CNTL_IDLE 0x0049 +#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 +#define mmSDMA1_RELAX_ORDERING_LUT 0x004a +#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 +#define mmSDMA1_CHICKEN_BITS_2 0x004b +#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 +#define mmSDMA1_STATUS3_REG 0x004c +#define mmSDMA1_STATUS3_REG_BASE_IDX 0 +#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PHASE2_QUANTUM 0x004f +#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 +#define mmSDMA1_ERROR_LOG 0x0050 +#define mmSDMA1_ERROR_LOG_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG0 0x0051 +#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG1 0x0052 +#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG2 0x0053 +#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG3 0x0054 +#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 +#define mmSDMA1_F32_COUNTER 0x0055 +#define mmSDMA1_F32_COUNTER_BASE_IDX 0 +#define mmSDMA1_UNBREAKABLE 0x0056 +#define mmSDMA1_UNBREAKABLE_BASE_IDX 0 +#define mmSDMA1_PERFMON_CNTL 0x0057 +#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 +#define mmSDMA1_CRD_CNTL 0x005b +#define mmSDMA1_CRD_CNTL_BASE_IDX 0 +#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmSDMA1_ULV_CNTL 0x005e +#define mmSDMA1_ULV_CNTL_BASE_IDX 0 +#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define mmSDMA1_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA1_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 +#define mmSDMA1_GFX_RB_CNTL 0x0080 +#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_RB_BASE 0x0081 +#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 +#define mmSDMA1_GFX_RB_BASE_HI 0x0082 +#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR 0x0083 +#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR 0x0085 +#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_IB_CNTL 0x008a +#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_IB_RPTR 0x008b +#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_GFX_IB_OFFSET 0x008c +#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_GFX_IB_BASE_LO 0x008d +#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_GFX_IB_BASE_HI 0x008e +#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_GFX_IB_SIZE 0x008f +#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_GFX_SKIP_CNTL 0x0090 +#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL 0x0092 +#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 +#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_STATUS 0x00a8 +#define mmSDMA1_GFX_STATUS_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_GFX_WATERMARK 0x00aa +#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_GFX_PREEMPT 0x00b0 +#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 +#define mmSDMA1_GFX_DUMMY_REG 0x00b1 +#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_CNTL 0x00d8 +#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_BASE 0x00d9 +#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_BASE_HI 0x00da +#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR 0x00db +#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR 0x00dd +#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_CNTL 0x00e2 +#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_RPTR 0x00e3 +#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_SIZE 0x00e7 +#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL 0x00ea +#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 +#define mmSDMA1_PAGE_STATUS 0x0100 +#define mmSDMA1_PAGE_STATUS_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_PAGE_WATERMARK 0x0102 +#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_PAGE_PREEMPT 0x0108 +#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 +#define mmSDMA1_PAGE_DUMMY_REG 0x0109 +#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_CNTL 0x0130 +#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_BASE 0x0131 +#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR 0x0133 +#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR 0x0135 +#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_CNTL 0x013a +#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_RPTR 0x013b +#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_OFFSET 0x013c +#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_BASE_LO 0x013d +#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_BASE_HI 0x013e +#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_SIZE 0x013f +#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL 0x0142 +#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC0_STATUS 0x0158 +#define mmSDMA1_RLC0_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC0_WATERMARK 0x015a +#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC0_PREEMPT 0x0160 +#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC0_DUMMY_REG 0x0161 +#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_CNTL 0x0188 +#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_BASE 0x0189 +#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_BASE_HI 0x018a +#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR 0x018b +#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR 0x018d +#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_CNTL 0x0192 +#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_RPTR 0x0193 +#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_OFFSET 0x0194 +#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_SIZE 0x0197 +#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL 0x019a +#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC1_STATUS 0x01b0 +#define mmSDMA1_RLC1_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC1_WATERMARK 0x01b2 +#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC1_PREEMPT 0x01b8 +#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_CNTL 0x01e0 +#define mmSDMA1_RLC2_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_BASE 0x01e1 +#define mmSDMA1_RLC2_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_RPTR 0x01e3 +#define mmSDMA1_RLC2_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_WPTR 0x01e5 +#define mmSDMA1_RLC2_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_CNTL 0x01ea +#define mmSDMA1_RLC2_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_RPTR 0x01eb +#define mmSDMA1_RLC2_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_OFFSET 0x01ec +#define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_SIZE 0x01ef +#define mmSDMA1_RLC2_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC2_DOORBELL 0x01f2 +#define mmSDMA1_RLC2_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC2_STATUS 0x0208 +#define mmSDMA1_RLC2_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC2_WATERMARK 0x020a +#define mmSDMA1_RLC2_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC2_PREEMPT 0x0210 +#define mmSDMA1_RLC2_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC2_DUMMY_REG 0x0211 +#define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_CNTL 0x0238 +#define mmSDMA1_RLC3_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_BASE 0x0239 +#define mmSDMA1_RLC3_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_BASE_HI 0x023a +#define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_RPTR 0x023b +#define mmSDMA1_RLC3_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_WPTR 0x023d +#define mmSDMA1_RLC3_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_CNTL 0x0242 +#define mmSDMA1_RLC3_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_RPTR 0x0243 +#define mmSDMA1_RLC3_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_OFFSET 0x0244 +#define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_SIZE 0x0247 +#define mmSDMA1_RLC3_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC3_DOORBELL 0x024a +#define mmSDMA1_RLC3_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC3_STATUS 0x0260 +#define mmSDMA1_RLC3_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC3_WATERMARK 0x0262 +#define mmSDMA1_RLC3_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC3_PREEMPT 0x0268 +#define mmSDMA1_RLC3_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC3_DUMMY_REG 0x0269 +#define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_CNTL 0x0290 +#define mmSDMA1_RLC4_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_BASE 0x0291 +#define mmSDMA1_RLC4_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_RPTR 0x0293 +#define mmSDMA1_RLC4_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_WPTR 0x0295 +#define mmSDMA1_RLC4_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_CNTL 0x029a +#define mmSDMA1_RLC4_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_RPTR 0x029b +#define mmSDMA1_RLC4_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_OFFSET 0x029c +#define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_BASE_LO 0x029d +#define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_BASE_HI 0x029e +#define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_SIZE 0x029f +#define mmSDMA1_RLC4_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC4_DOORBELL 0x02a2 +#define mmSDMA1_RLC4_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC4_STATUS 0x02b8 +#define mmSDMA1_RLC4_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC4_WATERMARK 0x02ba +#define mmSDMA1_RLC4_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC4_PREEMPT 0x02c0 +#define mmSDMA1_RLC4_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_CNTL 0x02e8 +#define mmSDMA1_RLC5_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_BASE 0x02e9 +#define mmSDMA1_RLC5_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_RPTR 0x02eb +#define mmSDMA1_RLC5_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_WPTR 0x02ed +#define mmSDMA1_RLC5_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_CNTL 0x02f2 +#define mmSDMA1_RLC5_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_RPTR 0x02f3 +#define mmSDMA1_RLC5_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_SIZE 0x02f7 +#define mmSDMA1_RLC5_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC5_DOORBELL 0x02fa +#define mmSDMA1_RLC5_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC5_STATUS 0x0310 +#define mmSDMA1_RLC5_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC5_WATERMARK 0x0312 +#define mmSDMA1_RLC5_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC5_PREEMPT 0x0318 +#define mmSDMA1_RLC5_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC5_DUMMY_REG 0x0319 +#define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_CNTL 0x0340 +#define mmSDMA1_RLC6_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_BASE 0x0341 +#define mmSDMA1_RLC6_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_RPTR 0x0343 +#define mmSDMA1_RLC6_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_WPTR 0x0345 +#define mmSDMA1_RLC6_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_CNTL 0x034a +#define mmSDMA1_RLC6_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_RPTR 0x034b +#define mmSDMA1_RLC6_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_OFFSET 0x034c +#define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_BASE_LO 0x034d +#define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_BASE_HI 0x034e +#define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_SIZE 0x034f +#define mmSDMA1_RLC6_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC6_DOORBELL 0x0352 +#define mmSDMA1_RLC6_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC6_STATUS 0x0368 +#define mmSDMA1_RLC6_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC6_WATERMARK 0x036a +#define mmSDMA1_RLC6_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC6_PREEMPT 0x0370 +#define mmSDMA1_RLC6_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC6_DUMMY_REG 0x0371 +#define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_CNTL 0x0398 +#define mmSDMA1_RLC7_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_BASE 0x0399 +#define mmSDMA1_RLC7_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_BASE_HI 0x039a +#define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_RPTR 0x039b +#define mmSDMA1_RLC7_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_WPTR 0x039d +#define mmSDMA1_RLC7_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_CNTL 0x03a2 +#define mmSDMA1_RLC7_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_RPTR 0x03a3 +#define mmSDMA1_RLC7_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_SIZE 0x03a7 +#define mmSDMA1_RLC7_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC7_DOORBELL 0x03aa +#define mmSDMA1_RLC7_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC7_STATUS 0x03c0 +#define mmSDMA1_RLC7_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC7_WATERMARK 0x03c2 +#define mmSDMA1_RLC7_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC7_PREEMPT 0x03c8 +#define mmSDMA1_RLC7_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h new file mode 100644 index 0000000..ac2468e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma1_4_2_2_SH_MASK_HEADER +#define _sdma1_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma1_sdma1dec +//SDMA1_UCODE_ADDR +#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA1_UCODE_DATA +#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_VM_CNTL +#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA1_VM_CTX_LO +#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_VM_CTX_HI +#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_ACTIVE_FCN_ID +#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA1_VM_CTX_CNTL +#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA1_VIRT_RESET_REQ +#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA1_VF_ENABLE +#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA1_CONTEXT_REG_TYPE0 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA1_CONTEXT_REG_TYPE1 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA1_CONTEXT_REG_TYPE2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA1_CONTEXT_REG_TYPE3 +#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_PUB_REG_TYPE0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE2 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE3 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE3__SDMA1_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE3__SDMA1_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA1_MMHUB_CNTL +#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA1_CONTEXT_GROUP_BOUNDARY +#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_POWER_CNTL +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA1_CLK_CTRL +#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA1_CNTL +#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA1_CHICKEN_BITS +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA1_GB_ADDR_CONFIG +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA1_GB_ADDR_CONFIG_READ +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA1_RB_RPTR_FETCH_HI +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA1_RB_RPTR_FETCH +#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA1_IB_OFFSET_FETCH +#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA1_PROGRAM +#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA1_STATUS_REG +#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA1_STATUS1_REG +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA1_RD_BURST_CNTL +#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA1_HBM_PAGE_CONFIG +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA1_UCODE_CHECKSUM +#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA1_F32_CNTL +#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L +//SDMA1_FREEZE +#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA1_PHASE0_QUANTUM +#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_PHASE1_QUANTUM +#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_EDC_CONFIG +#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA1_BA_THRESHOLD +#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA1_ID +#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA1_VERSION +#define SDMA1_VERSION__MINVER__SHIFT 0x0 +#define SDMA1_VERSION__MAJVER__SHIFT 0x8 +#define SDMA1_VERSION__REV__SHIFT 0x10 +#define SDMA1_VERSION__MINVER_MASK 0x0000007FL +#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA1_VERSION__REV_MASK 0x003F0000L +//SDMA1_EDC_COUNTER +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA1_EDC_COUNTER_CLEAR +#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA1_STATUS2_REG +#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA1_ATOMIC_CNTL +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA1_ATOMIC_PREOP_LO +#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_ATOMIC_PREOP_HI +#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_CNTL +#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA1_UTCL1_WATERMK +#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA1_UTCL1_RD_STATUS +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA1_UTCL1_WR_STATUS +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA1_UTCL1_INV0 +#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA1_UTCL1_INV1 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_INV2 +#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK1 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA1_UTCL1_WR_XNACK0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_WR_XNACK1 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA1_UTCL1_TIMEOUT +#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA1_UTCL1_PAGE +#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA1_POWER_CNTL_IDLE +#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA1_RELAX_ORDERING_LUT +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA1_CHICKEN_BITS_2 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA1_STATUS3_REG +#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA1_PHYSICAL_ADDR_LO +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA1_PHYSICAL_ADDR_HI +#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA1_PHASE2_QUANTUM +#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_ERROR_LOG +#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA1_PUB_DUMMY_REG0 +#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG1 +#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG2 +#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG3 +#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA1_F32_COUNTER +#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA1_UNBREAKABLE +#define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA1_PERFMON_CNTL +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA1_PERFCOUNTER0_RESULT +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER1_RESULT +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA1_CRD_CNTL +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA1_GPU_IOV_VIOLATION_LOG +#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA1_ULV_CNTL +#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA1_EA_DBIT_ADDR_DATA +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_EA_DBIT_ADDR_INDEX +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA1_GPU_IOV_VIOLATION_LOG2 +#define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA1_GFX_RB_CNTL +#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_GFX_RB_BASE +#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_BASE_HI +#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_GFX_RB_RPTR +#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_RPTR_HI +#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR +#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_HI +#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_CNTL +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_GFX_RB_RPTR_ADDR_HI +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_RPTR_ADDR_LO +#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_IB_CNTL +#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_GFX_IB_RPTR +#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_GFX_IB_OFFSET +#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_GFX_IB_BASE_LO +#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_GFX_IB_BASE_HI +#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_IB_SIZE +#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_GFX_SKIP_CNTL +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_GFX_CONTEXT_STATUS +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_GFX_DOORBELL +#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_GFX_CONTEXT_CNTL +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA1_GFX_STATUS +#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_GFX_DOORBELL_LOG +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_GFX_WATERMARK +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_GFX_DOORBELL_OFFSET +#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_GFX_CSA_ADDR_LO +#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_CSA_ADDR_HI +#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_IB_SUB_REMAIN +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_GFX_PREEMPT +#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_GFX_DUMMY_REG +#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_RB_AQL_CNTL +#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_GFX_MINOR_PTR_UPDATE +#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_GFX_MIDCMD_DATA0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA1 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA2 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA3 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA4 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA5 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA6 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA7 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA8 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_CNTL +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_PAGE_RB_CNTL +#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_PAGE_RB_BASE +#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_BASE_HI +#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_PAGE_RB_RPTR +#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_RPTR_HI +#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR +#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_HI +#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_CNTL +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_PAGE_RB_RPTR_ADDR_HI +#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_RPTR_ADDR_LO +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_IB_CNTL +#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_PAGE_IB_RPTR +#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_PAGE_IB_OFFSET +#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_PAGE_IB_BASE_LO +#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_PAGE_IB_BASE_HI +#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_IB_SIZE +#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_PAGE_SKIP_CNTL +#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_PAGE_CONTEXT_STATUS +#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_PAGE_DOORBELL +#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_PAGE_STATUS +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_PAGE_DOORBELL_LOG +#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_PAGE_WATERMARK +#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_PAGE_DOORBELL_OFFSET +#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_PAGE_CSA_ADDR_LO +#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_CSA_ADDR_HI +#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_IB_SUB_REMAIN +#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_PAGE_PREEMPT +#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_PAGE_DUMMY_REG +#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_RB_AQL_CNTL +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_PAGE_MINOR_PTR_UPDATE +#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_PAGE_MIDCMD_DATA0 +#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA1 +#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA2 +#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA3 +#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA4 +#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA5 +#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA6 +#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA7 +#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA8 +#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_CNTL +#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC0_RB_CNTL +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC0_RB_BASE +#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_BASE_HI +#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC0_RB_RPTR +#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_RPTR_HI +#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR +#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_HI +#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_CNTL +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC0_RB_RPTR_ADDR_HI +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_RPTR_ADDR_LO +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_IB_CNTL +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC0_IB_RPTR +#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC0_IB_OFFSET +#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC0_IB_BASE_LO +#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC0_IB_BASE_HI +#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_IB_SIZE +#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC0_SKIP_CNTL +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC0_CONTEXT_STATUS +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC0_DOORBELL +#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC0_STATUS +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC0_DOORBELL_LOG +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC0_WATERMARK +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC0_DOORBELL_OFFSET +#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC0_CSA_ADDR_LO +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_CSA_ADDR_HI +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_IB_SUB_REMAIN +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC0_PREEMPT +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC0_DUMMY_REG +#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_RB_AQL_CNTL +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC0_MINOR_PTR_UPDATE +#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC0_MIDCMD_DATA0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA1 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA2 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA3 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA4 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA5 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA6 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA7 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA8 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_CNTL +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC1_RB_CNTL +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC1_RB_BASE +#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_BASE_HI +#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC1_RB_RPTR +#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_RPTR_HI +#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR +#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_HI +#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_CNTL +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC1_RB_RPTR_ADDR_HI +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_RPTR_ADDR_LO +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_IB_CNTL +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC1_IB_RPTR +#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC1_IB_OFFSET +#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC1_IB_BASE_LO +#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC1_IB_BASE_HI +#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_IB_SIZE +#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC1_SKIP_CNTL +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC1_CONTEXT_STATUS +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC1_DOORBELL +#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC1_STATUS +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC1_DOORBELL_LOG +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC1_WATERMARK +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC1_DOORBELL_OFFSET +#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC1_CSA_ADDR_LO +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_CSA_ADDR_HI +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_IB_SUB_REMAIN +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC1_PREEMPT +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC1_DUMMY_REG +#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_RB_AQL_CNTL +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC1_MINOR_PTR_UPDATE +#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC1_MIDCMD_DATA0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA1 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA2 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA3 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA4 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA5 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA6 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA7 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA8 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_CNTL +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC2_RB_CNTL +#define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC2_RB_BASE +#define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_BASE_HI +#define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC2_RB_RPTR +#define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_RPTR_HI +#define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR +#define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_HI +#define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_POLL_CNTL +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC2_RB_RPTR_ADDR_HI +#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_RPTR_ADDR_LO +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC2_IB_CNTL +#define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC2_IB_RPTR +#define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC2_IB_OFFSET +#define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC2_IB_BASE_LO +#define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC2_IB_BASE_HI +#define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_IB_SIZE +#define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC2_SKIP_CNTL +#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC2_CONTEXT_STATUS +#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC2_DOORBELL +#define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC2_STATUS +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC2_DOORBELL_LOG +#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC2_WATERMARK +#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC2_DOORBELL_OFFSET +#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC2_CSA_ADDR_LO +#define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC2_CSA_ADDR_HI +#define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_IB_SUB_REMAIN +#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC2_PREEMPT +#define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC2_DUMMY_REG +#define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC2_RB_AQL_CNTL +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC2_MINOR_PTR_UPDATE +#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC2_MIDCMD_DATA0 +#define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA1 +#define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA2 +#define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA3 +#define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA4 +#define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA5 +#define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA6 +#define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA7 +#define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA8 +#define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_CNTL +#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC3_RB_CNTL +#define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC3_RB_BASE +#define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_BASE_HI +#define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC3_RB_RPTR +#define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_RPTR_HI +#define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR +#define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_HI +#define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_POLL_CNTL +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC3_RB_RPTR_ADDR_HI +#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_RPTR_ADDR_LO +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC3_IB_CNTL +#define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC3_IB_RPTR +#define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC3_IB_OFFSET +#define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC3_IB_BASE_LO +#define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC3_IB_BASE_HI +#define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_IB_SIZE +#define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC3_SKIP_CNTL +#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC3_CONTEXT_STATUS +#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC3_DOORBELL +#define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC3_STATUS +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC3_DOORBELL_LOG +#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC3_WATERMARK +#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC3_DOORBELL_OFFSET +#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC3_CSA_ADDR_LO +#define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC3_CSA_ADDR_HI +#define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_IB_SUB_REMAIN +#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC3_PREEMPT +#define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC3_DUMMY_REG +#define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC3_RB_AQL_CNTL +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC3_MINOR_PTR_UPDATE +#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC3_MIDCMD_DATA0 +#define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA1 +#define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA2 +#define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA3 +#define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA4 +#define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA5 +#define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA6 +#define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA7 +#define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA8 +#define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_CNTL +#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC4_RB_CNTL +#define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC4_RB_BASE +#define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_BASE_HI +#define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC4_RB_RPTR +#define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_RPTR_HI +#define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR +#define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_HI +#define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_POLL_CNTL +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC4_RB_RPTR_ADDR_HI +#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_RPTR_ADDR_LO +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC4_IB_CNTL +#define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC4_IB_RPTR +#define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC4_IB_OFFSET +#define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC4_IB_BASE_LO +#define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC4_IB_BASE_HI +#define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_IB_SIZE +#define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC4_SKIP_CNTL +#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC4_CONTEXT_STATUS +#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC4_DOORBELL +#define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC4_STATUS +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC4_DOORBELL_LOG +#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC4_WATERMARK +#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC4_DOORBELL_OFFSET +#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC4_CSA_ADDR_LO +#define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC4_CSA_ADDR_HI +#define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_IB_SUB_REMAIN +#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC4_PREEMPT +#define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC4_DUMMY_REG +#define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC4_RB_AQL_CNTL +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC4_MINOR_PTR_UPDATE +#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC4_MIDCMD_DATA0 +#define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA1 +#define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA2 +#define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA3 +#define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA4 +#define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA5 +#define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA6 +#define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA7 +#define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA8 +#define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_CNTL +#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC5_RB_CNTL +#define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC5_RB_BASE +#define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_BASE_HI +#define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC5_RB_RPTR +#define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_RPTR_HI +#define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR +#define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_HI +#define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_POLL_CNTL +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC5_RB_RPTR_ADDR_HI +#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_RPTR_ADDR_LO +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC5_IB_CNTL +#define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC5_IB_RPTR +#define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC5_IB_OFFSET +#define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC5_IB_BASE_LO +#define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC5_IB_BASE_HI +#define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_IB_SIZE +#define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC5_SKIP_CNTL +#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC5_CONTEXT_STATUS +#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC5_DOORBELL +#define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC5_STATUS +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC5_DOORBELL_LOG +#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC5_WATERMARK +#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC5_DOORBELL_OFFSET +#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC5_CSA_ADDR_LO +#define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC5_CSA_ADDR_HI +#define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_IB_SUB_REMAIN +#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC5_PREEMPT +#define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC5_DUMMY_REG +#define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC5_RB_AQL_CNTL +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC5_MINOR_PTR_UPDATE +#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC5_MIDCMD_DATA0 +#define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA1 +#define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA2 +#define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA3 +#define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA4 +#define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA5 +#define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA6 +#define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA7 +#define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA8 +#define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_CNTL +#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC6_RB_CNTL +#define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC6_RB_BASE +#define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_BASE_HI +#define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC6_RB_RPTR +#define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_RPTR_HI +#define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR +#define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_HI +#define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_POLL_CNTL +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC6_RB_RPTR_ADDR_HI +#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_RPTR_ADDR_LO +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC6_IB_CNTL +#define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC6_IB_RPTR +#define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC6_IB_OFFSET +#define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC6_IB_BASE_LO +#define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC6_IB_BASE_HI +#define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_IB_SIZE +#define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC6_SKIP_CNTL +#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC6_CONTEXT_STATUS +#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC6_DOORBELL +#define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC6_STATUS +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC6_DOORBELL_LOG +#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC6_WATERMARK +#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC6_DOORBELL_OFFSET +#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC6_CSA_ADDR_LO +#define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC6_CSA_ADDR_HI +#define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_IB_SUB_REMAIN +#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC6_PREEMPT +#define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC6_DUMMY_REG +#define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC6_RB_AQL_CNTL +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC6_MINOR_PTR_UPDATE +#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC6_MIDCMD_DATA0 +#define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA1 +#define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA2 +#define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA3 +#define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA4 +#define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA5 +#define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA6 +#define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA7 +#define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA8 +#define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_CNTL +#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC7_RB_CNTL +#define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC7_RB_BASE +#define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_BASE_HI +#define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC7_RB_RPTR +#define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_RPTR_HI +#define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR +#define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_HI +#define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_POLL_CNTL +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC7_RB_RPTR_ADDR_HI +#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_RPTR_ADDR_LO +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC7_IB_CNTL +#define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC7_IB_RPTR +#define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC7_IB_OFFSET +#define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC7_IB_BASE_LO +#define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC7_IB_BASE_HI +#define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_IB_SIZE +#define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC7_SKIP_CNTL +#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC7_CONTEXT_STATUS +#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC7_DOORBELL +#define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC7_STATUS +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC7_DOORBELL_LOG +#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC7_WATERMARK +#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC7_DOORBELL_OFFSET +#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC7_CSA_ADDR_LO +#define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC7_CSA_ADDR_HI +#define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_IB_SUB_REMAIN +#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC7_PREEMPT +#define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC7_DUMMY_REG +#define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC7_RB_AQL_CNTL +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC7_MINOR_PTR_UPDATE +#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC7_MIDCMD_DATA0 +#define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA1 +#define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA2 +#define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA3 +#define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA4 +#define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA5 +#define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA6 +#define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA7 +#define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA8 +#define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_CNTL +#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h new file mode 100644 index 0000000..6aa0813 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma2_4_2_2_OFFSET_HEADER +#define _sdma2_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma2_sdma2dec +// base address: 0x78000 +#define mmSDMA2_UCODE_ADDR 0x0000 +#define mmSDMA2_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA2_UCODE_DATA 0x0001 +#define mmSDMA2_UCODE_DATA_BASE_IDX 1 +#define mmSDMA2_VM_CNTL 0x0004 +#define mmSDMA2_VM_CNTL_BASE_IDX 1 +#define mmSDMA2_VM_CTX_LO 0x0005 +#define mmSDMA2_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA2_VM_CTX_HI 0x0006 +#define mmSDMA2_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA2_ACTIVE_FCN_ID 0x0007 +#define mmSDMA2_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA2_VM_CTX_CNTL 0x0008 +#define mmSDMA2_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA2_VIRT_RESET_REQ 0x0009 +#define mmSDMA2_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA2_VF_ENABLE 0x000a +#define mmSDMA2_VF_ENABLE_BASE_IDX 1 +#define mmSDMA2_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA2_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA2_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA2_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA2_PUB_REG_TYPE0 0x000f +#define mmSDMA2_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA2_PUB_REG_TYPE1 0x0010 +#define mmSDMA2_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA2_PUB_REG_TYPE2 0x0011 +#define mmSDMA2_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA2_PUB_REG_TYPE3 0x0012 +#define mmSDMA2_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA2_MMHUB_CNTL 0x0013 +#define mmSDMA2_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA2_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA2_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA2_POWER_CNTL 0x001a +#define mmSDMA2_POWER_CNTL_BASE_IDX 1 +#define mmSDMA2_CLK_CTRL 0x001b +#define mmSDMA2_CLK_CTRL_BASE_IDX 1 +#define mmSDMA2_CNTL 0x001c +#define mmSDMA2_CNTL_BASE_IDX 1 +#define mmSDMA2_CHICKEN_BITS 0x001d +#define mmSDMA2_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA2_GB_ADDR_CONFIG 0x001e +#define mmSDMA2_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA2_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA2_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA2_RB_RPTR_FETCH 0x0022 +#define mmSDMA2_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA2_IB_OFFSET_FETCH 0x0023 +#define mmSDMA2_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA2_PROGRAM 0x0024 +#define mmSDMA2_PROGRAM_BASE_IDX 1 +#define mmSDMA2_STATUS_REG 0x0025 +#define mmSDMA2_STATUS_REG_BASE_IDX 1 +#define mmSDMA2_STATUS1_REG 0x0026 +#define mmSDMA2_STATUS1_REG_BASE_IDX 1 +#define mmSDMA2_RD_BURST_CNTL 0x0027 +#define mmSDMA2_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA2_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA2_UCODE_CHECKSUM 0x0029 +#define mmSDMA2_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA2_F32_CNTL 0x002a +#define mmSDMA2_F32_CNTL_BASE_IDX 1 +#define mmSDMA2_FREEZE 0x002b +#define mmSDMA2_FREEZE_BASE_IDX 1 +#define mmSDMA2_PHASE0_QUANTUM 0x002c +#define mmSDMA2_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA2_PHASE1_QUANTUM 0x002d +#define mmSDMA2_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA2_EDC_CONFIG 0x0032 +#define mmSDMA2_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA2_BA_THRESHOLD 0x0033 +#define mmSDMA2_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA2_ID 0x0034 +#define mmSDMA2_ID_BASE_IDX 1 +#define mmSDMA2_VERSION 0x0035 +#define mmSDMA2_VERSION_BASE_IDX 1 +#define mmSDMA2_EDC_COUNTER 0x0036 +#define mmSDMA2_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA2_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA2_STATUS2_REG 0x0038 +#define mmSDMA2_STATUS2_REG_BASE_IDX 1 +#define mmSDMA2_ATOMIC_CNTL 0x0039 +#define mmSDMA2_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA2_ATOMIC_PREOP_LO 0x003a +#define mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA2_ATOMIC_PREOP_HI 0x003b +#define mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA2_UTCL1_CNTL 0x003c +#define mmSDMA2_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA2_UTCL1_WATERMK 0x003d +#define mmSDMA2_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA2_UTCL1_RD_STATUS 0x003e +#define mmSDMA2_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA2_UTCL1_WR_STATUS 0x003f +#define mmSDMA2_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA2_UTCL1_INV0 0x0040 +#define mmSDMA2_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA2_UTCL1_INV1 0x0041 +#define mmSDMA2_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA2_UTCL1_INV2 0x0042 +#define mmSDMA2_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA2_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA2_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA2_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA2_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA2_UTCL1_TIMEOUT 0x0047 +#define mmSDMA2_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA2_UTCL1_PAGE 0x0048 +#define mmSDMA2_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA2_POWER_CNTL_IDLE 0x0049 +#define mmSDMA2_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA2_RELAX_ORDERING_LUT 0x004a +#define mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA2_CHICKEN_BITS_2 0x004b +#define mmSDMA2_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA2_STATUS3_REG 0x004c +#define mmSDMA2_STATUS3_REG_BASE_IDX 1 +#define mmSDMA2_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_PHASE2_QUANTUM 0x004f +#define mmSDMA2_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA2_ERROR_LOG 0x0050 +#define mmSDMA2_ERROR_LOG_BASE_IDX 1 +#define mmSDMA2_PUB_DUMMY_REG0 0x0051 +#define mmSDMA2_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA2_PUB_DUMMY_REG1 0x0052 +#define mmSDMA2_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA2_PUB_DUMMY_REG2 0x0053 +#define mmSDMA2_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA2_PUB_DUMMY_REG3 0x0054 +#define mmSDMA2_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA2_F32_COUNTER 0x0055 +#define mmSDMA2_F32_COUNTER_BASE_IDX 1 +#define mmSDMA2_UNBREAKABLE 0x0056 +#define mmSDMA2_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA2_PERFMON_CNTL 0x0057 +#define mmSDMA2_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA2_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA2_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA2_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA2_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA2_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA2_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA2_CRD_CNTL 0x005b +#define mmSDMA2_CRD_CNTL_BASE_IDX 1 +#define mmSDMA2_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA2_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA2_ULV_CNTL 0x005e +#define mmSDMA2_ULV_CNTL_BASE_IDX 1 +#define mmSDMA2_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA2_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA2_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA2_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA2_GFX_RB_CNTL 0x0080 +#define mmSDMA2_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_RB_BASE 0x0081 +#define mmSDMA2_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA2_GFX_RB_BASE_HI 0x0082 +#define mmSDMA2_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_GFX_RB_RPTR 0x0083 +#define mmSDMA2_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_GFX_RB_WPTR 0x0085 +#define mmSDMA2_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_GFX_IB_CNTL 0x008a +#define mmSDMA2_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_IB_RPTR 0x008b +#define mmSDMA2_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_GFX_IB_OFFSET 0x008c +#define mmSDMA2_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_GFX_IB_BASE_LO 0x008d +#define mmSDMA2_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_GFX_IB_BASE_HI 0x008e +#define mmSDMA2_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_GFX_IB_SIZE 0x008f +#define mmSDMA2_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_GFX_SKIP_CNTL 0x0090 +#define mmSDMA2_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_GFX_DOORBELL 0x0092 +#define mmSDMA2_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA2_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_STATUS 0x00a8 +#define mmSDMA2_GFX_STATUS_BASE_IDX 1 +#define mmSDMA2_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_GFX_WATERMARK 0x00aa +#define mmSDMA2_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA2_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_GFX_PREEMPT 0x00b0 +#define mmSDMA2_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA2_GFX_DUMMY_REG 0x00b1 +#define mmSDMA2_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_CNTL 0x00d8 +#define mmSDMA2_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_BASE 0x00d9 +#define mmSDMA2_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_BASE_HI 0x00da +#define mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_RPTR 0x00db +#define mmSDMA2_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_WPTR 0x00dd +#define mmSDMA2_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_CNTL 0x00e2 +#define mmSDMA2_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_RPTR 0x00e3 +#define mmSDMA2_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA2_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_SIZE 0x00e7 +#define mmSDMA2_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_PAGE_DOORBELL 0x00ea +#define mmSDMA2_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA2_PAGE_STATUS 0x0100 +#define mmSDMA2_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA2_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_PAGE_WATERMARK 0x0102 +#define mmSDMA2_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA2_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_PAGE_PREEMPT 0x0108 +#define mmSDMA2_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA2_PAGE_DUMMY_REG 0x0109 +#define mmSDMA2_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_CNTL 0x0130 +#define mmSDMA2_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_BASE 0x0131 +#define mmSDMA2_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_RPTR 0x0133 +#define mmSDMA2_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_WPTR 0x0135 +#define mmSDMA2_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_CNTL 0x013a +#define mmSDMA2_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_RPTR 0x013b +#define mmSDMA2_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_OFFSET 0x013c +#define mmSDMA2_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_BASE_LO 0x013d +#define mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_BASE_HI 0x013e +#define mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_SIZE 0x013f +#define mmSDMA2_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC0_DOORBELL 0x0142 +#define mmSDMA2_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC0_STATUS 0x0158 +#define mmSDMA2_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC0_WATERMARK 0x015a +#define mmSDMA2_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC0_PREEMPT 0x0160 +#define mmSDMA2_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC0_DUMMY_REG 0x0161 +#define mmSDMA2_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_CNTL 0x0188 +#define mmSDMA2_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_BASE 0x0189 +#define mmSDMA2_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_BASE_HI 0x018a +#define mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_RPTR 0x018b +#define mmSDMA2_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_WPTR 0x018d +#define mmSDMA2_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_CNTL 0x0192 +#define mmSDMA2_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_RPTR 0x0193 +#define mmSDMA2_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_OFFSET 0x0194 +#define mmSDMA2_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_SIZE 0x0197 +#define mmSDMA2_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC1_DOORBELL 0x019a +#define mmSDMA2_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC1_STATUS 0x01b0 +#define mmSDMA2_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC1_WATERMARK 0x01b2 +#define mmSDMA2_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC1_PREEMPT 0x01b8 +#define mmSDMA2_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA2_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_CNTL 0x01e0 +#define mmSDMA2_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_BASE 0x01e1 +#define mmSDMA2_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_RPTR 0x01e3 +#define mmSDMA2_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_WPTR 0x01e5 +#define mmSDMA2_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_CNTL 0x01ea +#define mmSDMA2_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_RPTR 0x01eb +#define mmSDMA2_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_OFFSET 0x01ec +#define mmSDMA2_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_SIZE 0x01ef +#define mmSDMA2_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC2_DOORBELL 0x01f2 +#define mmSDMA2_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC2_STATUS 0x0208 +#define mmSDMA2_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC2_WATERMARK 0x020a +#define mmSDMA2_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC2_PREEMPT 0x0210 +#define mmSDMA2_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC2_DUMMY_REG 0x0211 +#define mmSDMA2_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_CNTL 0x0238 +#define mmSDMA2_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_BASE 0x0239 +#define mmSDMA2_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_BASE_HI 0x023a +#define mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_RPTR 0x023b +#define mmSDMA2_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_WPTR 0x023d +#define mmSDMA2_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_CNTL 0x0242 +#define mmSDMA2_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_RPTR 0x0243 +#define mmSDMA2_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_OFFSET 0x0244 +#define mmSDMA2_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_SIZE 0x0247 +#define mmSDMA2_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC3_DOORBELL 0x024a +#define mmSDMA2_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC3_STATUS 0x0260 +#define mmSDMA2_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC3_WATERMARK 0x0262 +#define mmSDMA2_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC3_PREEMPT 0x0268 +#define mmSDMA2_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC3_DUMMY_REG 0x0269 +#define mmSDMA2_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_CNTL 0x0290 +#define mmSDMA2_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_BASE 0x0291 +#define mmSDMA2_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_RPTR 0x0293 +#define mmSDMA2_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_WPTR 0x0295 +#define mmSDMA2_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_CNTL 0x029a +#define mmSDMA2_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_RPTR 0x029b +#define mmSDMA2_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_OFFSET 0x029c +#define mmSDMA2_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_BASE_LO 0x029d +#define mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_BASE_HI 0x029e +#define mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_SIZE 0x029f +#define mmSDMA2_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC4_DOORBELL 0x02a2 +#define mmSDMA2_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC4_STATUS 0x02b8 +#define mmSDMA2_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC4_WATERMARK 0x02ba +#define mmSDMA2_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC4_PREEMPT 0x02c0 +#define mmSDMA2_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA2_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_CNTL 0x02e8 +#define mmSDMA2_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_BASE 0x02e9 +#define mmSDMA2_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_RPTR 0x02eb +#define mmSDMA2_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_WPTR 0x02ed +#define mmSDMA2_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_CNTL 0x02f2 +#define mmSDMA2_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_RPTR 0x02f3 +#define mmSDMA2_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA2_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_SIZE 0x02f7 +#define mmSDMA2_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC5_DOORBELL 0x02fa +#define mmSDMA2_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC5_STATUS 0x0310 +#define mmSDMA2_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC5_WATERMARK 0x0312 +#define mmSDMA2_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC5_PREEMPT 0x0318 +#define mmSDMA2_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC5_DUMMY_REG 0x0319 +#define mmSDMA2_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_CNTL 0x0340 +#define mmSDMA2_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_BASE 0x0341 +#define mmSDMA2_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_RPTR 0x0343 +#define mmSDMA2_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_WPTR 0x0345 +#define mmSDMA2_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_CNTL 0x034a +#define mmSDMA2_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_RPTR 0x034b +#define mmSDMA2_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_OFFSET 0x034c +#define mmSDMA2_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_BASE_LO 0x034d +#define mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_BASE_HI 0x034e +#define mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_SIZE 0x034f +#define mmSDMA2_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC6_DOORBELL 0x0352 +#define mmSDMA2_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC6_STATUS 0x0368 +#define mmSDMA2_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC6_WATERMARK 0x036a +#define mmSDMA2_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC6_PREEMPT 0x0370 +#define mmSDMA2_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC6_DUMMY_REG 0x0371 +#define mmSDMA2_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_CNTL 0x0398 +#define mmSDMA2_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_BASE 0x0399 +#define mmSDMA2_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_BASE_HI 0x039a +#define mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_RPTR 0x039b +#define mmSDMA2_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_WPTR 0x039d +#define mmSDMA2_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_CNTL 0x03a2 +#define mmSDMA2_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_RPTR 0x03a3 +#define mmSDMA2_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA2_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_SIZE 0x03a7 +#define mmSDMA2_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC7_DOORBELL 0x03aa +#define mmSDMA2_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC7_STATUS 0x03c0 +#define mmSDMA2_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC7_WATERMARK 0x03c2 +#define mmSDMA2_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC7_PREEMPT 0x03c8 +#define mmSDMA2_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA2_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h new file mode 100644 index 0000000..be10d5d3 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma2_4_2_2_SH_MASK_HEADER +#define _sdma2_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma2_sdma2dec +//SDMA2_UCODE_ADDR +#define SDMA2_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA2_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA2_UCODE_DATA +#define SDMA2_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA2_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA2_VM_CNTL +#define SDMA2_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA2_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA2_VM_CTX_LO +#define SDMA2_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA2_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_VM_CTX_HI +#define SDMA2_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA2_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_ACTIVE_FCN_ID +#define SDMA2_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA2_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA2_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA2_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA2_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA2_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA2_VM_CTX_CNTL +#define SDMA2_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA2_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA2_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA2_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA2_VIRT_RESET_REQ +#define SDMA2_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA2_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA2_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA2_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA2_VF_ENABLE +#define SDMA2_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA2_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA2_CONTEXT_REG_TYPE0 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE__SHIFT 0x1 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL__SHIFT 0xa +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR__SHIFT 0xb +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE__SHIFT 0xf +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL__SHIFT 0x12 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_MASK 0x00000002L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL_MASK 0x00040000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA2_CONTEXT_REG_TYPE1 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS__SHIFT 0x8 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK__SHIFT 0xa +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT__SHIFT 0x10 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA2_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS_MASK 0x00000100L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK_MASK 0x00000400L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT_MASK 0x00010000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA2_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA2_CONTEXT_REG_TYPE2 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA2_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA2_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA2_CONTEXT_REG_TYPE3 +#define SDMA2_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA2_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA2_PUB_REG_TYPE0 +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR__SHIFT 0x0 +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA__SHIFT 0x1 +#define SDMA2_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL__SHIFT 0x4 +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO__SHIFT 0x5 +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI__SHIFT 0x6 +#define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA2_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA2_PUB_REG_TYPE0__SDMA2_MMHUB_CNTL__SHIFT 0x13 +#define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL__SHIFT 0x1a +#define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL__SHIFT 0x1b +#define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL__SHIFT 0x1c +#define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS__SHIFT 0x1d +#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR_MASK 0x00000001L +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA_MASK 0x00000002L +#define SDMA2_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL_MASK 0x00000010L +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO_MASK 0x00000020L +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI_MASK 0x00000040L +#define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA2_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_MMHUB_CNTL_MASK 0x00080000L +#define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL_MASK 0x04000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL_MASK 0x08000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL_MASK 0x10000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS_MASK 0x20000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA2_PUB_REG_TYPE1 +#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM__SHIFT 0x4 +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG__SHIFT 0x5 +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG__SHIFT 0x6 +#define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL__SHIFT 0xa +#define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE__SHIFT 0xb +#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA2_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG__SHIFT 0x12 +#define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD__SHIFT 0x13 +#define SDMA2_PUB_REG_TYPE1__SDMA2_ID__SHIFT 0x14 +#define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION__SHIFT 0x15 +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER__SHIFT 0x16 +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG__SHIFT 0x18 +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL__SHIFT 0x1c +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM_MASK 0x00000010L +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG_MASK 0x00000020L +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG_MASK 0x00000040L +#define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL_MASK 0x00000400L +#define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE_MASK 0x00000800L +#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA2_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG_MASK 0x00040000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD_MASK 0x00080000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_ID_MASK 0x00100000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION_MASK 0x00200000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_MASK 0x00400000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG_MASK 0x01000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL_MASK 0x10000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA2_PUB_REG_TYPE2 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0__SHIFT 0x0 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1__SHIFT 0x1 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2__SHIFT 0x2 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE__SHIFT 0x8 +#define SDMA2_PUB_REG_TYPE2__SDMA2_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG__SHIFT 0xc +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG__SHIFT 0x10 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER__SHIFT 0x15 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UNBREAKABLE__SHIFT 0x16 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFMON_CNTL__SHIFT 0x17 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL__SHIFT 0x1b +#define SDMA2_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA2_PUB_REG_TYPE2__SDMA2_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA2_PUB_REG_TYPE2__SDMA2_ULV_CNTL__SHIFT 0x1e +#define SDMA2_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0_MASK 0x00000001L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1_MASK 0x00000002L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2_MASK 0x00000004L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE_MASK 0x00000100L +#define SDMA2_PUB_REG_TYPE2__SDMA2_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG_MASK 0x00001000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG_MASK 0x00010000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER_MASK 0x00200000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UNBREAKABLE_MASK 0x00400000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFMON_CNTL_MASK 0x00800000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL_MASK 0x08000000L +#define SDMA2_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_ULV_CNTL_MASK 0x40000000L +#define SDMA2_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA2_PUB_REG_TYPE3 +#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA2_PUB_REG_TYPE3__SDMA2_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA2_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA2_PUB_REG_TYPE3__SDMA2_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA2_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA2_MMHUB_CNTL +#define SDMA2_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA2_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA2_CONTEXT_GROUP_BOUNDARY +#define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA2_POWER_CNTL +#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA2_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA2_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA2_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA2_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA2_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA2_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA2_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA2_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA2_CLK_CTRL +#define SDMA2_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA2_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA2_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA2_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA2_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA2_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA2_CNTL +#define SDMA2_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA2_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA2_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA2_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA2_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA2_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA2_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA2_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA2_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA2_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA2_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA2_CHICKEN_BITS +#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA2_GB_ADDR_CONFIG +#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA2_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA2_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA2_GB_ADDR_CONFIG_READ +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA2_RB_RPTR_FETCH_HI +#define SDMA2_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA2_RB_RPTR_FETCH +#define SDMA2_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA2_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA2_IB_OFFSET_FETCH +#define SDMA2_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA2_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA2_PROGRAM +#define SDMA2_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA2_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA2_STATUS_REG +#define SDMA2_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA2_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA2_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA2_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA2_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA2_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA2_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA2_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA2_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA2_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA2_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA2_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA2_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA2_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA2_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA2_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA2_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA2_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA2_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA2_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA2_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA2_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA2_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA2_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA2_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA2_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA2_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA2_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA2_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA2_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA2_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA2_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA2_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA2_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA2_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA2_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA2_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA2_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA2_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA2_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA2_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA2_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA2_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA2_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA2_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA2_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA2_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA2_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA2_STATUS1_REG +#define SDMA2_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA2_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA2_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA2_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA2_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA2_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA2_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA2_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA2_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA2_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA2_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA2_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA2_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA2_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA2_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA2_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA2_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA2_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA2_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA2_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA2_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA2_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA2_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA2_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA2_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA2_RD_BURST_CNTL +#define SDMA2_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA2_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA2_HBM_PAGE_CONFIG +#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA2_UCODE_CHECKSUM +#define SDMA2_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA2_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA2_F32_CNTL +#define SDMA2_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA2_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA2_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA2_F32_CNTL__STEP_MASK 0x00000002L +//SDMA2_FREEZE +#define SDMA2_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA2_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA2_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA2_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA2_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA2_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA2_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA2_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA2_PHASE0_QUANTUM +#define SDMA2_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA2_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA2_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA2_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA2_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA2_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA2_PHASE1_QUANTUM +#define SDMA2_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA2_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA2_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA2_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA2_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA2_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA2_EDC_CONFIG +#define SDMA2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA2_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA2_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA2_BA_THRESHOLD +#define SDMA2_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA2_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA2_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA2_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA2_ID +#define SDMA2_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA2_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA2_VERSION +#define SDMA2_VERSION__MINVER__SHIFT 0x0 +#define SDMA2_VERSION__MAJVER__SHIFT 0x8 +#define SDMA2_VERSION__REV__SHIFT 0x10 +#define SDMA2_VERSION__MINVER_MASK 0x0000007FL +#define SDMA2_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA2_VERSION__REV_MASK 0x003F0000L +//SDMA2_EDC_COUNTER +#define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA2_EDC_COUNTER_CLEAR +#define SDMA2_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA2_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA2_STATUS2_REG +#define SDMA2_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA2_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA2_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA2_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA2_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA2_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA2_ATOMIC_CNTL +#define SDMA2_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA2_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA2_ATOMIC_PREOP_LO +#define SDMA2_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA2_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA2_ATOMIC_PREOP_HI +#define SDMA2_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA2_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_CNTL +#define SDMA2_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA2_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA2_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA2_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA2_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA2_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA2_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA2_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA2_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA2_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA2_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA2_UTCL1_WATERMK +#define SDMA2_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA2_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA2_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA2_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA2_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA2_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA2_UTCL1_RD_STATUS +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA2_UTCL1_WR_STATUS +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA2_UTCL1_INV0 +#define SDMA2_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA2_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA2_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA2_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA2_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA2_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA2_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA2_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA2_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA2_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA2_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA2_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA2_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA2_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA2_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA2_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA2_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA2_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA2_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA2_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA2_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA2_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA2_UTCL1_INV1 +#define SDMA2_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA2_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_INV2 +#define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_RD_XNACK0 +#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_RD_XNACK1 +#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA2_UTCL1_WR_XNACK0 +#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_WR_XNACK1 +#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA2_UTCL1_TIMEOUT +#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA2_UTCL1_PAGE +#define SDMA2_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA2_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA2_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA2_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA2_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA2_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA2_POWER_CNTL_IDLE +#define SDMA2_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA2_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA2_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA2_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA2_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA2_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA2_RELAX_ORDERING_LUT +#define SDMA2_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA2_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA2_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA2_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA2_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA2_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA2_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA2_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA2_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA2_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA2_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA2_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA2_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA2_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA2_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA2_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA2_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA2_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA2_CHICKEN_BITS_2 +#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA2_STATUS3_REG +#define SDMA2_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA2_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA2_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA2_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA2_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA2_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA2_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA2_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA2_PHYSICAL_ADDR_LO +#define SDMA2_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA2_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA2_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA2_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA2_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA2_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA2_PHYSICAL_ADDR_HI +#define SDMA2_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA2_PHASE2_QUANTUM +#define SDMA2_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA2_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA2_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA2_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA2_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA2_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA2_ERROR_LOG +#define SDMA2_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA2_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA2_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA2_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA2_PUB_DUMMY_REG0 +#define SDMA2_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA2_PUB_DUMMY_REG1 +#define SDMA2_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA2_PUB_DUMMY_REG2 +#define SDMA2_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA2_PUB_DUMMY_REG3 +#define SDMA2_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA2_F32_COUNTER +#define SDMA2_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA2_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA2_UNBREAKABLE +#define SDMA2_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA2_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA2_PERFMON_CNTL +#define SDMA2_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA2_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA2_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA2_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA2_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA2_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA2_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA2_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA2_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA2_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA2_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA2_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA2_PERFCOUNTER0_RESULT +#define SDMA2_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA2_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA2_PERFCOUNTER1_RESULT +#define SDMA2_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA2_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA2_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA2_CRD_CNTL +#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA2_GPU_IOV_VIOLATION_LOG +#define SDMA2_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA2_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA2_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA2_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA2_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA2_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA2_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA2_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA2_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA2_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA2_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA2_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA2_ULV_CNTL +#define SDMA2_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA2_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA2_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA2_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA2_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA2_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA2_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA2_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA2_EA_DBIT_ADDR_DATA +#define SDMA2_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA2_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA2_EA_DBIT_ADDR_INDEX +#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA2_GPU_IOV_VIOLATION_LOG2 +#define SDMA2_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA2_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA2_GFX_RB_CNTL +#define SDMA2_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_GFX_RB_BASE +#define SDMA2_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_BASE_HI +#define SDMA2_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_GFX_RB_RPTR +#define SDMA2_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_RPTR_HI +#define SDMA2_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR +#define SDMA2_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_HI +#define SDMA2_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_POLL_CNTL +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_GFX_RB_RPTR_ADDR_HI +#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_RPTR_ADDR_LO +#define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_GFX_IB_CNTL +#define SDMA2_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_GFX_IB_RPTR +#define SDMA2_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_GFX_IB_OFFSET +#define SDMA2_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_GFX_IB_BASE_LO +#define SDMA2_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_GFX_IB_BASE_HI +#define SDMA2_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_IB_SIZE +#define SDMA2_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_GFX_SKIP_CNTL +#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_GFX_CONTEXT_STATUS +#define SDMA2_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_GFX_DOORBELL +#define SDMA2_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_GFX_CONTEXT_CNTL +#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA2_GFX_STATUS +#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_GFX_DOORBELL_LOG +#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_GFX_WATERMARK +#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_GFX_DOORBELL_OFFSET +#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_GFX_CSA_ADDR_LO +#define SDMA2_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_GFX_CSA_ADDR_HI +#define SDMA2_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_IB_SUB_REMAIN +#define SDMA2_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_GFX_PREEMPT +#define SDMA2_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_GFX_DUMMY_REG +#define SDMA2_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_GFX_RB_AQL_CNTL +#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_GFX_MINOR_PTR_UPDATE +#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_GFX_MIDCMD_DATA0 +#define SDMA2_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA1 +#define SDMA2_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA2 +#define SDMA2_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA3 +#define SDMA2_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA4 +#define SDMA2_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA5 +#define SDMA2_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA6 +#define SDMA2_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA7 +#define SDMA2_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA8 +#define SDMA2_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_CNTL +#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_PAGE_RB_CNTL +#define SDMA2_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_PAGE_RB_BASE +#define SDMA2_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_BASE_HI +#define SDMA2_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_PAGE_RB_RPTR +#define SDMA2_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_RPTR_HI +#define SDMA2_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR +#define SDMA2_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_HI +#define SDMA2_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_POLL_CNTL +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_PAGE_RB_RPTR_ADDR_HI +#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_RPTR_ADDR_LO +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_PAGE_IB_CNTL +#define SDMA2_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_PAGE_IB_RPTR +#define SDMA2_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_PAGE_IB_OFFSET +#define SDMA2_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_PAGE_IB_BASE_LO +#define SDMA2_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_PAGE_IB_BASE_HI +#define SDMA2_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_IB_SIZE +#define SDMA2_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_PAGE_SKIP_CNTL +#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_PAGE_CONTEXT_STATUS +#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_PAGE_DOORBELL +#define SDMA2_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_PAGE_STATUS +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_PAGE_DOORBELL_LOG +#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_PAGE_WATERMARK +#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_PAGE_DOORBELL_OFFSET +#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_PAGE_CSA_ADDR_LO +#define SDMA2_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_PAGE_CSA_ADDR_HI +#define SDMA2_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_IB_SUB_REMAIN +#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_PAGE_PREEMPT +#define SDMA2_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_PAGE_DUMMY_REG +#define SDMA2_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_PAGE_RB_AQL_CNTL +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_PAGE_MINOR_PTR_UPDATE +#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_PAGE_MIDCMD_DATA0 +#define SDMA2_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA1 +#define SDMA2_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA2 +#define SDMA2_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA3 +#define SDMA2_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA4 +#define SDMA2_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA5 +#define SDMA2_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA6 +#define SDMA2_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA7 +#define SDMA2_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA8 +#define SDMA2_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_CNTL +#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC0_RB_CNTL +#define SDMA2_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC0_RB_BASE +#define SDMA2_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_BASE_HI +#define SDMA2_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC0_RB_RPTR +#define SDMA2_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_RPTR_HI +#define SDMA2_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR +#define SDMA2_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_HI +#define SDMA2_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_POLL_CNTL +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC0_RB_RPTR_ADDR_HI +#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_RPTR_ADDR_LO +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC0_IB_CNTL +#define SDMA2_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC0_IB_RPTR +#define SDMA2_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC0_IB_OFFSET +#define SDMA2_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC0_IB_BASE_LO +#define SDMA2_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC0_IB_BASE_HI +#define SDMA2_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_IB_SIZE +#define SDMA2_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC0_SKIP_CNTL +#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC0_CONTEXT_STATUS +#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC0_DOORBELL +#define SDMA2_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC0_STATUS +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC0_DOORBELL_LOG +#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC0_WATERMARK +#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC0_DOORBELL_OFFSET +#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC0_CSA_ADDR_LO +#define SDMA2_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC0_CSA_ADDR_HI +#define SDMA2_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_IB_SUB_REMAIN +#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC0_PREEMPT +#define SDMA2_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC0_DUMMY_REG +#define SDMA2_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC0_RB_AQL_CNTL +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC0_MINOR_PTR_UPDATE +#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC0_MIDCMD_DATA0 +#define SDMA2_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA1 +#define SDMA2_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA2 +#define SDMA2_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA3 +#define SDMA2_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA4 +#define SDMA2_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA5 +#define SDMA2_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA6 +#define SDMA2_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA7 +#define SDMA2_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA8 +#define SDMA2_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_CNTL +#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC1_RB_CNTL +#define SDMA2_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC1_RB_BASE +#define SDMA2_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_BASE_HI +#define SDMA2_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC1_RB_RPTR +#define SDMA2_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_RPTR_HI +#define SDMA2_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR +#define SDMA2_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_HI +#define SDMA2_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_POLL_CNTL +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC1_RB_RPTR_ADDR_HI +#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_RPTR_ADDR_LO +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC1_IB_CNTL +#define SDMA2_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC1_IB_RPTR +#define SDMA2_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC1_IB_OFFSET +#define SDMA2_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC1_IB_BASE_LO +#define SDMA2_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC1_IB_BASE_HI +#define SDMA2_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_IB_SIZE +#define SDMA2_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC1_SKIP_CNTL +#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC1_CONTEXT_STATUS +#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC1_DOORBELL +#define SDMA2_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC1_STATUS +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC1_DOORBELL_LOG +#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC1_WATERMARK +#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC1_DOORBELL_OFFSET +#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC1_CSA_ADDR_LO +#define SDMA2_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC1_CSA_ADDR_HI +#define SDMA2_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_IB_SUB_REMAIN +#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC1_PREEMPT +#define SDMA2_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC1_DUMMY_REG +#define SDMA2_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC1_RB_AQL_CNTL +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC1_MINOR_PTR_UPDATE +#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC1_MIDCMD_DATA0 +#define SDMA2_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA1 +#define SDMA2_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA2 +#define SDMA2_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA3 +#define SDMA2_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA4 +#define SDMA2_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA5 +#define SDMA2_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA6 +#define SDMA2_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA7 +#define SDMA2_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA8 +#define SDMA2_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_CNTL +#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC2_RB_CNTL +#define SDMA2_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC2_RB_BASE +#define SDMA2_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_BASE_HI +#define SDMA2_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC2_RB_RPTR +#define SDMA2_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_RPTR_HI +#define SDMA2_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR +#define SDMA2_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_HI +#define SDMA2_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_POLL_CNTL +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC2_RB_RPTR_ADDR_HI +#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_RPTR_ADDR_LO +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC2_IB_CNTL +#define SDMA2_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC2_IB_RPTR +#define SDMA2_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC2_IB_OFFSET +#define SDMA2_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC2_IB_BASE_LO +#define SDMA2_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC2_IB_BASE_HI +#define SDMA2_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_IB_SIZE +#define SDMA2_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC2_SKIP_CNTL +#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC2_CONTEXT_STATUS +#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC2_DOORBELL +#define SDMA2_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC2_STATUS +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC2_DOORBELL_LOG +#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC2_WATERMARK +#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC2_DOORBELL_OFFSET +#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC2_CSA_ADDR_LO +#define SDMA2_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC2_CSA_ADDR_HI +#define SDMA2_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_IB_SUB_REMAIN +#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC2_PREEMPT +#define SDMA2_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC2_DUMMY_REG +#define SDMA2_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC2_RB_AQL_CNTL +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC2_MINOR_PTR_UPDATE +#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC2_MIDCMD_DATA0 +#define SDMA2_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA1 +#define SDMA2_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA2 +#define SDMA2_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA3 +#define SDMA2_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA4 +#define SDMA2_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA5 +#define SDMA2_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA6 +#define SDMA2_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA7 +#define SDMA2_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA8 +#define SDMA2_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_CNTL +#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC3_RB_CNTL +#define SDMA2_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC3_RB_BASE +#define SDMA2_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_BASE_HI +#define SDMA2_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC3_RB_RPTR +#define SDMA2_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_RPTR_HI +#define SDMA2_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR +#define SDMA2_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_HI +#define SDMA2_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_POLL_CNTL +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC3_RB_RPTR_ADDR_HI +#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_RPTR_ADDR_LO +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC3_IB_CNTL +#define SDMA2_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC3_IB_RPTR +#define SDMA2_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC3_IB_OFFSET +#define SDMA2_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC3_IB_BASE_LO +#define SDMA2_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC3_IB_BASE_HI +#define SDMA2_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_IB_SIZE +#define SDMA2_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC3_SKIP_CNTL +#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC3_CONTEXT_STATUS +#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC3_DOORBELL +#define SDMA2_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC3_STATUS +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC3_DOORBELL_LOG +#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC3_WATERMARK +#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC3_DOORBELL_OFFSET +#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC3_CSA_ADDR_LO +#define SDMA2_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC3_CSA_ADDR_HI +#define SDMA2_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_IB_SUB_REMAIN +#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC3_PREEMPT +#define SDMA2_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC3_DUMMY_REG +#define SDMA2_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC3_RB_AQL_CNTL +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC3_MINOR_PTR_UPDATE +#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC3_MIDCMD_DATA0 +#define SDMA2_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA1 +#define SDMA2_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA2 +#define SDMA2_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA3 +#define SDMA2_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA4 +#define SDMA2_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA5 +#define SDMA2_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA6 +#define SDMA2_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA7 +#define SDMA2_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA8 +#define SDMA2_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_CNTL +#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC4_RB_CNTL +#define SDMA2_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC4_RB_BASE +#define SDMA2_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_BASE_HI +#define SDMA2_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC4_RB_RPTR +#define SDMA2_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_RPTR_HI +#define SDMA2_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR +#define SDMA2_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_HI +#define SDMA2_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_POLL_CNTL +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC4_RB_RPTR_ADDR_HI +#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_RPTR_ADDR_LO +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC4_IB_CNTL +#define SDMA2_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC4_IB_RPTR +#define SDMA2_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC4_IB_OFFSET +#define SDMA2_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC4_IB_BASE_LO +#define SDMA2_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC4_IB_BASE_HI +#define SDMA2_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_IB_SIZE +#define SDMA2_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC4_SKIP_CNTL +#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC4_CONTEXT_STATUS +#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC4_DOORBELL +#define SDMA2_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC4_STATUS +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC4_DOORBELL_LOG +#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC4_WATERMARK +#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC4_DOORBELL_OFFSET +#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC4_CSA_ADDR_LO +#define SDMA2_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC4_CSA_ADDR_HI +#define SDMA2_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_IB_SUB_REMAIN +#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC4_PREEMPT +#define SDMA2_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC4_DUMMY_REG +#define SDMA2_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC4_RB_AQL_CNTL +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC4_MINOR_PTR_UPDATE +#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC4_MIDCMD_DATA0 +#define SDMA2_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA1 +#define SDMA2_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA2 +#define SDMA2_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA3 +#define SDMA2_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA4 +#define SDMA2_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA5 +#define SDMA2_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA6 +#define SDMA2_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA7 +#define SDMA2_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA8 +#define SDMA2_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_CNTL +#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC5_RB_CNTL +#define SDMA2_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC5_RB_BASE +#define SDMA2_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_BASE_HI +#define SDMA2_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC5_RB_RPTR +#define SDMA2_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_RPTR_HI +#define SDMA2_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR +#define SDMA2_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_HI +#define SDMA2_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_POLL_CNTL +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC5_RB_RPTR_ADDR_HI +#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_RPTR_ADDR_LO +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC5_IB_CNTL +#define SDMA2_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC5_IB_RPTR +#define SDMA2_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC5_IB_OFFSET +#define SDMA2_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC5_IB_BASE_LO +#define SDMA2_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC5_IB_BASE_HI +#define SDMA2_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_IB_SIZE +#define SDMA2_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC5_SKIP_CNTL +#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC5_CONTEXT_STATUS +#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC5_DOORBELL +#define SDMA2_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC5_STATUS +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC5_DOORBELL_LOG +#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC5_WATERMARK +#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC5_DOORBELL_OFFSET +#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC5_CSA_ADDR_LO +#define SDMA2_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC5_CSA_ADDR_HI +#define SDMA2_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_IB_SUB_REMAIN +#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC5_PREEMPT +#define SDMA2_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC5_DUMMY_REG +#define SDMA2_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC5_RB_AQL_CNTL +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC5_MINOR_PTR_UPDATE +#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC5_MIDCMD_DATA0 +#define SDMA2_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA1 +#define SDMA2_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA2 +#define SDMA2_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA3 +#define SDMA2_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA4 +#define SDMA2_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA5 +#define SDMA2_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA6 +#define SDMA2_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA7 +#define SDMA2_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA8 +#define SDMA2_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_CNTL +#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC6_RB_CNTL +#define SDMA2_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC6_RB_BASE +#define SDMA2_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_BASE_HI +#define SDMA2_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC6_RB_RPTR +#define SDMA2_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_RPTR_HI +#define SDMA2_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR +#define SDMA2_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_HI +#define SDMA2_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_POLL_CNTL +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC6_RB_RPTR_ADDR_HI +#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_RPTR_ADDR_LO +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC6_IB_CNTL +#define SDMA2_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC6_IB_RPTR +#define SDMA2_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC6_IB_OFFSET +#define SDMA2_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC6_IB_BASE_LO +#define SDMA2_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC6_IB_BASE_HI +#define SDMA2_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_IB_SIZE +#define SDMA2_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC6_SKIP_CNTL +#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC6_CONTEXT_STATUS +#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC6_DOORBELL +#define SDMA2_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC6_STATUS +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC6_DOORBELL_LOG +#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC6_WATERMARK +#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC6_DOORBELL_OFFSET +#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC6_CSA_ADDR_LO +#define SDMA2_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC6_CSA_ADDR_HI +#define SDMA2_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_IB_SUB_REMAIN +#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC6_PREEMPT +#define SDMA2_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC6_DUMMY_REG +#define SDMA2_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC6_RB_AQL_CNTL +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC6_MINOR_PTR_UPDATE +#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC6_MIDCMD_DATA0 +#define SDMA2_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA1 +#define SDMA2_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA2 +#define SDMA2_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA3 +#define SDMA2_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA4 +#define SDMA2_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA5 +#define SDMA2_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA6 +#define SDMA2_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA7 +#define SDMA2_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA8 +#define SDMA2_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_CNTL +#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC7_RB_CNTL +#define SDMA2_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC7_RB_BASE +#define SDMA2_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_BASE_HI +#define SDMA2_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC7_RB_RPTR +#define SDMA2_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_RPTR_HI +#define SDMA2_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR +#define SDMA2_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_HI +#define SDMA2_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_POLL_CNTL +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC7_RB_RPTR_ADDR_HI +#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_RPTR_ADDR_LO +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC7_IB_CNTL +#define SDMA2_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC7_IB_RPTR +#define SDMA2_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC7_IB_OFFSET +#define SDMA2_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC7_IB_BASE_LO +#define SDMA2_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC7_IB_BASE_HI +#define SDMA2_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_IB_SIZE +#define SDMA2_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC7_SKIP_CNTL +#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC7_CONTEXT_STATUS +#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC7_DOORBELL +#define SDMA2_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC7_STATUS +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC7_DOORBELL_LOG +#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC7_WATERMARK +#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC7_DOORBELL_OFFSET +#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC7_CSA_ADDR_LO +#define SDMA2_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC7_CSA_ADDR_HI +#define SDMA2_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_IB_SUB_REMAIN +#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC7_PREEMPT +#define SDMA2_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC7_DUMMY_REG +#define SDMA2_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC7_RB_AQL_CNTL +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC7_MINOR_PTR_UPDATE +#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC7_MIDCMD_DATA0 +#define SDMA2_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA1 +#define SDMA2_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA2 +#define SDMA2_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA3 +#define SDMA2_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA4 +#define SDMA2_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA5 +#define SDMA2_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA6 +#define SDMA2_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA7 +#define SDMA2_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA8 +#define SDMA2_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_CNTL +#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h new file mode 100644 index 0000000..09e8302 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma3_4_2_2_OFFSET_HEADER +#define _sdma3_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma3_sdma3dec +// base address: 0x79000 +#define mmSDMA3_UCODE_ADDR 0x0000 +#define mmSDMA3_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA3_UCODE_DATA 0x0001 +#define mmSDMA3_UCODE_DATA_BASE_IDX 1 +#define mmSDMA3_VM_CNTL 0x0004 +#define mmSDMA3_VM_CNTL_BASE_IDX 1 +#define mmSDMA3_VM_CTX_LO 0x0005 +#define mmSDMA3_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA3_VM_CTX_HI 0x0006 +#define mmSDMA3_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA3_ACTIVE_FCN_ID 0x0007 +#define mmSDMA3_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA3_VM_CTX_CNTL 0x0008 +#define mmSDMA3_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA3_VIRT_RESET_REQ 0x0009 +#define mmSDMA3_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA3_VF_ENABLE 0x000a +#define mmSDMA3_VF_ENABLE_BASE_IDX 1 +#define mmSDMA3_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA3_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA3_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA3_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA3_PUB_REG_TYPE0 0x000f +#define mmSDMA3_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA3_PUB_REG_TYPE1 0x0010 +#define mmSDMA3_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA3_PUB_REG_TYPE2 0x0011 +#define mmSDMA3_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA3_PUB_REG_TYPE3 0x0012 +#define mmSDMA3_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA3_MMHUB_CNTL 0x0013 +#define mmSDMA3_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA3_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA3_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA3_POWER_CNTL 0x001a +#define mmSDMA3_POWER_CNTL_BASE_IDX 1 +#define mmSDMA3_CLK_CTRL 0x001b +#define mmSDMA3_CLK_CTRL_BASE_IDX 1 +#define mmSDMA3_CNTL 0x001c +#define mmSDMA3_CNTL_BASE_IDX 1 +#define mmSDMA3_CHICKEN_BITS 0x001d +#define mmSDMA3_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA3_GB_ADDR_CONFIG 0x001e +#define mmSDMA3_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA3_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA3_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA3_RB_RPTR_FETCH 0x0022 +#define mmSDMA3_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA3_IB_OFFSET_FETCH 0x0023 +#define mmSDMA3_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA3_PROGRAM 0x0024 +#define mmSDMA3_PROGRAM_BASE_IDX 1 +#define mmSDMA3_STATUS_REG 0x0025 +#define mmSDMA3_STATUS_REG_BASE_IDX 1 +#define mmSDMA3_STATUS1_REG 0x0026 +#define mmSDMA3_STATUS1_REG_BASE_IDX 1 +#define mmSDMA3_RD_BURST_CNTL 0x0027 +#define mmSDMA3_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA3_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA3_UCODE_CHECKSUM 0x0029 +#define mmSDMA3_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA3_F32_CNTL 0x002a +#define mmSDMA3_F32_CNTL_BASE_IDX 1 +#define mmSDMA3_FREEZE 0x002b +#define mmSDMA3_FREEZE_BASE_IDX 1 +#define mmSDMA3_PHASE0_QUANTUM 0x002c +#define mmSDMA3_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA3_PHASE1_QUANTUM 0x002d +#define mmSDMA3_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA3_EDC_CONFIG 0x0032 +#define mmSDMA3_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA3_BA_THRESHOLD 0x0033 +#define mmSDMA3_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA3_ID 0x0034 +#define mmSDMA3_ID_BASE_IDX 1 +#define mmSDMA3_VERSION 0x0035 +#define mmSDMA3_VERSION_BASE_IDX 1 +#define mmSDMA3_EDC_COUNTER 0x0036 +#define mmSDMA3_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA3_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA3_STATUS2_REG 0x0038 +#define mmSDMA3_STATUS2_REG_BASE_IDX 1 +#define mmSDMA3_ATOMIC_CNTL 0x0039 +#define mmSDMA3_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA3_ATOMIC_PREOP_LO 0x003a +#define mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA3_ATOMIC_PREOP_HI 0x003b +#define mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA3_UTCL1_CNTL 0x003c +#define mmSDMA3_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA3_UTCL1_WATERMK 0x003d +#define mmSDMA3_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA3_UTCL1_RD_STATUS 0x003e +#define mmSDMA3_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA3_UTCL1_WR_STATUS 0x003f +#define mmSDMA3_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA3_UTCL1_INV0 0x0040 +#define mmSDMA3_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA3_UTCL1_INV1 0x0041 +#define mmSDMA3_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA3_UTCL1_INV2 0x0042 +#define mmSDMA3_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA3_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA3_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA3_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA3_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA3_UTCL1_TIMEOUT 0x0047 +#define mmSDMA3_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA3_UTCL1_PAGE 0x0048 +#define mmSDMA3_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA3_POWER_CNTL_IDLE 0x0049 +#define mmSDMA3_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA3_RELAX_ORDERING_LUT 0x004a +#define mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA3_CHICKEN_BITS_2 0x004b +#define mmSDMA3_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA3_STATUS3_REG 0x004c +#define mmSDMA3_STATUS3_REG_BASE_IDX 1 +#define mmSDMA3_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_PHASE2_QUANTUM 0x004f +#define mmSDMA3_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA3_ERROR_LOG 0x0050 +#define mmSDMA3_ERROR_LOG_BASE_IDX 1 +#define mmSDMA3_PUB_DUMMY_REG0 0x0051 +#define mmSDMA3_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA3_PUB_DUMMY_REG1 0x0052 +#define mmSDMA3_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA3_PUB_DUMMY_REG2 0x0053 +#define mmSDMA3_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA3_PUB_DUMMY_REG3 0x0054 +#define mmSDMA3_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA3_F32_COUNTER 0x0055 +#define mmSDMA3_F32_COUNTER_BASE_IDX 1 +#define mmSDMA3_UNBREAKABLE 0x0056 +#define mmSDMA3_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA3_PERFMON_CNTL 0x0057 +#define mmSDMA3_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA3_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA3_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA3_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA3_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA3_CRD_CNTL 0x005b +#define mmSDMA3_CRD_CNTL_BASE_IDX 1 +#define mmSDMA3_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA3_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA3_ULV_CNTL 0x005e +#define mmSDMA3_ULV_CNTL_BASE_IDX 1 +#define mmSDMA3_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA3_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA3_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA3_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA3_GFX_RB_CNTL 0x0080 +#define mmSDMA3_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_RB_BASE 0x0081 +#define mmSDMA3_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA3_GFX_RB_BASE_HI 0x0082 +#define mmSDMA3_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_GFX_RB_RPTR 0x0083 +#define mmSDMA3_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_GFX_RB_WPTR 0x0085 +#define mmSDMA3_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_GFX_IB_CNTL 0x008a +#define mmSDMA3_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_IB_RPTR 0x008b +#define mmSDMA3_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_GFX_IB_OFFSET 0x008c +#define mmSDMA3_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_GFX_IB_BASE_LO 0x008d +#define mmSDMA3_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_GFX_IB_BASE_HI 0x008e +#define mmSDMA3_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_GFX_IB_SIZE 0x008f +#define mmSDMA3_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_GFX_SKIP_CNTL 0x0090 +#define mmSDMA3_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_GFX_DOORBELL 0x0092 +#define mmSDMA3_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA3_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_STATUS 0x00a8 +#define mmSDMA3_GFX_STATUS_BASE_IDX 1 +#define mmSDMA3_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_GFX_WATERMARK 0x00aa +#define mmSDMA3_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA3_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_GFX_PREEMPT 0x00b0 +#define mmSDMA3_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA3_GFX_DUMMY_REG 0x00b1 +#define mmSDMA3_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_CNTL 0x00d8 +#define mmSDMA3_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_BASE 0x00d9 +#define mmSDMA3_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_BASE_HI 0x00da +#define mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_RPTR 0x00db +#define mmSDMA3_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_WPTR 0x00dd +#define mmSDMA3_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_CNTL 0x00e2 +#define mmSDMA3_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_RPTR 0x00e3 +#define mmSDMA3_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA3_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_SIZE 0x00e7 +#define mmSDMA3_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_PAGE_DOORBELL 0x00ea +#define mmSDMA3_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA3_PAGE_STATUS 0x0100 +#define mmSDMA3_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA3_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_PAGE_WATERMARK 0x0102 +#define mmSDMA3_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA3_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_PAGE_PREEMPT 0x0108 +#define mmSDMA3_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA3_PAGE_DUMMY_REG 0x0109 +#define mmSDMA3_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_CNTL 0x0130 +#define mmSDMA3_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_BASE 0x0131 +#define mmSDMA3_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_RPTR 0x0133 +#define mmSDMA3_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_WPTR 0x0135 +#define mmSDMA3_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_CNTL 0x013a +#define mmSDMA3_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_RPTR 0x013b +#define mmSDMA3_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_OFFSET 0x013c +#define mmSDMA3_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_BASE_LO 0x013d +#define mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_BASE_HI 0x013e +#define mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_SIZE 0x013f +#define mmSDMA3_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC0_DOORBELL 0x0142 +#define mmSDMA3_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC0_STATUS 0x0158 +#define mmSDMA3_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC0_WATERMARK 0x015a +#define mmSDMA3_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC0_PREEMPT 0x0160 +#define mmSDMA3_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC0_DUMMY_REG 0x0161 +#define mmSDMA3_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_CNTL 0x0188 +#define mmSDMA3_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_BASE 0x0189 +#define mmSDMA3_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_BASE_HI 0x018a +#define mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_RPTR 0x018b +#define mmSDMA3_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_WPTR 0x018d +#define mmSDMA3_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_CNTL 0x0192 +#define mmSDMA3_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_RPTR 0x0193 +#define mmSDMA3_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_OFFSET 0x0194 +#define mmSDMA3_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_SIZE 0x0197 +#define mmSDMA3_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC1_DOORBELL 0x019a +#define mmSDMA3_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC1_STATUS 0x01b0 +#define mmSDMA3_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC1_WATERMARK 0x01b2 +#define mmSDMA3_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC1_PREEMPT 0x01b8 +#define mmSDMA3_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA3_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_CNTL 0x01e0 +#define mmSDMA3_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_BASE 0x01e1 +#define mmSDMA3_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_RPTR 0x01e3 +#define mmSDMA3_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_WPTR 0x01e5 +#define mmSDMA3_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_CNTL 0x01ea +#define mmSDMA3_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_RPTR 0x01eb +#define mmSDMA3_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_OFFSET 0x01ec +#define mmSDMA3_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_SIZE 0x01ef +#define mmSDMA3_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC2_DOORBELL 0x01f2 +#define mmSDMA3_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC2_STATUS 0x0208 +#define mmSDMA3_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC2_WATERMARK 0x020a +#define mmSDMA3_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC2_PREEMPT 0x0210 +#define mmSDMA3_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC2_DUMMY_REG 0x0211 +#define mmSDMA3_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_CNTL 0x0238 +#define mmSDMA3_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_BASE 0x0239 +#define mmSDMA3_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_BASE_HI 0x023a +#define mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_RPTR 0x023b +#define mmSDMA3_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_WPTR 0x023d +#define mmSDMA3_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_CNTL 0x0242 +#define mmSDMA3_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_RPTR 0x0243 +#define mmSDMA3_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_OFFSET 0x0244 +#define mmSDMA3_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_SIZE 0x0247 +#define mmSDMA3_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC3_DOORBELL 0x024a +#define mmSDMA3_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC3_STATUS 0x0260 +#define mmSDMA3_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC3_WATERMARK 0x0262 +#define mmSDMA3_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC3_PREEMPT 0x0268 +#define mmSDMA3_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC3_DUMMY_REG 0x0269 +#define mmSDMA3_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_CNTL 0x0290 +#define mmSDMA3_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_BASE 0x0291 +#define mmSDMA3_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_RPTR 0x0293 +#define mmSDMA3_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_WPTR 0x0295 +#define mmSDMA3_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_CNTL 0x029a +#define mmSDMA3_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_RPTR 0x029b +#define mmSDMA3_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_OFFSET 0x029c +#define mmSDMA3_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_BASE_LO 0x029d +#define mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_BASE_HI 0x029e +#define mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_SIZE 0x029f +#define mmSDMA3_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC4_DOORBELL 0x02a2 +#define mmSDMA3_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC4_STATUS 0x02b8 +#define mmSDMA3_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC4_WATERMARK 0x02ba +#define mmSDMA3_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC4_PREEMPT 0x02c0 +#define mmSDMA3_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA3_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_CNTL 0x02e8 +#define mmSDMA3_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_BASE 0x02e9 +#define mmSDMA3_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_RPTR 0x02eb +#define mmSDMA3_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_WPTR 0x02ed +#define mmSDMA3_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_CNTL 0x02f2 +#define mmSDMA3_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_RPTR 0x02f3 +#define mmSDMA3_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA3_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_SIZE 0x02f7 +#define mmSDMA3_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC5_DOORBELL 0x02fa +#define mmSDMA3_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC5_STATUS 0x0310 +#define mmSDMA3_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC5_WATERMARK 0x0312 +#define mmSDMA3_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC5_PREEMPT 0x0318 +#define mmSDMA3_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC5_DUMMY_REG 0x0319 +#define mmSDMA3_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_CNTL 0x0340 +#define mmSDMA3_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_BASE 0x0341 +#define mmSDMA3_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_RPTR 0x0343 +#define mmSDMA3_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_WPTR 0x0345 +#define mmSDMA3_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_CNTL 0x034a +#define mmSDMA3_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_RPTR 0x034b +#define mmSDMA3_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_OFFSET 0x034c +#define mmSDMA3_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_BASE_LO 0x034d +#define mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_BASE_HI 0x034e +#define mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_SIZE 0x034f +#define mmSDMA3_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC6_DOORBELL 0x0352 +#define mmSDMA3_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC6_STATUS 0x0368 +#define mmSDMA3_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC6_WATERMARK 0x036a +#define mmSDMA3_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC6_PREEMPT 0x0370 +#define mmSDMA3_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC6_DUMMY_REG 0x0371 +#define mmSDMA3_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_CNTL 0x0398 +#define mmSDMA3_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_BASE 0x0399 +#define mmSDMA3_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_BASE_HI 0x039a +#define mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_RPTR 0x039b +#define mmSDMA3_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_WPTR 0x039d +#define mmSDMA3_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_CNTL 0x03a2 +#define mmSDMA3_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_RPTR 0x03a3 +#define mmSDMA3_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA3_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_SIZE 0x03a7 +#define mmSDMA3_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC7_DOORBELL 0x03aa +#define mmSDMA3_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC7_STATUS 0x03c0 +#define mmSDMA3_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC7_WATERMARK 0x03c2 +#define mmSDMA3_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC7_PREEMPT 0x03c8 +#define mmSDMA3_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA3_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h new file mode 100644 index 0000000..6f2d5ad --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma3_4_2_2_SH_MASK_HEADER +#define _sdma3_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma3_sdma3dec +//SDMA3_UCODE_ADDR +#define SDMA3_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA3_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA3_UCODE_DATA +#define SDMA3_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA3_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA3_VM_CNTL +#define SDMA3_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA3_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA3_VM_CTX_LO +#define SDMA3_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA3_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_VM_CTX_HI +#define SDMA3_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA3_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_ACTIVE_FCN_ID +#define SDMA3_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA3_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA3_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA3_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA3_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA3_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA3_VM_CTX_CNTL +#define SDMA3_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA3_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA3_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA3_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA3_VIRT_RESET_REQ +#define SDMA3_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA3_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA3_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA3_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA3_VF_ENABLE +#define SDMA3_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA3_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA3_CONTEXT_REG_TYPE0 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE__SHIFT 0x1 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL__SHIFT 0xa +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR__SHIFT 0xb +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE__SHIFT 0xf +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL__SHIFT 0x12 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_MASK 0x00000002L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL_MASK 0x00040000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA3_CONTEXT_REG_TYPE1 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS__SHIFT 0x8 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK__SHIFT 0xa +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT__SHIFT 0x10 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA3_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS_MASK 0x00000100L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK_MASK 0x00000400L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT_MASK 0x00010000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA3_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA3_CONTEXT_REG_TYPE2 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA3_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA3_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA3_CONTEXT_REG_TYPE3 +#define SDMA3_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA3_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA3_PUB_REG_TYPE0 +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR__SHIFT 0x0 +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA__SHIFT 0x1 +#define SDMA3_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL__SHIFT 0x4 +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO__SHIFT 0x5 +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI__SHIFT 0x6 +#define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA3_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA3_PUB_REG_TYPE0__SDMA3_MMHUB_CNTL__SHIFT 0x13 +#define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL__SHIFT 0x1a +#define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL__SHIFT 0x1b +#define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL__SHIFT 0x1c +#define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS__SHIFT 0x1d +#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR_MASK 0x00000001L +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA_MASK 0x00000002L +#define SDMA3_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL_MASK 0x00000010L +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO_MASK 0x00000020L +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI_MASK 0x00000040L +#define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA3_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_MMHUB_CNTL_MASK 0x00080000L +#define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL_MASK 0x04000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL_MASK 0x08000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL_MASK 0x10000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS_MASK 0x20000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA3_PUB_REG_TYPE1 +#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM__SHIFT 0x4 +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG__SHIFT 0x5 +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG__SHIFT 0x6 +#define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL__SHIFT 0xa +#define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE__SHIFT 0xb +#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA3_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG__SHIFT 0x12 +#define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD__SHIFT 0x13 +#define SDMA3_PUB_REG_TYPE1__SDMA3_ID__SHIFT 0x14 +#define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION__SHIFT 0x15 +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER__SHIFT 0x16 +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG__SHIFT 0x18 +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL__SHIFT 0x1c +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM_MASK 0x00000010L +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG_MASK 0x00000020L +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG_MASK 0x00000040L +#define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL_MASK 0x00000400L +#define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE_MASK 0x00000800L +#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA3_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG_MASK 0x00040000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD_MASK 0x00080000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_ID_MASK 0x00100000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION_MASK 0x00200000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_MASK 0x00400000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG_MASK 0x01000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL_MASK 0x10000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA3_PUB_REG_TYPE2 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0__SHIFT 0x0 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1__SHIFT 0x1 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2__SHIFT 0x2 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE__SHIFT 0x8 +#define SDMA3_PUB_REG_TYPE2__SDMA3_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG__SHIFT 0xc +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG__SHIFT 0x10 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER__SHIFT 0x15 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UNBREAKABLE__SHIFT 0x16 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFMON_CNTL__SHIFT 0x17 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL__SHIFT 0x1b +#define SDMA3_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA3_PUB_REG_TYPE2__SDMA3_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA3_PUB_REG_TYPE2__SDMA3_ULV_CNTL__SHIFT 0x1e +#define SDMA3_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0_MASK 0x00000001L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1_MASK 0x00000002L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2_MASK 0x00000004L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE_MASK 0x00000100L +#define SDMA3_PUB_REG_TYPE2__SDMA3_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG_MASK 0x00001000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG_MASK 0x00010000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER_MASK 0x00200000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UNBREAKABLE_MASK 0x00400000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFMON_CNTL_MASK 0x00800000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL_MASK 0x08000000L +#define SDMA3_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_ULV_CNTL_MASK 0x40000000L +#define SDMA3_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA3_PUB_REG_TYPE3 +#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA3_PUB_REG_TYPE3__SDMA3_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA3_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA3_PUB_REG_TYPE3__SDMA3_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA3_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA3_MMHUB_CNTL +#define SDMA3_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA3_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA3_CONTEXT_GROUP_BOUNDARY +#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA3_POWER_CNTL +#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA3_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA3_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA3_CLK_CTRL +#define SDMA3_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA3_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA3_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA3_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA3_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA3_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA3_CNTL +#define SDMA3_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA3_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA3_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA3_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA3_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA3_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA3_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA3_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA3_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA3_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA3_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA3_CHICKEN_BITS +#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA3_GB_ADDR_CONFIG +#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA3_GB_ADDR_CONFIG_READ +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA3_RB_RPTR_FETCH_HI +#define SDMA3_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA3_RB_RPTR_FETCH +#define SDMA3_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA3_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA3_IB_OFFSET_FETCH +#define SDMA3_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA3_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA3_PROGRAM +#define SDMA3_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA3_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA3_STATUS_REG +#define SDMA3_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA3_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA3_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA3_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA3_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA3_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA3_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA3_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA3_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA3_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA3_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA3_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA3_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA3_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA3_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA3_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA3_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA3_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA3_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA3_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA3_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA3_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA3_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA3_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA3_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA3_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA3_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA3_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA3_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA3_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA3_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA3_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA3_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA3_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA3_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA3_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA3_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA3_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA3_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA3_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA3_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA3_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA3_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA3_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA3_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA3_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA3_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA3_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA3_STATUS1_REG +#define SDMA3_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA3_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA3_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA3_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA3_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA3_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA3_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA3_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA3_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA3_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA3_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA3_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA3_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA3_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA3_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA3_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA3_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA3_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA3_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA3_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA3_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA3_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA3_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA3_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA3_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA3_RD_BURST_CNTL +#define SDMA3_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA3_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA3_HBM_PAGE_CONFIG +#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA3_UCODE_CHECKSUM +#define SDMA3_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA3_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA3_F32_CNTL +#define SDMA3_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA3_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA3_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA3_F32_CNTL__STEP_MASK 0x00000002L +//SDMA3_FREEZE +#define SDMA3_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA3_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA3_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA3_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA3_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA3_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA3_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA3_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA3_PHASE0_QUANTUM +#define SDMA3_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA3_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA3_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA3_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA3_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA3_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA3_PHASE1_QUANTUM +#define SDMA3_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA3_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA3_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA3_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA3_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA3_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA3_EDC_CONFIG +#define SDMA3_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA3_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA3_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA3_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA3_BA_THRESHOLD +#define SDMA3_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA3_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA3_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA3_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA3_ID +#define SDMA3_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA3_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA3_VERSION +#define SDMA3_VERSION__MINVER__SHIFT 0x0 +#define SDMA3_VERSION__MAJVER__SHIFT 0x8 +#define SDMA3_VERSION__REV__SHIFT 0x10 +#define SDMA3_VERSION__MINVER_MASK 0x0000007FL +#define SDMA3_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA3_VERSION__REV_MASK 0x003F0000L +//SDMA3_EDC_COUNTER +#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA3_EDC_COUNTER_CLEAR +#define SDMA3_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA3_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA3_STATUS2_REG +#define SDMA3_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA3_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA3_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA3_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA3_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA3_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA3_ATOMIC_CNTL +#define SDMA3_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA3_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA3_ATOMIC_PREOP_LO +#define SDMA3_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA3_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA3_ATOMIC_PREOP_HI +#define SDMA3_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA3_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_CNTL +#define SDMA3_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA3_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA3_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA3_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA3_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA3_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA3_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA3_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA3_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA3_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA3_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA3_UTCL1_WATERMK +#define SDMA3_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA3_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA3_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA3_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA3_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA3_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA3_UTCL1_RD_STATUS +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA3_UTCL1_WR_STATUS +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA3_UTCL1_INV0 +#define SDMA3_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA3_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA3_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA3_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA3_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA3_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA3_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA3_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA3_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA3_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA3_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA3_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA3_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA3_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA3_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA3_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA3_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA3_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA3_UTCL1_INV1 +#define SDMA3_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA3_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_INV2 +#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_RD_XNACK0 +#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_RD_XNACK1 +#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA3_UTCL1_WR_XNACK0 +#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_WR_XNACK1 +#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA3_UTCL1_TIMEOUT +#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA3_UTCL1_PAGE +#define SDMA3_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA3_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA3_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA3_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA3_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA3_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA3_POWER_CNTL_IDLE +#define SDMA3_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA3_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA3_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA3_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA3_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA3_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA3_RELAX_ORDERING_LUT +#define SDMA3_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA3_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA3_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA3_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA3_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA3_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA3_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA3_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA3_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA3_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA3_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA3_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA3_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA3_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA3_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA3_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA3_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA3_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA3_CHICKEN_BITS_2 +#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA3_STATUS3_REG +#define SDMA3_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA3_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA3_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA3_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA3_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA3_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA3_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA3_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA3_PHYSICAL_ADDR_LO +#define SDMA3_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA3_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA3_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA3_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA3_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA3_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA3_PHYSICAL_ADDR_HI +#define SDMA3_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA3_PHASE2_QUANTUM +#define SDMA3_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA3_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA3_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA3_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA3_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA3_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA3_ERROR_LOG +#define SDMA3_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA3_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA3_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA3_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA3_PUB_DUMMY_REG0 +#define SDMA3_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA3_PUB_DUMMY_REG1 +#define SDMA3_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA3_PUB_DUMMY_REG2 +#define SDMA3_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA3_PUB_DUMMY_REG3 +#define SDMA3_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA3_F32_COUNTER +#define SDMA3_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA3_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA3_UNBREAKABLE +#define SDMA3_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA3_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA3_PERFMON_CNTL +#define SDMA3_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA3_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA3_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA3_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA3_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA3_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA3_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA3_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA3_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA3_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA3_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA3_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA3_PERFCOUNTER0_RESULT +#define SDMA3_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA3_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA3_PERFCOUNTER1_RESULT +#define SDMA3_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA3_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA3_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA3_CRD_CNTL +#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA3_GPU_IOV_VIOLATION_LOG +#define SDMA3_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA3_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA3_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA3_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA3_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA3_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA3_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA3_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA3_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA3_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA3_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA3_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA3_ULV_CNTL +#define SDMA3_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA3_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA3_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA3_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA3_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA3_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA3_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA3_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA3_EA_DBIT_ADDR_DATA +#define SDMA3_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA3_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA3_EA_DBIT_ADDR_INDEX +#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA3_GPU_IOV_VIOLATION_LOG2 +#define SDMA3_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA3_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA3_GFX_RB_CNTL +#define SDMA3_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_GFX_RB_BASE +#define SDMA3_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_BASE_HI +#define SDMA3_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_GFX_RB_RPTR +#define SDMA3_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_RPTR_HI +#define SDMA3_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR +#define SDMA3_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_HI +#define SDMA3_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_POLL_CNTL +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_GFX_RB_RPTR_ADDR_HI +#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_RPTR_ADDR_LO +#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_GFX_IB_CNTL +#define SDMA3_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_GFX_IB_RPTR +#define SDMA3_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_GFX_IB_OFFSET +#define SDMA3_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_GFX_IB_BASE_LO +#define SDMA3_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_GFX_IB_BASE_HI +#define SDMA3_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_IB_SIZE +#define SDMA3_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_GFX_SKIP_CNTL +#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_GFX_CONTEXT_STATUS +#define SDMA3_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_GFX_DOORBELL +#define SDMA3_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_GFX_CONTEXT_CNTL +#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA3_GFX_STATUS +#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_GFX_DOORBELL_LOG +#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_GFX_WATERMARK +#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_GFX_DOORBELL_OFFSET +#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_GFX_CSA_ADDR_LO +#define SDMA3_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_GFX_CSA_ADDR_HI +#define SDMA3_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_IB_SUB_REMAIN +#define SDMA3_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_GFX_PREEMPT +#define SDMA3_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_GFX_DUMMY_REG +#define SDMA3_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_GFX_RB_AQL_CNTL +#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_GFX_MINOR_PTR_UPDATE +#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_GFX_MIDCMD_DATA0 +#define SDMA3_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA1 +#define SDMA3_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA2 +#define SDMA3_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA3 +#define SDMA3_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA4 +#define SDMA3_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA5 +#define SDMA3_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA6 +#define SDMA3_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA7 +#define SDMA3_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA8 +#define SDMA3_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_CNTL +#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_PAGE_RB_CNTL +#define SDMA3_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_PAGE_RB_BASE +#define SDMA3_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_BASE_HI +#define SDMA3_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_PAGE_RB_RPTR +#define SDMA3_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_RPTR_HI +#define SDMA3_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR +#define SDMA3_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_HI +#define SDMA3_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_POLL_CNTL +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_PAGE_RB_RPTR_ADDR_HI +#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_RPTR_ADDR_LO +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_PAGE_IB_CNTL +#define SDMA3_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_PAGE_IB_RPTR +#define SDMA3_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_PAGE_IB_OFFSET +#define SDMA3_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_PAGE_IB_BASE_LO +#define SDMA3_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_PAGE_IB_BASE_HI +#define SDMA3_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_IB_SIZE +#define SDMA3_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_PAGE_SKIP_CNTL +#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_PAGE_CONTEXT_STATUS +#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_PAGE_DOORBELL +#define SDMA3_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_PAGE_STATUS +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_PAGE_DOORBELL_LOG +#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_PAGE_WATERMARK +#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_PAGE_DOORBELL_OFFSET +#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_PAGE_CSA_ADDR_LO +#define SDMA3_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_PAGE_CSA_ADDR_HI +#define SDMA3_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_IB_SUB_REMAIN +#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_PAGE_PREEMPT +#define SDMA3_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_PAGE_DUMMY_REG +#define SDMA3_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_PAGE_RB_AQL_CNTL +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_PAGE_MINOR_PTR_UPDATE +#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_PAGE_MIDCMD_DATA0 +#define SDMA3_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA1 +#define SDMA3_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA2 +#define SDMA3_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA3 +#define SDMA3_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA4 +#define SDMA3_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA5 +#define SDMA3_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA6 +#define SDMA3_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA7 +#define SDMA3_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA8 +#define SDMA3_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_CNTL +#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC0_RB_CNTL +#define SDMA3_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC0_RB_BASE +#define SDMA3_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_BASE_HI +#define SDMA3_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC0_RB_RPTR +#define SDMA3_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_RPTR_HI +#define SDMA3_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR +#define SDMA3_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_HI +#define SDMA3_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_POLL_CNTL +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC0_RB_RPTR_ADDR_HI +#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_RPTR_ADDR_LO +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC0_IB_CNTL +#define SDMA3_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC0_IB_RPTR +#define SDMA3_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC0_IB_OFFSET +#define SDMA3_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC0_IB_BASE_LO +#define SDMA3_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC0_IB_BASE_HI +#define SDMA3_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_IB_SIZE +#define SDMA3_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC0_SKIP_CNTL +#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC0_CONTEXT_STATUS +#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC0_DOORBELL +#define SDMA3_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC0_STATUS +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC0_DOORBELL_LOG +#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC0_WATERMARK +#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC0_DOORBELL_OFFSET +#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC0_CSA_ADDR_LO +#define SDMA3_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC0_CSA_ADDR_HI +#define SDMA3_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_IB_SUB_REMAIN +#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC0_PREEMPT +#define SDMA3_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC0_DUMMY_REG +#define SDMA3_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC0_RB_AQL_CNTL +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC0_MINOR_PTR_UPDATE +#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC0_MIDCMD_DATA0 +#define SDMA3_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA1 +#define SDMA3_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA2 +#define SDMA3_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA3 +#define SDMA3_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA4 +#define SDMA3_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA5 +#define SDMA3_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA6 +#define SDMA3_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA7 +#define SDMA3_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA8 +#define SDMA3_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_CNTL +#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC1_RB_CNTL +#define SDMA3_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC1_RB_BASE +#define SDMA3_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_BASE_HI +#define SDMA3_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC1_RB_RPTR +#define SDMA3_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_RPTR_HI +#define SDMA3_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR +#define SDMA3_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_HI +#define SDMA3_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_POLL_CNTL +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC1_RB_RPTR_ADDR_HI +#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_RPTR_ADDR_LO +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC1_IB_CNTL +#define SDMA3_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC1_IB_RPTR +#define SDMA3_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC1_IB_OFFSET +#define SDMA3_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC1_IB_BASE_LO +#define SDMA3_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC1_IB_BASE_HI +#define SDMA3_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_IB_SIZE +#define SDMA3_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC1_SKIP_CNTL +#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC1_CONTEXT_STATUS +#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC1_DOORBELL +#define SDMA3_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC1_STATUS +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC1_DOORBELL_LOG +#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC1_WATERMARK +#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC1_DOORBELL_OFFSET +#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC1_CSA_ADDR_LO +#define SDMA3_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC1_CSA_ADDR_HI +#define SDMA3_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_IB_SUB_REMAIN +#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC1_PREEMPT +#define SDMA3_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC1_DUMMY_REG +#define SDMA3_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC1_RB_AQL_CNTL +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC1_MINOR_PTR_UPDATE +#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC1_MIDCMD_DATA0 +#define SDMA3_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA1 +#define SDMA3_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA2 +#define SDMA3_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA3 +#define SDMA3_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA4 +#define SDMA3_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA5 +#define SDMA3_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA6 +#define SDMA3_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA7 +#define SDMA3_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA8 +#define SDMA3_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_CNTL +#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC2_RB_CNTL +#define SDMA3_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC2_RB_BASE +#define SDMA3_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_BASE_HI +#define SDMA3_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC2_RB_RPTR +#define SDMA3_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_RPTR_HI +#define SDMA3_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR +#define SDMA3_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_HI +#define SDMA3_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_POLL_CNTL +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC2_RB_RPTR_ADDR_HI +#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_RPTR_ADDR_LO +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC2_IB_CNTL +#define SDMA3_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC2_IB_RPTR +#define SDMA3_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC2_IB_OFFSET +#define SDMA3_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC2_IB_BASE_LO +#define SDMA3_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC2_IB_BASE_HI +#define SDMA3_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_IB_SIZE +#define SDMA3_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC2_SKIP_CNTL +#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC2_CONTEXT_STATUS +#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC2_DOORBELL +#define SDMA3_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC2_STATUS +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC2_DOORBELL_LOG +#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC2_WATERMARK +#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC2_DOORBELL_OFFSET +#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC2_CSA_ADDR_LO +#define SDMA3_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC2_CSA_ADDR_HI +#define SDMA3_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_IB_SUB_REMAIN +#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC2_PREEMPT +#define SDMA3_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC2_DUMMY_REG +#define SDMA3_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC2_RB_AQL_CNTL +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC2_MINOR_PTR_UPDATE +#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC2_MIDCMD_DATA0 +#define SDMA3_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA1 +#define SDMA3_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA2 +#define SDMA3_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA3 +#define SDMA3_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA4 +#define SDMA3_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA5 +#define SDMA3_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA6 +#define SDMA3_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA7 +#define SDMA3_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA8 +#define SDMA3_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_CNTL +#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC3_RB_CNTL +#define SDMA3_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC3_RB_BASE +#define SDMA3_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_BASE_HI +#define SDMA3_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC3_RB_RPTR +#define SDMA3_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_RPTR_HI +#define SDMA3_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR +#define SDMA3_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_HI +#define SDMA3_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_POLL_CNTL +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC3_RB_RPTR_ADDR_HI +#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_RPTR_ADDR_LO +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC3_IB_CNTL +#define SDMA3_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC3_IB_RPTR +#define SDMA3_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC3_IB_OFFSET +#define SDMA3_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC3_IB_BASE_LO +#define SDMA3_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC3_IB_BASE_HI +#define SDMA3_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_IB_SIZE +#define SDMA3_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC3_SKIP_CNTL +#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC3_CONTEXT_STATUS +#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC3_DOORBELL +#define SDMA3_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC3_STATUS +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC3_DOORBELL_LOG +#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC3_WATERMARK +#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC3_DOORBELL_OFFSET +#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC3_CSA_ADDR_LO +#define SDMA3_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC3_CSA_ADDR_HI +#define SDMA3_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_IB_SUB_REMAIN +#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC3_PREEMPT +#define SDMA3_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC3_DUMMY_REG +#define SDMA3_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC3_RB_AQL_CNTL +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC3_MINOR_PTR_UPDATE +#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC3_MIDCMD_DATA0 +#define SDMA3_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA1 +#define SDMA3_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA2 +#define SDMA3_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA3 +#define SDMA3_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA4 +#define SDMA3_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA5 +#define SDMA3_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA6 +#define SDMA3_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA7 +#define SDMA3_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA8 +#define SDMA3_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_CNTL +#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC4_RB_CNTL +#define SDMA3_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC4_RB_BASE +#define SDMA3_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_BASE_HI +#define SDMA3_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC4_RB_RPTR +#define SDMA3_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_RPTR_HI +#define SDMA3_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR +#define SDMA3_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_HI +#define SDMA3_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_POLL_CNTL +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC4_RB_RPTR_ADDR_HI +#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_RPTR_ADDR_LO +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC4_IB_CNTL +#define SDMA3_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC4_IB_RPTR +#define SDMA3_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC4_IB_OFFSET +#define SDMA3_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC4_IB_BASE_LO +#define SDMA3_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC4_IB_BASE_HI +#define SDMA3_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_IB_SIZE +#define SDMA3_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC4_SKIP_CNTL +#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC4_CONTEXT_STATUS +#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC4_DOORBELL +#define SDMA3_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC4_STATUS +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC4_DOORBELL_LOG +#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC4_WATERMARK +#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC4_DOORBELL_OFFSET +#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC4_CSA_ADDR_LO +#define SDMA3_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC4_CSA_ADDR_HI +#define SDMA3_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_IB_SUB_REMAIN +#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC4_PREEMPT +#define SDMA3_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC4_DUMMY_REG +#define SDMA3_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC4_RB_AQL_CNTL +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC4_MINOR_PTR_UPDATE +#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC4_MIDCMD_DATA0 +#define SDMA3_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA1 +#define SDMA3_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA2 +#define SDMA3_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA3 +#define SDMA3_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA4 +#define SDMA3_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA5 +#define SDMA3_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA6 +#define SDMA3_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA7 +#define SDMA3_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA8 +#define SDMA3_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_CNTL +#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC5_RB_CNTL +#define SDMA3_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC5_RB_BASE +#define SDMA3_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_BASE_HI +#define SDMA3_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC5_RB_RPTR +#define SDMA3_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_RPTR_HI +#define SDMA3_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR +#define SDMA3_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_HI +#define SDMA3_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_POLL_CNTL +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC5_RB_RPTR_ADDR_HI +#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_RPTR_ADDR_LO +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC5_IB_CNTL +#define SDMA3_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC5_IB_RPTR +#define SDMA3_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC5_IB_OFFSET +#define SDMA3_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC5_IB_BASE_LO +#define SDMA3_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC5_IB_BASE_HI +#define SDMA3_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_IB_SIZE +#define SDMA3_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC5_SKIP_CNTL +#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC5_CONTEXT_STATUS +#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC5_DOORBELL +#define SDMA3_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC5_STATUS +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC5_DOORBELL_LOG +#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC5_WATERMARK +#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC5_DOORBELL_OFFSET +#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC5_CSA_ADDR_LO +#define SDMA3_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC5_CSA_ADDR_HI +#define SDMA3_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_IB_SUB_REMAIN +#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC5_PREEMPT +#define SDMA3_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC5_DUMMY_REG +#define SDMA3_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC5_RB_AQL_CNTL +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC5_MINOR_PTR_UPDATE +#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC5_MIDCMD_DATA0 +#define SDMA3_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA1 +#define SDMA3_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA2 +#define SDMA3_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA3 +#define SDMA3_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA4 +#define SDMA3_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA5 +#define SDMA3_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA6 +#define SDMA3_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA7 +#define SDMA3_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA8 +#define SDMA3_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_CNTL +#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC6_RB_CNTL +#define SDMA3_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC6_RB_BASE +#define SDMA3_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_BASE_HI +#define SDMA3_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC6_RB_RPTR +#define SDMA3_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_RPTR_HI +#define SDMA3_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR +#define SDMA3_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_HI +#define SDMA3_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_POLL_CNTL +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC6_RB_RPTR_ADDR_HI +#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_RPTR_ADDR_LO +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC6_IB_CNTL +#define SDMA3_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC6_IB_RPTR +#define SDMA3_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC6_IB_OFFSET +#define SDMA3_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC6_IB_BASE_LO +#define SDMA3_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC6_IB_BASE_HI +#define SDMA3_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_IB_SIZE +#define SDMA3_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC6_SKIP_CNTL +#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC6_CONTEXT_STATUS +#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC6_DOORBELL +#define SDMA3_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC6_STATUS +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC6_DOORBELL_LOG +#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC6_WATERMARK +#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC6_DOORBELL_OFFSET +#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC6_CSA_ADDR_LO +#define SDMA3_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC6_CSA_ADDR_HI +#define SDMA3_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_IB_SUB_REMAIN +#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC6_PREEMPT +#define SDMA3_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC6_DUMMY_REG +#define SDMA3_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC6_RB_AQL_CNTL +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC6_MINOR_PTR_UPDATE +#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC6_MIDCMD_DATA0 +#define SDMA3_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA1 +#define SDMA3_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA2 +#define SDMA3_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA3 +#define SDMA3_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA4 +#define SDMA3_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA5 +#define SDMA3_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA6 +#define SDMA3_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA7 +#define SDMA3_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA8 +#define SDMA3_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_CNTL +#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC7_RB_CNTL +#define SDMA3_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC7_RB_BASE +#define SDMA3_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_BASE_HI +#define SDMA3_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC7_RB_RPTR +#define SDMA3_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_RPTR_HI +#define SDMA3_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR +#define SDMA3_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_HI +#define SDMA3_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_POLL_CNTL +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC7_RB_RPTR_ADDR_HI +#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_RPTR_ADDR_LO +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC7_IB_CNTL +#define SDMA3_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC7_IB_RPTR +#define SDMA3_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC7_IB_OFFSET +#define SDMA3_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC7_IB_BASE_LO +#define SDMA3_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC7_IB_BASE_HI +#define SDMA3_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_IB_SIZE +#define SDMA3_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC7_SKIP_CNTL +#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC7_CONTEXT_STATUS +#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC7_DOORBELL +#define SDMA3_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC7_STATUS +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC7_DOORBELL_LOG +#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC7_WATERMARK +#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC7_DOORBELL_OFFSET +#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC7_CSA_ADDR_LO +#define SDMA3_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC7_CSA_ADDR_HI +#define SDMA3_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_IB_SUB_REMAIN +#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC7_PREEMPT +#define SDMA3_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC7_DUMMY_REG +#define SDMA3_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC7_RB_AQL_CNTL +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC7_MINOR_PTR_UPDATE +#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC7_MIDCMD_DATA0 +#define SDMA3_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA1 +#define SDMA3_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA2 +#define SDMA3_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA3 +#define SDMA3_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA4 +#define SDMA3_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA5 +#define SDMA3_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA6 +#define SDMA3_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA7 +#define SDMA3_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA8 +#define SDMA3_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_CNTL +#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h new file mode 100644 index 0000000..755ffa5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma4_4_2_2_OFFSET_HEADER +#define _sdma4_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma4_sdma4dec +// base address: 0x7a000 +#define mmSDMA4_UCODE_ADDR 0x0000 +#define mmSDMA4_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA4_UCODE_DATA 0x0001 +#define mmSDMA4_UCODE_DATA_BASE_IDX 1 +#define mmSDMA4_VM_CNTL 0x0004 +#define mmSDMA4_VM_CNTL_BASE_IDX 1 +#define mmSDMA4_VM_CTX_LO 0x0005 +#define mmSDMA4_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA4_VM_CTX_HI 0x0006 +#define mmSDMA4_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA4_ACTIVE_FCN_ID 0x0007 +#define mmSDMA4_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA4_VM_CTX_CNTL 0x0008 +#define mmSDMA4_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA4_VIRT_RESET_REQ 0x0009 +#define mmSDMA4_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA4_VF_ENABLE 0x000a +#define mmSDMA4_VF_ENABLE_BASE_IDX 1 +#define mmSDMA4_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA4_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA4_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA4_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA4_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA4_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA4_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA4_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA4_PUB_REG_TYPE0 0x000f +#define mmSDMA4_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA4_PUB_REG_TYPE1 0x0010 +#define mmSDMA4_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA4_PUB_REG_TYPE2 0x0011 +#define mmSDMA4_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA4_PUB_REG_TYPE3 0x0012 +#define mmSDMA4_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA4_MMHUB_CNTL 0x0013 +#define mmSDMA4_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA4_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA4_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA4_POWER_CNTL 0x001a +#define mmSDMA4_POWER_CNTL_BASE_IDX 1 +#define mmSDMA4_CLK_CTRL 0x001b +#define mmSDMA4_CLK_CTRL_BASE_IDX 1 +#define mmSDMA4_CNTL 0x001c +#define mmSDMA4_CNTL_BASE_IDX 1 +#define mmSDMA4_CHICKEN_BITS 0x001d +#define mmSDMA4_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA4_GB_ADDR_CONFIG 0x001e +#define mmSDMA4_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA4_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA4_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA4_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA4_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA4_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA4_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA4_RB_RPTR_FETCH 0x0022 +#define mmSDMA4_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA4_IB_OFFSET_FETCH 0x0023 +#define mmSDMA4_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA4_PROGRAM 0x0024 +#define mmSDMA4_PROGRAM_BASE_IDX 1 +#define mmSDMA4_STATUS_REG 0x0025 +#define mmSDMA4_STATUS_REG_BASE_IDX 1 +#define mmSDMA4_STATUS1_REG 0x0026 +#define mmSDMA4_STATUS1_REG_BASE_IDX 1 +#define mmSDMA4_RD_BURST_CNTL 0x0027 +#define mmSDMA4_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA4_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA4_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA4_UCODE_CHECKSUM 0x0029 +#define mmSDMA4_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA4_F32_CNTL 0x002a +#define mmSDMA4_F32_CNTL_BASE_IDX 1 +#define mmSDMA4_FREEZE 0x002b +#define mmSDMA4_FREEZE_BASE_IDX 1 +#define mmSDMA4_PHASE0_QUANTUM 0x002c +#define mmSDMA4_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA4_PHASE1_QUANTUM 0x002d +#define mmSDMA4_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA4_EDC_CONFIG 0x0032 +#define mmSDMA4_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA4_BA_THRESHOLD 0x0033 +#define mmSDMA4_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA4_ID 0x0034 +#define mmSDMA4_ID_BASE_IDX 1 +#define mmSDMA4_VERSION 0x0035 +#define mmSDMA4_VERSION_BASE_IDX 1 +#define mmSDMA4_EDC_COUNTER 0x0036 +#define mmSDMA4_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA4_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA4_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA4_STATUS2_REG 0x0038 +#define mmSDMA4_STATUS2_REG_BASE_IDX 1 +#define mmSDMA4_ATOMIC_CNTL 0x0039 +#define mmSDMA4_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA4_ATOMIC_PREOP_LO 0x003a +#define mmSDMA4_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA4_ATOMIC_PREOP_HI 0x003b +#define mmSDMA4_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA4_UTCL1_CNTL 0x003c +#define mmSDMA4_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA4_UTCL1_WATERMK 0x003d +#define mmSDMA4_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA4_UTCL1_RD_STATUS 0x003e +#define mmSDMA4_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA4_UTCL1_WR_STATUS 0x003f +#define mmSDMA4_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA4_UTCL1_INV0 0x0040 +#define mmSDMA4_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA4_UTCL1_INV1 0x0041 +#define mmSDMA4_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA4_UTCL1_INV2 0x0042 +#define mmSDMA4_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA4_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA4_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA4_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA4_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA4_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA4_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA4_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA4_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA4_UTCL1_TIMEOUT 0x0047 +#define mmSDMA4_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA4_UTCL1_PAGE 0x0048 +#define mmSDMA4_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA4_POWER_CNTL_IDLE 0x0049 +#define mmSDMA4_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA4_RELAX_ORDERING_LUT 0x004a +#define mmSDMA4_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA4_CHICKEN_BITS_2 0x004b +#define mmSDMA4_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA4_STATUS3_REG 0x004c +#define mmSDMA4_STATUS3_REG_BASE_IDX 1 +#define mmSDMA4_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA4_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA4_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_PHASE2_QUANTUM 0x004f +#define mmSDMA4_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA4_ERROR_LOG 0x0050 +#define mmSDMA4_ERROR_LOG_BASE_IDX 1 +#define mmSDMA4_PUB_DUMMY_REG0 0x0051 +#define mmSDMA4_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA4_PUB_DUMMY_REG1 0x0052 +#define mmSDMA4_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA4_PUB_DUMMY_REG2 0x0053 +#define mmSDMA4_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA4_PUB_DUMMY_REG3 0x0054 +#define mmSDMA4_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA4_F32_COUNTER 0x0055 +#define mmSDMA4_F32_COUNTER_BASE_IDX 1 +#define mmSDMA4_UNBREAKABLE 0x0056 +#define mmSDMA4_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA4_PERFMON_CNTL 0x0057 +#define mmSDMA4_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA4_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA4_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA4_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA4_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA4_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA4_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA4_CRD_CNTL 0x005b +#define mmSDMA4_CRD_CNTL_BASE_IDX 1 +#define mmSDMA4_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA4_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA4_ULV_CNTL 0x005e +#define mmSDMA4_ULV_CNTL_BASE_IDX 1 +#define mmSDMA4_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA4_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA4_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA4_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA4_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA4_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA4_GFX_RB_CNTL 0x0080 +#define mmSDMA4_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_RB_BASE 0x0081 +#define mmSDMA4_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA4_GFX_RB_BASE_HI 0x0082 +#define mmSDMA4_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_GFX_RB_RPTR 0x0083 +#define mmSDMA4_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA4_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_GFX_RB_WPTR 0x0085 +#define mmSDMA4_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA4_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA4_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA4_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA4_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_GFX_IB_CNTL 0x008a +#define mmSDMA4_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_IB_RPTR 0x008b +#define mmSDMA4_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_GFX_IB_OFFSET 0x008c +#define mmSDMA4_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_GFX_IB_BASE_LO 0x008d +#define mmSDMA4_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_GFX_IB_BASE_HI 0x008e +#define mmSDMA4_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_GFX_IB_SIZE 0x008f +#define mmSDMA4_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_GFX_SKIP_CNTL 0x0090 +#define mmSDMA4_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA4_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_GFX_DOORBELL 0x0092 +#define mmSDMA4_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA4_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA4_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_STATUS 0x00a8 +#define mmSDMA4_GFX_STATUS_BASE_IDX 1 +#define mmSDMA4_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA4_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_GFX_WATERMARK 0x00aa +#define mmSDMA4_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA4_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA4_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA4_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA4_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA4_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_GFX_PREEMPT 0x00b0 +#define mmSDMA4_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA4_GFX_DUMMY_REG 0x00b1 +#define mmSDMA4_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA4_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA4_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA4_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA4_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA4_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA4_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA4_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA4_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA4_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA4_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA4_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA4_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_CNTL 0x00d8 +#define mmSDMA4_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_BASE 0x00d9 +#define mmSDMA4_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_BASE_HI 0x00da +#define mmSDMA4_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_RPTR 0x00db +#define mmSDMA4_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA4_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_WPTR 0x00dd +#define mmSDMA4_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA4_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA4_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA4_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA4_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_CNTL 0x00e2 +#define mmSDMA4_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_RPTR 0x00e3 +#define mmSDMA4_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA4_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA4_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA4_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_SIZE 0x00e7 +#define mmSDMA4_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA4_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA4_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_PAGE_DOORBELL 0x00ea +#define mmSDMA4_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA4_PAGE_STATUS 0x0100 +#define mmSDMA4_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA4_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA4_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_PAGE_WATERMARK 0x0102 +#define mmSDMA4_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA4_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA4_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA4_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA4_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA4_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_PAGE_PREEMPT 0x0108 +#define mmSDMA4_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA4_PAGE_DUMMY_REG 0x0109 +#define mmSDMA4_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA4_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA4_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA4_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA4_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA4_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA4_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA4_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA4_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA4_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA4_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA4_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA4_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_CNTL 0x0130 +#define mmSDMA4_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_BASE 0x0131 +#define mmSDMA4_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA4_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_RPTR 0x0133 +#define mmSDMA4_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA4_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_WPTR 0x0135 +#define mmSDMA4_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA4_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA4_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA4_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA4_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_CNTL 0x013a +#define mmSDMA4_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_RPTR 0x013b +#define mmSDMA4_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_OFFSET 0x013c +#define mmSDMA4_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_BASE_LO 0x013d +#define mmSDMA4_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_BASE_HI 0x013e +#define mmSDMA4_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_SIZE 0x013f +#define mmSDMA4_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA4_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA4_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC0_DOORBELL 0x0142 +#define mmSDMA4_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC0_STATUS 0x0158 +#define mmSDMA4_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA4_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC0_WATERMARK 0x015a +#define mmSDMA4_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA4_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA4_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA4_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA4_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC0_PREEMPT 0x0160 +#define mmSDMA4_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC0_DUMMY_REG 0x0161 +#define mmSDMA4_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA4_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA4_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA4_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA4_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA4_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA4_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA4_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA4_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA4_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA4_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA4_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA4_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_CNTL 0x0188 +#define mmSDMA4_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_BASE 0x0189 +#define mmSDMA4_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_BASE_HI 0x018a +#define mmSDMA4_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_RPTR 0x018b +#define mmSDMA4_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA4_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_WPTR 0x018d +#define mmSDMA4_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA4_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA4_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA4_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA4_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_CNTL 0x0192 +#define mmSDMA4_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_RPTR 0x0193 +#define mmSDMA4_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_OFFSET 0x0194 +#define mmSDMA4_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA4_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA4_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_SIZE 0x0197 +#define mmSDMA4_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA4_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA4_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC1_DOORBELL 0x019a +#define mmSDMA4_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC1_STATUS 0x01b0 +#define mmSDMA4_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA4_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC1_WATERMARK 0x01b2 +#define mmSDMA4_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA4_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA4_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA4_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA4_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC1_PREEMPT 0x01b8 +#define mmSDMA4_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA4_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA4_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA4_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA4_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA4_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA4_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA4_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA4_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA4_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA4_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA4_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA4_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA4_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_CNTL 0x01e0 +#define mmSDMA4_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_BASE 0x01e1 +#define mmSDMA4_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA4_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_RPTR 0x01e3 +#define mmSDMA4_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA4_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_WPTR 0x01e5 +#define mmSDMA4_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA4_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA4_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA4_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA4_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_CNTL 0x01ea +#define mmSDMA4_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_RPTR 0x01eb +#define mmSDMA4_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_OFFSET 0x01ec +#define mmSDMA4_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA4_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA4_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_SIZE 0x01ef +#define mmSDMA4_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA4_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA4_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC2_DOORBELL 0x01f2 +#define mmSDMA4_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC2_STATUS 0x0208 +#define mmSDMA4_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA4_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC2_WATERMARK 0x020a +#define mmSDMA4_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA4_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA4_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA4_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA4_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC2_PREEMPT 0x0210 +#define mmSDMA4_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC2_DUMMY_REG 0x0211 +#define mmSDMA4_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA4_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA4_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA4_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA4_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA4_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA4_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA4_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA4_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA4_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA4_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA4_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA4_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_CNTL 0x0238 +#define mmSDMA4_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_BASE 0x0239 +#define mmSDMA4_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_BASE_HI 0x023a +#define mmSDMA4_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_RPTR 0x023b +#define mmSDMA4_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA4_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_WPTR 0x023d +#define mmSDMA4_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA4_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA4_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA4_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA4_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_CNTL 0x0242 +#define mmSDMA4_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_RPTR 0x0243 +#define mmSDMA4_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_OFFSET 0x0244 +#define mmSDMA4_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA4_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA4_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_SIZE 0x0247 +#define mmSDMA4_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA4_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA4_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC3_DOORBELL 0x024a +#define mmSDMA4_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC3_STATUS 0x0260 +#define mmSDMA4_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA4_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC3_WATERMARK 0x0262 +#define mmSDMA4_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA4_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA4_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA4_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA4_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC3_PREEMPT 0x0268 +#define mmSDMA4_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC3_DUMMY_REG 0x0269 +#define mmSDMA4_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA4_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA4_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA4_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA4_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA4_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA4_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA4_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA4_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA4_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA4_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA4_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA4_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_CNTL 0x0290 +#define mmSDMA4_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_BASE 0x0291 +#define mmSDMA4_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA4_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_RPTR 0x0293 +#define mmSDMA4_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA4_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_WPTR 0x0295 +#define mmSDMA4_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA4_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA4_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA4_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA4_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_CNTL 0x029a +#define mmSDMA4_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_RPTR 0x029b +#define mmSDMA4_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_OFFSET 0x029c +#define mmSDMA4_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_BASE_LO 0x029d +#define mmSDMA4_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_BASE_HI 0x029e +#define mmSDMA4_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_SIZE 0x029f +#define mmSDMA4_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA4_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA4_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC4_DOORBELL 0x02a2 +#define mmSDMA4_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC4_STATUS 0x02b8 +#define mmSDMA4_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA4_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC4_WATERMARK 0x02ba +#define mmSDMA4_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA4_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA4_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA4_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA4_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC4_PREEMPT 0x02c0 +#define mmSDMA4_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA4_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA4_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA4_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA4_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA4_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA4_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA4_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA4_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA4_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA4_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA4_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA4_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA4_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_CNTL 0x02e8 +#define mmSDMA4_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_BASE 0x02e9 +#define mmSDMA4_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA4_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_RPTR 0x02eb +#define mmSDMA4_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA4_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_WPTR 0x02ed +#define mmSDMA4_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA4_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA4_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA4_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA4_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_CNTL 0x02f2 +#define mmSDMA4_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_RPTR 0x02f3 +#define mmSDMA4_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA4_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA4_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA4_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_SIZE 0x02f7 +#define mmSDMA4_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA4_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA4_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC5_DOORBELL 0x02fa +#define mmSDMA4_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC5_STATUS 0x0310 +#define mmSDMA4_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA4_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC5_WATERMARK 0x0312 +#define mmSDMA4_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA4_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA4_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA4_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA4_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC5_PREEMPT 0x0318 +#define mmSDMA4_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC5_DUMMY_REG 0x0319 +#define mmSDMA4_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA4_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA4_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA4_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA4_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA4_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA4_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA4_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA4_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA4_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA4_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA4_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA4_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_CNTL 0x0340 +#define mmSDMA4_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_BASE 0x0341 +#define mmSDMA4_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA4_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_RPTR 0x0343 +#define mmSDMA4_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA4_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_WPTR 0x0345 +#define mmSDMA4_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA4_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA4_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA4_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA4_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_CNTL 0x034a +#define mmSDMA4_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_RPTR 0x034b +#define mmSDMA4_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_OFFSET 0x034c +#define mmSDMA4_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_BASE_LO 0x034d +#define mmSDMA4_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_BASE_HI 0x034e +#define mmSDMA4_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_SIZE 0x034f +#define mmSDMA4_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA4_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA4_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC6_DOORBELL 0x0352 +#define mmSDMA4_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC6_STATUS 0x0368 +#define mmSDMA4_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA4_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC6_WATERMARK 0x036a +#define mmSDMA4_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA4_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA4_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA4_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA4_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC6_PREEMPT 0x0370 +#define mmSDMA4_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC6_DUMMY_REG 0x0371 +#define mmSDMA4_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA4_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA4_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA4_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA4_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA4_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA4_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA4_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA4_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA4_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA4_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA4_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA4_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_CNTL 0x0398 +#define mmSDMA4_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_BASE 0x0399 +#define mmSDMA4_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_BASE_HI 0x039a +#define mmSDMA4_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_RPTR 0x039b +#define mmSDMA4_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA4_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_WPTR 0x039d +#define mmSDMA4_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA4_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA4_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA4_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA4_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_CNTL 0x03a2 +#define mmSDMA4_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_RPTR 0x03a3 +#define mmSDMA4_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA4_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA4_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA4_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_SIZE 0x03a7 +#define mmSDMA4_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA4_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA4_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC7_DOORBELL 0x03aa +#define mmSDMA4_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC7_STATUS 0x03c0 +#define mmSDMA4_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA4_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC7_WATERMARK 0x03c2 +#define mmSDMA4_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA4_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA4_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA4_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA4_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC7_PREEMPT 0x03c8 +#define mmSDMA4_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA4_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA4_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA4_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA4_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA4_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA4_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA4_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA4_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA4_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA4_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA4_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA4_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA4_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h new file mode 100644 index 0000000..2cc5109 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma4_4_2_2_SH_MASK_HEADER +#define _sdma4_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma4_sdma4dec +//SDMA4_UCODE_ADDR +#define SDMA4_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA4_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA4_UCODE_DATA +#define SDMA4_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA4_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA4_VM_CNTL +#define SDMA4_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA4_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA4_VM_CTX_LO +#define SDMA4_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA4_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_VM_CTX_HI +#define SDMA4_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA4_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_ACTIVE_FCN_ID +#define SDMA4_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA4_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA4_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA4_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA4_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA4_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA4_VM_CTX_CNTL +#define SDMA4_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA4_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA4_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA4_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA4_VIRT_RESET_REQ +#define SDMA4_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA4_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA4_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA4_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA4_VF_ENABLE +#define SDMA4_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA4_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA4_CONTEXT_REG_TYPE0 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE__SHIFT 0x1 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_CNTL__SHIFT 0xa +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_RPTR__SHIFT 0xb +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_SIZE__SHIFT 0xf +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_DOORBELL__SHIFT 0x12 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE_MASK 0x00000002L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_DOORBELL_MASK 0x00040000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA4_CONTEXT_REG_TYPE1 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_STATUS__SHIFT 0x8 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_WATERMARK__SHIFT 0xa +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA4_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_PREEMPT__SHIFT 0x10 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA4_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_STATUS_MASK 0x00000100L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_WATERMARK_MASK 0x00000400L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA4_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_PREEMPT_MASK 0x00010000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA4_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA4_CONTEXT_REG_TYPE2 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA4_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA4_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA4_CONTEXT_REG_TYPE3 +#define SDMA4_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA4_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA4_PUB_REG_TYPE0 +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR__SHIFT 0x0 +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA__SHIFT 0x1 +#define SDMA4_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CNTL__SHIFT 0x4 +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_LO__SHIFT 0x5 +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_HI__SHIFT 0x6 +#define SDMA4_PUB_REG_TYPE0__SDMA4_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA4_PUB_REG_TYPE0__SDMA4_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA4_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA4_PUB_REG_TYPE0__SDMA4_MMHUB_CNTL__SHIFT 0x13 +#define SDMA4_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA4_PUB_REG_TYPE0__SDMA4_POWER_CNTL__SHIFT 0x1a +#define SDMA4_PUB_REG_TYPE0__SDMA4_CLK_CTRL__SHIFT 0x1b +#define SDMA4_PUB_REG_TYPE0__SDMA4_CNTL__SHIFT 0x1c +#define SDMA4_PUB_REG_TYPE0__SDMA4_CHICKEN_BITS__SHIFT 0x1d +#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR_MASK 0x00000001L +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA_MASK 0x00000002L +#define SDMA4_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CNTL_MASK 0x00000010L +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_LO_MASK 0x00000020L +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_HI_MASK 0x00000040L +#define SDMA4_PUB_REG_TYPE0__SDMA4_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA4_PUB_REG_TYPE0__SDMA4_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA4_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_MMHUB_CNTL_MASK 0x00080000L +#define SDMA4_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_POWER_CNTL_MASK 0x04000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CLK_CTRL_MASK 0x08000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CNTL_MASK 0x10000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CHICKEN_BITS_MASK 0x20000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA4_PUB_REG_TYPE1 +#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA4_PUB_REG_TYPE1__SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA4_PUB_REG_TYPE1__SDMA4_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA4_PUB_REG_TYPE1__SDMA4_PROGRAM__SHIFT 0x4 +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS_REG__SHIFT 0x5 +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS1_REG__SHIFT 0x6 +#define SDMA4_PUB_REG_TYPE1__SDMA4_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA4_PUB_REG_TYPE1__SDMA4_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA4_PUB_REG_TYPE1__SDMA4_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA4_PUB_REG_TYPE1__SDMA4_F32_CNTL__SHIFT 0xa +#define SDMA4_PUB_REG_TYPE1__SDMA4_FREEZE__SHIFT 0xb +#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA4_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_CONFIG__SHIFT 0x12 +#define SDMA4_PUB_REG_TYPE1__SDMA4_BA_THRESHOLD__SHIFT 0x13 +#define SDMA4_PUB_REG_TYPE1__SDMA4_ID__SHIFT 0x14 +#define SDMA4_PUB_REG_TYPE1__SDMA4_VERSION__SHIFT 0x15 +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER__SHIFT 0x16 +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS2_REG__SHIFT 0x18 +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_CNTL__SHIFT 0x1c +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA4_PUB_REG_TYPE1__SDMA4_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA4_PUB_REG_TYPE1__SDMA4_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA4_PUB_REG_TYPE1__SDMA4_PROGRAM_MASK 0x00000010L +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS_REG_MASK 0x00000020L +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS1_REG_MASK 0x00000040L +#define SDMA4_PUB_REG_TYPE1__SDMA4_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA4_PUB_REG_TYPE1__SDMA4_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA4_PUB_REG_TYPE1__SDMA4_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA4_PUB_REG_TYPE1__SDMA4_F32_CNTL_MASK 0x00000400L +#define SDMA4_PUB_REG_TYPE1__SDMA4_FREEZE_MASK 0x00000800L +#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA4_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_CONFIG_MASK 0x00040000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_BA_THRESHOLD_MASK 0x00080000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_ID_MASK 0x00100000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_VERSION_MASK 0x00200000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER_MASK 0x00400000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS2_REG_MASK 0x01000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_CNTL_MASK 0x10000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA4_PUB_REG_TYPE2 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV0__SHIFT 0x0 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV1__SHIFT 0x1 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV2__SHIFT 0x2 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_PAGE__SHIFT 0x8 +#define SDMA4_PUB_REG_TYPE2__SDMA4_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA4_PUB_REG_TYPE2__SDMA4_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA4_PUB_REG_TYPE2__SDMA4_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA4_PUB_REG_TYPE2__SDMA4_STATUS3_REG__SHIFT 0xc +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA4_PUB_REG_TYPE2__SDMA4_ERROR_LOG__SHIFT 0x10 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA4_PUB_REG_TYPE2__SDMA4_F32_COUNTER__SHIFT 0x15 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UNBREAKABLE__SHIFT 0x16 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFMON_CNTL__SHIFT 0x17 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA4_PUB_REG_TYPE2__SDMA4_CRD_CNTL__SHIFT 0x1b +#define SDMA4_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA4_PUB_REG_TYPE2__SDMA4_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA4_PUB_REG_TYPE2__SDMA4_ULV_CNTL__SHIFT 0x1e +#define SDMA4_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV0_MASK 0x00000001L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV1_MASK 0x00000002L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV2_MASK 0x00000004L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_PAGE_MASK 0x00000100L +#define SDMA4_PUB_REG_TYPE2__SDMA4_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA4_PUB_REG_TYPE2__SDMA4_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA4_PUB_REG_TYPE2__SDMA4_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA4_PUB_REG_TYPE2__SDMA4_STATUS3_REG_MASK 0x00001000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_ERROR_LOG_MASK 0x00010000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_F32_COUNTER_MASK 0x00200000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UNBREAKABLE_MASK 0x00400000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFMON_CNTL_MASK 0x00800000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_CRD_CNTL_MASK 0x08000000L +#define SDMA4_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_ULV_CNTL_MASK 0x40000000L +#define SDMA4_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA4_PUB_REG_TYPE3 +#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA4_PUB_REG_TYPE3__SDMA4_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA4_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA4_PUB_REG_TYPE3__SDMA4_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA4_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA4_MMHUB_CNTL +#define SDMA4_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA4_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA4_CONTEXT_GROUP_BOUNDARY +#define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA4_POWER_CNTL +#define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA4_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA4_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA4_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA4_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA4_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA4_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA4_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA4_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA4_CLK_CTRL +#define SDMA4_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA4_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA4_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA4_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA4_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA4_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA4_CNTL +#define SDMA4_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA4_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA4_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA4_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA4_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA4_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA4_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA4_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA4_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA4_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA4_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA4_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA4_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA4_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA4_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA4_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA4_CHICKEN_BITS +#define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA4_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA4_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA4_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA4_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA4_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA4_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA4_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA4_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA4_GB_ADDR_CONFIG +#define SDMA4_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA4_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA4_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA4_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA4_GB_ADDR_CONFIG_READ +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA4_RB_RPTR_FETCH_HI +#define SDMA4_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA4_RB_RPTR_FETCH +#define SDMA4_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA4_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA4_IB_OFFSET_FETCH +#define SDMA4_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA4_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA4_PROGRAM +#define SDMA4_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA4_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA4_STATUS_REG +#define SDMA4_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA4_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA4_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA4_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA4_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA4_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA4_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA4_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA4_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA4_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA4_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA4_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA4_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA4_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA4_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA4_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA4_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA4_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA4_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA4_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA4_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA4_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA4_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA4_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA4_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA4_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA4_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA4_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA4_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA4_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA4_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA4_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA4_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA4_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA4_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA4_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA4_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA4_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA4_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA4_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA4_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA4_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA4_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA4_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA4_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA4_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA4_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA4_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA4_STATUS1_REG +#define SDMA4_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA4_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA4_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA4_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA4_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA4_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA4_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA4_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA4_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA4_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA4_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA4_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA4_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA4_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA4_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA4_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA4_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA4_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA4_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA4_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA4_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA4_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA4_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA4_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA4_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA4_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA4_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA4_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA4_RD_BURST_CNTL +#define SDMA4_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA4_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA4_HBM_PAGE_CONFIG +#define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA4_UCODE_CHECKSUM +#define SDMA4_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA4_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA4_F32_CNTL +#define SDMA4_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA4_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA4_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA4_F32_CNTL__STEP_MASK 0x00000002L +//SDMA4_FREEZE +#define SDMA4_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA4_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA4_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA4_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA4_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA4_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA4_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA4_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA4_PHASE0_QUANTUM +#define SDMA4_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA4_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA4_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA4_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA4_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA4_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA4_PHASE1_QUANTUM +#define SDMA4_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA4_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA4_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA4_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA4_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA4_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA4_EDC_CONFIG +#define SDMA4_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA4_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA4_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA4_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA4_BA_THRESHOLD +#define SDMA4_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA4_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA4_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA4_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA4_ID +#define SDMA4_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA4_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA4_VERSION +#define SDMA4_VERSION__MINVER__SHIFT 0x0 +#define SDMA4_VERSION__MAJVER__SHIFT 0x8 +#define SDMA4_VERSION__REV__SHIFT 0x10 +#define SDMA4_VERSION__MINVER_MASK 0x0000007FL +#define SDMA4_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA4_VERSION__REV_MASK 0x003F0000L +//SDMA4_EDC_COUNTER +#define SDMA4_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA4_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA4_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA4_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA4_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA4_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA4_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA4_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA4_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA4_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA4_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA4_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA4_EDC_COUNTER_CLEAR +#define SDMA4_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA4_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA4_STATUS2_REG +#define SDMA4_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA4_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA4_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA4_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA4_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA4_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA4_ATOMIC_CNTL +#define SDMA4_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA4_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA4_ATOMIC_PREOP_LO +#define SDMA4_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA4_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA4_ATOMIC_PREOP_HI +#define SDMA4_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA4_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_CNTL +#define SDMA4_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA4_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA4_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA4_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA4_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA4_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA4_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA4_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA4_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA4_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA4_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA4_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA4_UTCL1_WATERMK +#define SDMA4_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA4_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA4_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA4_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA4_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA4_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA4_UTCL1_RD_STATUS +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA4_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA4_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA4_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA4_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA4_UTCL1_WR_STATUS +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA4_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA4_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA4_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA4_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA4_UTCL1_INV0 +#define SDMA4_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA4_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA4_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA4_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA4_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA4_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA4_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA4_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA4_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA4_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA4_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA4_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA4_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA4_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA4_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA4_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA4_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA4_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA4_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA4_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA4_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA4_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA4_UTCL1_INV1 +#define SDMA4_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA4_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_INV2 +#define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_RD_XNACK0 +#define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_RD_XNACK1 +#define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA4_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA4_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA4_UTCL1_WR_XNACK0 +#define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_WR_XNACK1 +#define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA4_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA4_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA4_UTCL1_TIMEOUT +#define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA4_UTCL1_PAGE +#define SDMA4_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA4_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA4_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA4_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA4_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA4_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA4_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA4_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA4_POWER_CNTL_IDLE +#define SDMA4_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA4_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA4_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA4_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA4_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA4_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA4_RELAX_ORDERING_LUT +#define SDMA4_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA4_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA4_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA4_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA4_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA4_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA4_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA4_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA4_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA4_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA4_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA4_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA4_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA4_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA4_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA4_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA4_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA4_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA4_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA4_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA4_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA4_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA4_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA4_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA4_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA4_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA4_CHICKEN_BITS_2 +#define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA4_STATUS3_REG +#define SDMA4_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA4_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA4_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA4_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA4_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA4_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA4_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA4_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA4_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA4_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA4_PHYSICAL_ADDR_LO +#define SDMA4_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA4_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA4_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA4_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA4_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA4_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA4_PHYSICAL_ADDR_HI +#define SDMA4_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA4_PHASE2_QUANTUM +#define SDMA4_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA4_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA4_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA4_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA4_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA4_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA4_ERROR_LOG +#define SDMA4_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA4_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA4_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA4_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA4_PUB_DUMMY_REG0 +#define SDMA4_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA4_PUB_DUMMY_REG1 +#define SDMA4_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA4_PUB_DUMMY_REG2 +#define SDMA4_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA4_PUB_DUMMY_REG3 +#define SDMA4_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA4_F32_COUNTER +#define SDMA4_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA4_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA4_UNBREAKABLE +#define SDMA4_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA4_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA4_PERFMON_CNTL +#define SDMA4_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA4_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA4_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA4_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA4_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA4_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA4_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA4_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA4_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA4_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA4_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA4_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA4_PERFCOUNTER0_RESULT +#define SDMA4_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA4_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA4_PERFCOUNTER1_RESULT +#define SDMA4_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA4_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA4_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA4_CRD_CNTL +#define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA4_GPU_IOV_VIOLATION_LOG +#define SDMA4_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA4_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA4_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA4_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA4_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA4_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA4_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA4_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA4_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA4_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA4_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA4_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA4_ULV_CNTL +#define SDMA4_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA4_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA4_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA4_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA4_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA4_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA4_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA4_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA4_EA_DBIT_ADDR_DATA +#define SDMA4_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA4_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA4_EA_DBIT_ADDR_INDEX +#define SDMA4_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA4_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA4_GPU_IOV_VIOLATION_LOG2 +#define SDMA4_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA4_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA4_GFX_RB_CNTL +#define SDMA4_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_GFX_RB_BASE +#define SDMA4_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_BASE_HI +#define SDMA4_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_GFX_RB_RPTR +#define SDMA4_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_RPTR_HI +#define SDMA4_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR +#define SDMA4_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_HI +#define SDMA4_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_POLL_CNTL +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_GFX_RB_RPTR_ADDR_HI +#define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_RPTR_ADDR_LO +#define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_GFX_IB_CNTL +#define SDMA4_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_GFX_IB_RPTR +#define SDMA4_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_GFX_IB_OFFSET +#define SDMA4_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_GFX_IB_BASE_LO +#define SDMA4_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_GFX_IB_BASE_HI +#define SDMA4_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_IB_SIZE +#define SDMA4_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_GFX_SKIP_CNTL +#define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_GFX_CONTEXT_STATUS +#define SDMA4_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_GFX_DOORBELL +#define SDMA4_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_GFX_CONTEXT_CNTL +#define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA4_GFX_STATUS +#define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_GFX_DOORBELL_LOG +#define SDMA4_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_GFX_WATERMARK +#define SDMA4_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_GFX_DOORBELL_OFFSET +#define SDMA4_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_GFX_CSA_ADDR_LO +#define SDMA4_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_GFX_CSA_ADDR_HI +#define SDMA4_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_IB_SUB_REMAIN +#define SDMA4_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_GFX_PREEMPT +#define SDMA4_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_GFX_DUMMY_REG +#define SDMA4_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_GFX_RB_AQL_CNTL +#define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_GFX_MINOR_PTR_UPDATE +#define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_GFX_MIDCMD_DATA0 +#define SDMA4_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA1 +#define SDMA4_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA2 +#define SDMA4_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA3 +#define SDMA4_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA4 +#define SDMA4_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA5 +#define SDMA4_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA6 +#define SDMA4_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA7 +#define SDMA4_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA8 +#define SDMA4_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_CNTL +#define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_PAGE_RB_CNTL +#define SDMA4_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_PAGE_RB_BASE +#define SDMA4_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_BASE_HI +#define SDMA4_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_PAGE_RB_RPTR +#define SDMA4_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_RPTR_HI +#define SDMA4_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR +#define SDMA4_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_HI +#define SDMA4_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_POLL_CNTL +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_PAGE_RB_RPTR_ADDR_HI +#define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_RPTR_ADDR_LO +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_PAGE_IB_CNTL +#define SDMA4_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_PAGE_IB_RPTR +#define SDMA4_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_PAGE_IB_OFFSET +#define SDMA4_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_PAGE_IB_BASE_LO +#define SDMA4_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_PAGE_IB_BASE_HI +#define SDMA4_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_IB_SIZE +#define SDMA4_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_PAGE_SKIP_CNTL +#define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_PAGE_CONTEXT_STATUS +#define SDMA4_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_PAGE_DOORBELL +#define SDMA4_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_PAGE_STATUS +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_PAGE_DOORBELL_LOG +#define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_PAGE_WATERMARK +#define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_PAGE_DOORBELL_OFFSET +#define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_PAGE_CSA_ADDR_LO +#define SDMA4_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_PAGE_CSA_ADDR_HI +#define SDMA4_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_IB_SUB_REMAIN +#define SDMA4_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_PAGE_PREEMPT +#define SDMA4_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_PAGE_DUMMY_REG +#define SDMA4_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_PAGE_RB_AQL_CNTL +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_PAGE_MINOR_PTR_UPDATE +#define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_PAGE_MIDCMD_DATA0 +#define SDMA4_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA1 +#define SDMA4_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA2 +#define SDMA4_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA3 +#define SDMA4_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA4 +#define SDMA4_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA5 +#define SDMA4_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA6 +#define SDMA4_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA7 +#define SDMA4_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA8 +#define SDMA4_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_CNTL +#define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC0_RB_CNTL +#define SDMA4_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC0_RB_BASE +#define SDMA4_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_BASE_HI +#define SDMA4_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC0_RB_RPTR +#define SDMA4_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_RPTR_HI +#define SDMA4_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR +#define SDMA4_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_HI +#define SDMA4_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_POLL_CNTL +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC0_RB_RPTR_ADDR_HI +#define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_RPTR_ADDR_LO +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC0_IB_CNTL +#define SDMA4_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC0_IB_RPTR +#define SDMA4_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC0_IB_OFFSET +#define SDMA4_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC0_IB_BASE_LO +#define SDMA4_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC0_IB_BASE_HI +#define SDMA4_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_IB_SIZE +#define SDMA4_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC0_SKIP_CNTL +#define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC0_CONTEXT_STATUS +#define SDMA4_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC0_DOORBELL +#define SDMA4_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC0_STATUS +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC0_DOORBELL_LOG +#define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC0_WATERMARK +#define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC0_DOORBELL_OFFSET +#define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC0_CSA_ADDR_LO +#define SDMA4_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC0_CSA_ADDR_HI +#define SDMA4_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_IB_SUB_REMAIN +#define SDMA4_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC0_PREEMPT +#define SDMA4_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC0_DUMMY_REG +#define SDMA4_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC0_RB_AQL_CNTL +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC0_MINOR_PTR_UPDATE +#define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC0_MIDCMD_DATA0 +#define SDMA4_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA1 +#define SDMA4_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA2 +#define SDMA4_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA3 +#define SDMA4_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA4 +#define SDMA4_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA5 +#define SDMA4_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA6 +#define SDMA4_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA7 +#define SDMA4_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA8 +#define SDMA4_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_CNTL +#define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC1_RB_CNTL +#define SDMA4_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC1_RB_BASE +#define SDMA4_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_BASE_HI +#define SDMA4_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC1_RB_RPTR +#define SDMA4_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_RPTR_HI +#define SDMA4_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR +#define SDMA4_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_HI +#define SDMA4_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_POLL_CNTL +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC1_RB_RPTR_ADDR_HI +#define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_RPTR_ADDR_LO +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC1_IB_CNTL +#define SDMA4_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC1_IB_RPTR +#define SDMA4_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC1_IB_OFFSET +#define SDMA4_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC1_IB_BASE_LO +#define SDMA4_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC1_IB_BASE_HI +#define SDMA4_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_IB_SIZE +#define SDMA4_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC1_SKIP_CNTL +#define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC1_CONTEXT_STATUS +#define SDMA4_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC1_DOORBELL +#define SDMA4_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC1_STATUS +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC1_DOORBELL_LOG +#define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC1_WATERMARK +#define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC1_DOORBELL_OFFSET +#define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC1_CSA_ADDR_LO +#define SDMA4_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC1_CSA_ADDR_HI +#define SDMA4_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_IB_SUB_REMAIN +#define SDMA4_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC1_PREEMPT +#define SDMA4_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC1_DUMMY_REG +#define SDMA4_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC1_RB_AQL_CNTL +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC1_MINOR_PTR_UPDATE +#define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC1_MIDCMD_DATA0 +#define SDMA4_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA1 +#define SDMA4_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA2 +#define SDMA4_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA3 +#define SDMA4_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA4 +#define SDMA4_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA5 +#define SDMA4_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA6 +#define SDMA4_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA7 +#define SDMA4_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA8 +#define SDMA4_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_CNTL +#define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC2_RB_CNTL +#define SDMA4_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC2_RB_BASE +#define SDMA4_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_BASE_HI +#define SDMA4_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC2_RB_RPTR +#define SDMA4_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_RPTR_HI +#define SDMA4_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR +#define SDMA4_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_HI +#define SDMA4_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_POLL_CNTL +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC2_RB_RPTR_ADDR_HI +#define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_RPTR_ADDR_LO +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC2_IB_CNTL +#define SDMA4_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC2_IB_RPTR +#define SDMA4_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC2_IB_OFFSET +#define SDMA4_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC2_IB_BASE_LO +#define SDMA4_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC2_IB_BASE_HI +#define SDMA4_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_IB_SIZE +#define SDMA4_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC2_SKIP_CNTL +#define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC2_CONTEXT_STATUS +#define SDMA4_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC2_DOORBELL +#define SDMA4_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC2_STATUS +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC2_DOORBELL_LOG +#define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC2_WATERMARK +#define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC2_DOORBELL_OFFSET +#define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC2_CSA_ADDR_LO +#define SDMA4_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC2_CSA_ADDR_HI +#define SDMA4_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_IB_SUB_REMAIN +#define SDMA4_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC2_PREEMPT +#define SDMA4_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC2_DUMMY_REG +#define SDMA4_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC2_RB_AQL_CNTL +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC2_MINOR_PTR_UPDATE +#define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC2_MIDCMD_DATA0 +#define SDMA4_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA1 +#define SDMA4_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA2 +#define SDMA4_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA3 +#define SDMA4_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA4 +#define SDMA4_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA5 +#define SDMA4_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA6 +#define SDMA4_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA7 +#define SDMA4_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA8 +#define SDMA4_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_CNTL +#define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC3_RB_CNTL +#define SDMA4_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC3_RB_BASE +#define SDMA4_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_BASE_HI +#define SDMA4_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC3_RB_RPTR +#define SDMA4_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_RPTR_HI +#define SDMA4_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR +#define SDMA4_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_HI +#define SDMA4_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_POLL_CNTL +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC3_RB_RPTR_ADDR_HI +#define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_RPTR_ADDR_LO +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC3_IB_CNTL +#define SDMA4_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC3_IB_RPTR +#define SDMA4_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC3_IB_OFFSET +#define SDMA4_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC3_IB_BASE_LO +#define SDMA4_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC3_IB_BASE_HI +#define SDMA4_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_IB_SIZE +#define SDMA4_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC3_SKIP_CNTL +#define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC3_CONTEXT_STATUS +#define SDMA4_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC3_DOORBELL +#define SDMA4_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC3_STATUS +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC3_DOORBELL_LOG +#define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC3_WATERMARK +#define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC3_DOORBELL_OFFSET +#define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC3_CSA_ADDR_LO +#define SDMA4_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC3_CSA_ADDR_HI +#define SDMA4_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_IB_SUB_REMAIN +#define SDMA4_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC3_PREEMPT +#define SDMA4_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC3_DUMMY_REG +#define SDMA4_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC3_RB_AQL_CNTL +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC3_MINOR_PTR_UPDATE +#define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC3_MIDCMD_DATA0 +#define SDMA4_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA1 +#define SDMA4_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA2 +#define SDMA4_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA3 +#define SDMA4_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA4 +#define SDMA4_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA5 +#define SDMA4_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA6 +#define SDMA4_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA7 +#define SDMA4_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA8 +#define SDMA4_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_CNTL +#define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC4_RB_CNTL +#define SDMA4_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC4_RB_BASE +#define SDMA4_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_BASE_HI +#define SDMA4_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC4_RB_RPTR +#define SDMA4_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_RPTR_HI +#define SDMA4_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR +#define SDMA4_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_HI +#define SDMA4_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_POLL_CNTL +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC4_RB_RPTR_ADDR_HI +#define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_RPTR_ADDR_LO +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC4_IB_CNTL +#define SDMA4_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC4_IB_RPTR +#define SDMA4_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC4_IB_OFFSET +#define SDMA4_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC4_IB_BASE_LO +#define SDMA4_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC4_IB_BASE_HI +#define SDMA4_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_IB_SIZE +#define SDMA4_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC4_SKIP_CNTL +#define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC4_CONTEXT_STATUS +#define SDMA4_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC4_DOORBELL +#define SDMA4_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC4_STATUS +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC4_DOORBELL_LOG +#define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC4_WATERMARK +#define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC4_DOORBELL_OFFSET +#define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC4_CSA_ADDR_LO +#define SDMA4_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC4_CSA_ADDR_HI +#define SDMA4_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_IB_SUB_REMAIN +#define SDMA4_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC4_PREEMPT +#define SDMA4_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC4_DUMMY_REG +#define SDMA4_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC4_RB_AQL_CNTL +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC4_MINOR_PTR_UPDATE +#define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC4_MIDCMD_DATA0 +#define SDMA4_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA1 +#define SDMA4_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA2 +#define SDMA4_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA3 +#define SDMA4_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA4 +#define SDMA4_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA5 +#define SDMA4_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA6 +#define SDMA4_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA7 +#define SDMA4_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA8 +#define SDMA4_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_CNTL +#define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC5_RB_CNTL +#define SDMA4_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC5_RB_BASE +#define SDMA4_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_BASE_HI +#define SDMA4_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC5_RB_RPTR +#define SDMA4_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_RPTR_HI +#define SDMA4_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR +#define SDMA4_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_HI +#define SDMA4_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_POLL_CNTL +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC5_RB_RPTR_ADDR_HI +#define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_RPTR_ADDR_LO +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC5_IB_CNTL +#define SDMA4_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC5_IB_RPTR +#define SDMA4_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC5_IB_OFFSET +#define SDMA4_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC5_IB_BASE_LO +#define SDMA4_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC5_IB_BASE_HI +#define SDMA4_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_IB_SIZE +#define SDMA4_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC5_SKIP_CNTL +#define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC5_CONTEXT_STATUS +#define SDMA4_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC5_DOORBELL +#define SDMA4_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC5_STATUS +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC5_DOORBELL_LOG +#define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC5_WATERMARK +#define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC5_DOORBELL_OFFSET +#define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC5_CSA_ADDR_LO +#define SDMA4_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC5_CSA_ADDR_HI +#define SDMA4_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_IB_SUB_REMAIN +#define SDMA4_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC5_PREEMPT +#define SDMA4_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC5_DUMMY_REG +#define SDMA4_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC5_RB_AQL_CNTL +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC5_MINOR_PTR_UPDATE +#define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC5_MIDCMD_DATA0 +#define SDMA4_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA1 +#define SDMA4_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA2 +#define SDMA4_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA3 +#define SDMA4_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA4 +#define SDMA4_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA5 +#define SDMA4_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA6 +#define SDMA4_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA7 +#define SDMA4_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA8 +#define SDMA4_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_CNTL +#define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC6_RB_CNTL +#define SDMA4_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC6_RB_BASE +#define SDMA4_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_BASE_HI +#define SDMA4_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC6_RB_RPTR +#define SDMA4_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_RPTR_HI +#define SDMA4_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR +#define SDMA4_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_HI +#define SDMA4_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_POLL_CNTL +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC6_RB_RPTR_ADDR_HI +#define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_RPTR_ADDR_LO +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC6_IB_CNTL +#define SDMA4_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC6_IB_RPTR +#define SDMA4_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC6_IB_OFFSET +#define SDMA4_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC6_IB_BASE_LO +#define SDMA4_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC6_IB_BASE_HI +#define SDMA4_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_IB_SIZE +#define SDMA4_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC6_SKIP_CNTL +#define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC6_CONTEXT_STATUS +#define SDMA4_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC6_DOORBELL +#define SDMA4_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC6_STATUS +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC6_DOORBELL_LOG +#define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC6_WATERMARK +#define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC6_DOORBELL_OFFSET +#define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC6_CSA_ADDR_LO +#define SDMA4_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC6_CSA_ADDR_HI +#define SDMA4_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_IB_SUB_REMAIN +#define SDMA4_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC6_PREEMPT +#define SDMA4_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC6_DUMMY_REG +#define SDMA4_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC6_RB_AQL_CNTL +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC6_MINOR_PTR_UPDATE +#define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC6_MIDCMD_DATA0 +#define SDMA4_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA1 +#define SDMA4_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA2 +#define SDMA4_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA3 +#define SDMA4_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA4 +#define SDMA4_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA5 +#define SDMA4_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA6 +#define SDMA4_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA7 +#define SDMA4_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA8 +#define SDMA4_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_CNTL +#define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC7_RB_CNTL +#define SDMA4_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC7_RB_BASE +#define SDMA4_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_BASE_HI +#define SDMA4_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC7_RB_RPTR +#define SDMA4_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_RPTR_HI +#define SDMA4_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR +#define SDMA4_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_HI +#define SDMA4_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_POLL_CNTL +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC7_RB_RPTR_ADDR_HI +#define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_RPTR_ADDR_LO +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC7_IB_CNTL +#define SDMA4_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC7_IB_RPTR +#define SDMA4_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC7_IB_OFFSET +#define SDMA4_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC7_IB_BASE_LO +#define SDMA4_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC7_IB_BASE_HI +#define SDMA4_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_IB_SIZE +#define SDMA4_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC7_SKIP_CNTL +#define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC7_CONTEXT_STATUS +#define SDMA4_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC7_DOORBELL +#define SDMA4_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC7_STATUS +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC7_DOORBELL_LOG +#define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC7_WATERMARK +#define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC7_DOORBELL_OFFSET +#define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC7_CSA_ADDR_LO +#define SDMA4_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC7_CSA_ADDR_HI +#define SDMA4_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_IB_SUB_REMAIN +#define SDMA4_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC7_PREEMPT +#define SDMA4_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC7_DUMMY_REG +#define SDMA4_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC7_RB_AQL_CNTL +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC7_MINOR_PTR_UPDATE +#define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC7_MIDCMD_DATA0 +#define SDMA4_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA1 +#define SDMA4_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA2 +#define SDMA4_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA3 +#define SDMA4_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA4 +#define SDMA4_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA5 +#define SDMA4_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA6 +#define SDMA4_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA7 +#define SDMA4_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA8 +#define SDMA4_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_CNTL +#define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h new file mode 100644 index 0000000..ecb51b9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma5_4_2_2_OFFSET_HEADER +#define _sdma5_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma5_sdma5dec +// base address: 0x7b000 +#define mmSDMA5_UCODE_ADDR 0x0000 +#define mmSDMA5_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA5_UCODE_DATA 0x0001 +#define mmSDMA5_UCODE_DATA_BASE_IDX 1 +#define mmSDMA5_VM_CNTL 0x0004 +#define mmSDMA5_VM_CNTL_BASE_IDX 1 +#define mmSDMA5_VM_CTX_LO 0x0005 +#define mmSDMA5_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA5_VM_CTX_HI 0x0006 +#define mmSDMA5_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA5_ACTIVE_FCN_ID 0x0007 +#define mmSDMA5_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA5_VM_CTX_CNTL 0x0008 +#define mmSDMA5_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA5_VIRT_RESET_REQ 0x0009 +#define mmSDMA5_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA5_VF_ENABLE 0x000a +#define mmSDMA5_VF_ENABLE_BASE_IDX 1 +#define mmSDMA5_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA5_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA5_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA5_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA5_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA5_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA5_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA5_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA5_PUB_REG_TYPE0 0x000f +#define mmSDMA5_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA5_PUB_REG_TYPE1 0x0010 +#define mmSDMA5_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA5_PUB_REG_TYPE2 0x0011 +#define mmSDMA5_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA5_PUB_REG_TYPE3 0x0012 +#define mmSDMA5_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA5_MMHUB_CNTL 0x0013 +#define mmSDMA5_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA5_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA5_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA5_POWER_CNTL 0x001a +#define mmSDMA5_POWER_CNTL_BASE_IDX 1 +#define mmSDMA5_CLK_CTRL 0x001b +#define mmSDMA5_CLK_CTRL_BASE_IDX 1 +#define mmSDMA5_CNTL 0x001c +#define mmSDMA5_CNTL_BASE_IDX 1 +#define mmSDMA5_CHICKEN_BITS 0x001d +#define mmSDMA5_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA5_GB_ADDR_CONFIG 0x001e +#define mmSDMA5_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA5_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA5_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA5_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA5_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA5_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA5_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA5_RB_RPTR_FETCH 0x0022 +#define mmSDMA5_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA5_IB_OFFSET_FETCH 0x0023 +#define mmSDMA5_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA5_PROGRAM 0x0024 +#define mmSDMA5_PROGRAM_BASE_IDX 1 +#define mmSDMA5_STATUS_REG 0x0025 +#define mmSDMA5_STATUS_REG_BASE_IDX 1 +#define mmSDMA5_STATUS1_REG 0x0026 +#define mmSDMA5_STATUS1_REG_BASE_IDX 1 +#define mmSDMA5_RD_BURST_CNTL 0x0027 +#define mmSDMA5_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA5_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA5_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA5_UCODE_CHECKSUM 0x0029 +#define mmSDMA5_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA5_F32_CNTL 0x002a +#define mmSDMA5_F32_CNTL_BASE_IDX 1 +#define mmSDMA5_FREEZE 0x002b +#define mmSDMA5_FREEZE_BASE_IDX 1 +#define mmSDMA5_PHASE0_QUANTUM 0x002c +#define mmSDMA5_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA5_PHASE1_QUANTUM 0x002d +#define mmSDMA5_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA5_EDC_CONFIG 0x0032 +#define mmSDMA5_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA5_BA_THRESHOLD 0x0033 +#define mmSDMA5_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA5_ID 0x0034 +#define mmSDMA5_ID_BASE_IDX 1 +#define mmSDMA5_VERSION 0x0035 +#define mmSDMA5_VERSION_BASE_IDX 1 +#define mmSDMA5_EDC_COUNTER 0x0036 +#define mmSDMA5_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA5_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA5_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA5_STATUS2_REG 0x0038 +#define mmSDMA5_STATUS2_REG_BASE_IDX 1 +#define mmSDMA5_ATOMIC_CNTL 0x0039 +#define mmSDMA5_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA5_ATOMIC_PREOP_LO 0x003a +#define mmSDMA5_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA5_ATOMIC_PREOP_HI 0x003b +#define mmSDMA5_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA5_UTCL1_CNTL 0x003c +#define mmSDMA5_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA5_UTCL1_WATERMK 0x003d +#define mmSDMA5_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA5_UTCL1_RD_STATUS 0x003e +#define mmSDMA5_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA5_UTCL1_WR_STATUS 0x003f +#define mmSDMA5_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA5_UTCL1_INV0 0x0040 +#define mmSDMA5_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA5_UTCL1_INV1 0x0041 +#define mmSDMA5_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA5_UTCL1_INV2 0x0042 +#define mmSDMA5_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA5_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA5_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA5_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA5_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA5_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA5_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA5_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA5_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA5_UTCL1_TIMEOUT 0x0047 +#define mmSDMA5_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA5_UTCL1_PAGE 0x0048 +#define mmSDMA5_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA5_POWER_CNTL_IDLE 0x0049 +#define mmSDMA5_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA5_RELAX_ORDERING_LUT 0x004a +#define mmSDMA5_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA5_CHICKEN_BITS_2 0x004b +#define mmSDMA5_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA5_STATUS3_REG 0x004c +#define mmSDMA5_STATUS3_REG_BASE_IDX 1 +#define mmSDMA5_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA5_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA5_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_PHASE2_QUANTUM 0x004f +#define mmSDMA5_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA5_ERROR_LOG 0x0050 +#define mmSDMA5_ERROR_LOG_BASE_IDX 1 +#define mmSDMA5_PUB_DUMMY_REG0 0x0051 +#define mmSDMA5_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA5_PUB_DUMMY_REG1 0x0052 +#define mmSDMA5_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA5_PUB_DUMMY_REG2 0x0053 +#define mmSDMA5_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA5_PUB_DUMMY_REG3 0x0054 +#define mmSDMA5_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA5_F32_COUNTER 0x0055 +#define mmSDMA5_F32_COUNTER_BASE_IDX 1 +#define mmSDMA5_UNBREAKABLE 0x0056 +#define mmSDMA5_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA5_PERFMON_CNTL 0x0057 +#define mmSDMA5_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA5_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA5_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA5_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA5_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA5_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA5_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA5_CRD_CNTL 0x005b +#define mmSDMA5_CRD_CNTL_BASE_IDX 1 +#define mmSDMA5_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA5_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA5_ULV_CNTL 0x005e +#define mmSDMA5_ULV_CNTL_BASE_IDX 1 +#define mmSDMA5_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA5_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA5_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA5_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA5_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA5_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA5_GFX_RB_CNTL 0x0080 +#define mmSDMA5_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_RB_BASE 0x0081 +#define mmSDMA5_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA5_GFX_RB_BASE_HI 0x0082 +#define mmSDMA5_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_GFX_RB_RPTR 0x0083 +#define mmSDMA5_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA5_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_GFX_RB_WPTR 0x0085 +#define mmSDMA5_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA5_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA5_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA5_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA5_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_GFX_IB_CNTL 0x008a +#define mmSDMA5_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_IB_RPTR 0x008b +#define mmSDMA5_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_GFX_IB_OFFSET 0x008c +#define mmSDMA5_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_GFX_IB_BASE_LO 0x008d +#define mmSDMA5_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_GFX_IB_BASE_HI 0x008e +#define mmSDMA5_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_GFX_IB_SIZE 0x008f +#define mmSDMA5_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_GFX_SKIP_CNTL 0x0090 +#define mmSDMA5_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA5_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_GFX_DOORBELL 0x0092 +#define mmSDMA5_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA5_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA5_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_STATUS 0x00a8 +#define mmSDMA5_GFX_STATUS_BASE_IDX 1 +#define mmSDMA5_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA5_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_GFX_WATERMARK 0x00aa +#define mmSDMA5_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA5_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA5_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA5_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA5_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA5_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_GFX_PREEMPT 0x00b0 +#define mmSDMA5_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA5_GFX_DUMMY_REG 0x00b1 +#define mmSDMA5_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA5_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA5_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA5_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA5_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA5_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA5_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA5_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA5_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA5_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA5_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA5_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA5_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_CNTL 0x00d8 +#define mmSDMA5_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_BASE 0x00d9 +#define mmSDMA5_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_BASE_HI 0x00da +#define mmSDMA5_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_RPTR 0x00db +#define mmSDMA5_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA5_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_WPTR 0x00dd +#define mmSDMA5_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA5_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA5_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA5_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA5_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_CNTL 0x00e2 +#define mmSDMA5_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_RPTR 0x00e3 +#define mmSDMA5_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA5_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA5_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA5_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_SIZE 0x00e7 +#define mmSDMA5_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA5_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA5_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_PAGE_DOORBELL 0x00ea +#define mmSDMA5_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA5_PAGE_STATUS 0x0100 +#define mmSDMA5_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA5_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA5_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_PAGE_WATERMARK 0x0102 +#define mmSDMA5_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA5_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA5_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA5_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA5_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA5_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_PAGE_PREEMPT 0x0108 +#define mmSDMA5_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA5_PAGE_DUMMY_REG 0x0109 +#define mmSDMA5_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA5_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA5_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA5_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA5_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA5_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA5_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA5_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA5_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA5_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA5_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA5_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA5_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_CNTL 0x0130 +#define mmSDMA5_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_BASE 0x0131 +#define mmSDMA5_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA5_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_RPTR 0x0133 +#define mmSDMA5_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA5_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_WPTR 0x0135 +#define mmSDMA5_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA5_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA5_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA5_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA5_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_CNTL 0x013a +#define mmSDMA5_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_RPTR 0x013b +#define mmSDMA5_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_OFFSET 0x013c +#define mmSDMA5_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_BASE_LO 0x013d +#define mmSDMA5_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_BASE_HI 0x013e +#define mmSDMA5_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_SIZE 0x013f +#define mmSDMA5_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA5_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA5_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC0_DOORBELL 0x0142 +#define mmSDMA5_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC0_STATUS 0x0158 +#define mmSDMA5_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA5_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC0_WATERMARK 0x015a +#define mmSDMA5_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA5_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA5_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA5_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA5_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC0_PREEMPT 0x0160 +#define mmSDMA5_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC0_DUMMY_REG 0x0161 +#define mmSDMA5_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA5_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA5_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA5_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA5_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA5_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA5_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA5_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA5_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA5_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA5_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA5_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA5_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_CNTL 0x0188 +#define mmSDMA5_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_BASE 0x0189 +#define mmSDMA5_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_BASE_HI 0x018a +#define mmSDMA5_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_RPTR 0x018b +#define mmSDMA5_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA5_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_WPTR 0x018d +#define mmSDMA5_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA5_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA5_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA5_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA5_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_CNTL 0x0192 +#define mmSDMA5_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_RPTR 0x0193 +#define mmSDMA5_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_OFFSET 0x0194 +#define mmSDMA5_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA5_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA5_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_SIZE 0x0197 +#define mmSDMA5_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA5_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA5_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC1_DOORBELL 0x019a +#define mmSDMA5_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC1_STATUS 0x01b0 +#define mmSDMA5_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA5_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC1_WATERMARK 0x01b2 +#define mmSDMA5_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA5_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA5_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA5_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA5_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC1_PREEMPT 0x01b8 +#define mmSDMA5_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA5_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA5_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA5_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA5_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA5_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA5_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA5_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA5_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA5_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA5_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA5_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA5_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA5_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_CNTL 0x01e0 +#define mmSDMA5_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_BASE 0x01e1 +#define mmSDMA5_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA5_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_RPTR 0x01e3 +#define mmSDMA5_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA5_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_WPTR 0x01e5 +#define mmSDMA5_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA5_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA5_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA5_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA5_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_CNTL 0x01ea +#define mmSDMA5_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_RPTR 0x01eb +#define mmSDMA5_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_OFFSET 0x01ec +#define mmSDMA5_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA5_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA5_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_SIZE 0x01ef +#define mmSDMA5_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA5_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA5_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC2_DOORBELL 0x01f2 +#define mmSDMA5_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC2_STATUS 0x0208 +#define mmSDMA5_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA5_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC2_WATERMARK 0x020a +#define mmSDMA5_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA5_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA5_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA5_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA5_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC2_PREEMPT 0x0210 +#define mmSDMA5_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC2_DUMMY_REG 0x0211 +#define mmSDMA5_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA5_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA5_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA5_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA5_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA5_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA5_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA5_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA5_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA5_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA5_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA5_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA5_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_CNTL 0x0238 +#define mmSDMA5_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_BASE 0x0239 +#define mmSDMA5_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_BASE_HI 0x023a +#define mmSDMA5_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_RPTR 0x023b +#define mmSDMA5_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA5_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_WPTR 0x023d +#define mmSDMA5_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA5_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA5_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA5_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA5_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_CNTL 0x0242 +#define mmSDMA5_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_RPTR 0x0243 +#define mmSDMA5_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_OFFSET 0x0244 +#define mmSDMA5_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA5_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA5_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_SIZE 0x0247 +#define mmSDMA5_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA5_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA5_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC3_DOORBELL 0x024a +#define mmSDMA5_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC3_STATUS 0x0260 +#define mmSDMA5_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA5_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC3_WATERMARK 0x0262 +#define mmSDMA5_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA5_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA5_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA5_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA5_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC3_PREEMPT 0x0268 +#define mmSDMA5_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC3_DUMMY_REG 0x0269 +#define mmSDMA5_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA5_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA5_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA5_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA5_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA5_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA5_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA5_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA5_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA5_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA5_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA5_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA5_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_CNTL 0x0290 +#define mmSDMA5_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_BASE 0x0291 +#define mmSDMA5_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA5_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_RPTR 0x0293 +#define mmSDMA5_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA5_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_WPTR 0x0295 +#define mmSDMA5_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA5_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA5_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA5_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA5_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_CNTL 0x029a +#define mmSDMA5_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_RPTR 0x029b +#define mmSDMA5_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_OFFSET 0x029c +#define mmSDMA5_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_BASE_LO 0x029d +#define mmSDMA5_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_BASE_HI 0x029e +#define mmSDMA5_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_SIZE 0x029f +#define mmSDMA5_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA5_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA5_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC4_DOORBELL 0x02a2 +#define mmSDMA5_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC4_STATUS 0x02b8 +#define mmSDMA5_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA5_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC4_WATERMARK 0x02ba +#define mmSDMA5_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA5_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA5_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA5_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA5_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC4_PREEMPT 0x02c0 +#define mmSDMA5_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA5_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA5_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA5_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA5_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA5_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA5_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA5_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA5_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA5_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA5_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA5_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA5_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA5_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_CNTL 0x02e8 +#define mmSDMA5_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_BASE 0x02e9 +#define mmSDMA5_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA5_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_RPTR 0x02eb +#define mmSDMA5_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA5_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_WPTR 0x02ed +#define mmSDMA5_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA5_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA5_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA5_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA5_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_CNTL 0x02f2 +#define mmSDMA5_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_RPTR 0x02f3 +#define mmSDMA5_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA5_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA5_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA5_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_SIZE 0x02f7 +#define mmSDMA5_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA5_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA5_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC5_DOORBELL 0x02fa +#define mmSDMA5_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC5_STATUS 0x0310 +#define mmSDMA5_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA5_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC5_WATERMARK 0x0312 +#define mmSDMA5_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA5_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA5_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA5_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA5_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC5_PREEMPT 0x0318 +#define mmSDMA5_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC5_DUMMY_REG 0x0319 +#define mmSDMA5_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA5_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA5_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA5_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA5_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA5_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA5_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA5_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA5_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA5_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA5_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA5_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA5_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_CNTL 0x0340 +#define mmSDMA5_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_BASE 0x0341 +#define mmSDMA5_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA5_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_RPTR 0x0343 +#define mmSDMA5_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA5_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_WPTR 0x0345 +#define mmSDMA5_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA5_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA5_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA5_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA5_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_CNTL 0x034a +#define mmSDMA5_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_RPTR 0x034b +#define mmSDMA5_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_OFFSET 0x034c +#define mmSDMA5_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_BASE_LO 0x034d +#define mmSDMA5_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_BASE_HI 0x034e +#define mmSDMA5_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_SIZE 0x034f +#define mmSDMA5_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA5_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA5_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC6_DOORBELL 0x0352 +#define mmSDMA5_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC6_STATUS 0x0368 +#define mmSDMA5_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA5_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC6_WATERMARK 0x036a +#define mmSDMA5_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA5_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA5_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA5_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA5_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC6_PREEMPT 0x0370 +#define mmSDMA5_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC6_DUMMY_REG 0x0371 +#define mmSDMA5_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA5_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA5_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA5_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA5_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA5_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA5_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA5_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA5_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA5_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA5_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA5_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA5_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_CNTL 0x0398 +#define mmSDMA5_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_BASE 0x0399 +#define mmSDMA5_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_BASE_HI 0x039a +#define mmSDMA5_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_RPTR 0x039b +#define mmSDMA5_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA5_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_WPTR 0x039d +#define mmSDMA5_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA5_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA5_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA5_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA5_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_CNTL 0x03a2 +#define mmSDMA5_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_RPTR 0x03a3 +#define mmSDMA5_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA5_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA5_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA5_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_SIZE 0x03a7 +#define mmSDMA5_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA5_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA5_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC7_DOORBELL 0x03aa +#define mmSDMA5_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC7_STATUS 0x03c0 +#define mmSDMA5_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA5_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC7_WATERMARK 0x03c2 +#define mmSDMA5_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA5_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA5_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA5_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA5_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC7_PREEMPT 0x03c8 +#define mmSDMA5_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA5_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA5_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA5_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA5_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA5_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA5_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA5_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA5_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA5_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA5_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA5_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA5_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA5_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h new file mode 100644 index 0000000..e99856b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma5_4_2_2_SH_MASK_HEADER +#define _sdma5_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma5_sdma5dec +//SDMA5_UCODE_ADDR +#define SDMA5_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA5_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA5_UCODE_DATA +#define SDMA5_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA5_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA5_VM_CNTL +#define SDMA5_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA5_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA5_VM_CTX_LO +#define SDMA5_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA5_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_VM_CTX_HI +#define SDMA5_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA5_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_ACTIVE_FCN_ID +#define SDMA5_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA5_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA5_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA5_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA5_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA5_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA5_VM_CTX_CNTL +#define SDMA5_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA5_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA5_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA5_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA5_VIRT_RESET_REQ +#define SDMA5_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA5_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA5_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA5_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA5_VF_ENABLE +#define SDMA5_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA5_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA5_CONTEXT_REG_TYPE0 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE__SHIFT 0x1 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_CNTL__SHIFT 0xa +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_RPTR__SHIFT 0xb +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_SIZE__SHIFT 0xf +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_DOORBELL__SHIFT 0x12 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_MASK 0x00000002L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_DOORBELL_MASK 0x00040000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA5_CONTEXT_REG_TYPE1 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_STATUS__SHIFT 0x8 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_WATERMARK__SHIFT 0xa +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA5_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_PREEMPT__SHIFT 0x10 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA5_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_STATUS_MASK 0x00000100L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_WATERMARK_MASK 0x00000400L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA5_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_PREEMPT_MASK 0x00010000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA5_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA5_CONTEXT_REG_TYPE2 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA5_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA5_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA5_CONTEXT_REG_TYPE3 +#define SDMA5_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA5_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA5_PUB_REG_TYPE0 +#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_ADDR__SHIFT 0x0 +#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_DATA__SHIFT 0x1 +#define SDMA5_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CNTL__SHIFT 0x4 +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_LO__SHIFT 0x5 +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_HI__SHIFT 0x6 +#define SDMA5_PUB_REG_TYPE0__SDMA5_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA5_PUB_REG_TYPE0__SDMA5_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA5_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA5_PUB_REG_TYPE0__SDMA5_MMHUB_CNTL__SHIFT 0x13 +#define SDMA5_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA5_PUB_REG_TYPE0__SDMA5_POWER_CNTL__SHIFT 0x1a +#define SDMA5_PUB_REG_TYPE0__SDMA5_CLK_CTRL__SHIFT 0x1b +#define SDMA5_PUB_REG_TYPE0__SDMA5_CNTL__SHIFT 0x1c +#define SDMA5_PUB_REG_TYPE0__SDMA5_CHICKEN_BITS__SHIFT 0x1d +#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_ADDR_MASK 0x00000001L +#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_DATA_MASK 0x00000002L +#define SDMA5_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CNTL_MASK 0x00000010L +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_LO_MASK 0x00000020L +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_HI_MASK 0x00000040L +#define SDMA5_PUB_REG_TYPE0__SDMA5_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA5_PUB_REG_TYPE0__SDMA5_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA5_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_MMHUB_CNTL_MASK 0x00080000L +#define SDMA5_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_POWER_CNTL_MASK 0x04000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CLK_CTRL_MASK 0x08000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CNTL_MASK 0x10000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CHICKEN_BITS_MASK 0x20000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA5_PUB_REG_TYPE1 +#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA5_PUB_REG_TYPE1__SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA5_PUB_REG_TYPE1__SDMA5_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA5_PUB_REG_TYPE1__SDMA5_PROGRAM__SHIFT 0x4 +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS_REG__SHIFT 0x5 +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS1_REG__SHIFT 0x6 +#define SDMA5_PUB_REG_TYPE1__SDMA5_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA5_PUB_REG_TYPE1__SDMA5_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA5_PUB_REG_TYPE1__SDMA5_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA5_PUB_REG_TYPE1__SDMA5_F32_CNTL__SHIFT 0xa +#define SDMA5_PUB_REG_TYPE1__SDMA5_FREEZE__SHIFT 0xb +#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA5_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_CONFIG__SHIFT 0x12 +#define SDMA5_PUB_REG_TYPE1__SDMA5_BA_THRESHOLD__SHIFT 0x13 +#define SDMA5_PUB_REG_TYPE1__SDMA5_ID__SHIFT 0x14 +#define SDMA5_PUB_REG_TYPE1__SDMA5_VERSION__SHIFT 0x15 +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER__SHIFT 0x16 +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS2_REG__SHIFT 0x18 +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_CNTL__SHIFT 0x1c +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA5_PUB_REG_TYPE1__SDMA5_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA5_PUB_REG_TYPE1__SDMA5_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA5_PUB_REG_TYPE1__SDMA5_PROGRAM_MASK 0x00000010L +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS_REG_MASK 0x00000020L +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS1_REG_MASK 0x00000040L +#define SDMA5_PUB_REG_TYPE1__SDMA5_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA5_PUB_REG_TYPE1__SDMA5_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA5_PUB_REG_TYPE1__SDMA5_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA5_PUB_REG_TYPE1__SDMA5_F32_CNTL_MASK 0x00000400L +#define SDMA5_PUB_REG_TYPE1__SDMA5_FREEZE_MASK 0x00000800L +#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA5_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_CONFIG_MASK 0x00040000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_BA_THRESHOLD_MASK 0x00080000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_ID_MASK 0x00100000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_VERSION_MASK 0x00200000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_MASK 0x00400000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS2_REG_MASK 0x01000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_CNTL_MASK 0x10000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA5_PUB_REG_TYPE2 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV0__SHIFT 0x0 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV1__SHIFT 0x1 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV2__SHIFT 0x2 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_PAGE__SHIFT 0x8 +#define SDMA5_PUB_REG_TYPE2__SDMA5_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA5_PUB_REG_TYPE2__SDMA5_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA5_PUB_REG_TYPE2__SDMA5_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA5_PUB_REG_TYPE2__SDMA5_STATUS3_REG__SHIFT 0xc +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA5_PUB_REG_TYPE2__SDMA5_ERROR_LOG__SHIFT 0x10 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA5_PUB_REG_TYPE2__SDMA5_F32_COUNTER__SHIFT 0x15 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UNBREAKABLE__SHIFT 0x16 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFMON_CNTL__SHIFT 0x17 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA5_PUB_REG_TYPE2__SDMA5_CRD_CNTL__SHIFT 0x1b +#define SDMA5_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA5_PUB_REG_TYPE2__SDMA5_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA5_PUB_REG_TYPE2__SDMA5_ULV_CNTL__SHIFT 0x1e +#define SDMA5_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV0_MASK 0x00000001L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV1_MASK 0x00000002L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV2_MASK 0x00000004L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_PAGE_MASK 0x00000100L +#define SDMA5_PUB_REG_TYPE2__SDMA5_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA5_PUB_REG_TYPE2__SDMA5_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA5_PUB_REG_TYPE2__SDMA5_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA5_PUB_REG_TYPE2__SDMA5_STATUS3_REG_MASK 0x00001000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_ERROR_LOG_MASK 0x00010000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_F32_COUNTER_MASK 0x00200000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UNBREAKABLE_MASK 0x00400000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFMON_CNTL_MASK 0x00800000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_CRD_CNTL_MASK 0x08000000L +#define SDMA5_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_ULV_CNTL_MASK 0x40000000L +#define SDMA5_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA5_PUB_REG_TYPE3 +#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA5_PUB_REG_TYPE3__SDMA5_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA5_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA5_PUB_REG_TYPE3__SDMA5_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA5_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA5_MMHUB_CNTL +#define SDMA5_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA5_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA5_CONTEXT_GROUP_BOUNDARY +#define SDMA5_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA5_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA5_POWER_CNTL +#define SDMA5_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA5_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA5_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA5_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA5_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA5_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA5_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA5_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA5_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA5_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA5_CLK_CTRL +#define SDMA5_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA5_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA5_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA5_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA5_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA5_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA5_CNTL +#define SDMA5_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA5_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA5_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA5_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA5_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA5_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA5_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA5_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA5_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA5_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA5_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA5_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA5_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA5_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA5_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA5_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA5_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA5_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA5_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA5_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA5_CHICKEN_BITS +#define SDMA5_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA5_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA5_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA5_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA5_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA5_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA5_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA5_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA5_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA5_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA5_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA5_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA5_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA5_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA5_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA5_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA5_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA5_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA5_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA5_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA5_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA5_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA5_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA5_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA5_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA5_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA5_GB_ADDR_CONFIG +#define SDMA5_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA5_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA5_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA5_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA5_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA5_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA5_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA5_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA5_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA5_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA5_GB_ADDR_CONFIG_READ +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA5_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA5_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA5_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA5_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA5_RB_RPTR_FETCH_HI +#define SDMA5_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA5_RB_RPTR_FETCH +#define SDMA5_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA5_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA5_IB_OFFSET_FETCH +#define SDMA5_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA5_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA5_PROGRAM +#define SDMA5_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA5_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA5_STATUS_REG +#define SDMA5_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA5_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA5_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA5_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA5_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA5_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA5_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA5_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA5_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA5_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA5_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA5_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA5_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA5_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA5_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA5_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA5_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA5_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA5_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA5_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA5_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA5_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA5_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA5_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA5_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA5_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA5_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA5_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA5_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA5_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA5_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA5_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA5_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA5_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA5_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA5_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA5_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA5_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA5_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA5_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA5_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA5_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA5_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA5_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA5_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA5_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA5_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA5_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA5_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA5_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA5_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA5_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA5_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA5_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA5_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA5_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA5_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA5_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA5_STATUS1_REG +#define SDMA5_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA5_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA5_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA5_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA5_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA5_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA5_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA5_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA5_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA5_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA5_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA5_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA5_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA5_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA5_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA5_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA5_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA5_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA5_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA5_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA5_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA5_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA5_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA5_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA5_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA5_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA5_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA5_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA5_RD_BURST_CNTL +#define SDMA5_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA5_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA5_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA5_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA5_HBM_PAGE_CONFIG +#define SDMA5_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA5_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA5_UCODE_CHECKSUM +#define SDMA5_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA5_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA5_F32_CNTL +#define SDMA5_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA5_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA5_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA5_F32_CNTL__STEP_MASK 0x00000002L +//SDMA5_FREEZE +#define SDMA5_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA5_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA5_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA5_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA5_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA5_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA5_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA5_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA5_PHASE0_QUANTUM +#define SDMA5_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA5_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA5_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA5_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA5_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA5_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA5_PHASE1_QUANTUM +#define SDMA5_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA5_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA5_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA5_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA5_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA5_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA5_EDC_CONFIG +#define SDMA5_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA5_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA5_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA5_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA5_BA_THRESHOLD +#define SDMA5_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA5_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA5_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA5_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA5_ID +#define SDMA5_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA5_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA5_VERSION +#define SDMA5_VERSION__MINVER__SHIFT 0x0 +#define SDMA5_VERSION__MAJVER__SHIFT 0x8 +#define SDMA5_VERSION__REV__SHIFT 0x10 +#define SDMA5_VERSION__MINVER_MASK 0x0000007FL +#define SDMA5_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA5_VERSION__REV_MASK 0x003F0000L +//SDMA5_EDC_COUNTER +#define SDMA5_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA5_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA5_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA5_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA5_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA5_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA5_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA5_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA5_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA5_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA5_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA5_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA5_EDC_COUNTER_CLEAR +#define SDMA5_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA5_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA5_STATUS2_REG +#define SDMA5_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA5_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA5_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA5_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA5_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA5_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA5_ATOMIC_CNTL +#define SDMA5_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA5_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA5_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA5_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA5_ATOMIC_PREOP_LO +#define SDMA5_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA5_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA5_ATOMIC_PREOP_HI +#define SDMA5_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA5_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA5_UTCL1_CNTL +#define SDMA5_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA5_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA5_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA5_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA5_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA5_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA5_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA5_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA5_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA5_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA5_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA5_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA5_UTCL1_WATERMK +#define SDMA5_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA5_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA5_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA5_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA5_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA5_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA5_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA5_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA5_UTCL1_RD_STATUS +#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA5_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA5_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA5_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA5_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA5_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA5_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA5_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA5_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA5_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA5_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA5_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA5_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA5_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA5_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA5_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA5_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA5_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA5_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA5_UTCL1_WR_STATUS +#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA5_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA5_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA5_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA5_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA5_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA5_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA5_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA5_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA5_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA5_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA5_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA5_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA5_UTCL1_INV0 +#define SDMA5_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA5_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA5_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA5_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA5_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA5_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA5_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA5_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA5_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA5_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA5_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA5_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA5_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA5_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA5_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA5_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA5_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA5_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA5_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA5_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA5_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA5_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA5_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA5_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA5_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA5_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA5_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA5_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA5_UTCL1_INV1 +#define SDMA5_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA5_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA5_UTCL1_INV2 +#define SDMA5_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA5_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA5_UTCL1_RD_XNACK0 +#define SDMA5_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA5_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA5_UTCL1_RD_XNACK1 +#define SDMA5_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA5_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA5_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA5_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA5_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA5_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA5_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA5_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA5_UTCL1_WR_XNACK0 +#define SDMA5_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA5_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA5_UTCL1_WR_XNACK1 +#define SDMA5_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA5_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA5_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA5_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA5_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA5_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA5_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA5_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA5_UTCL1_TIMEOUT +#define SDMA5_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA5_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA5_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA5_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA5_UTCL1_PAGE +#define SDMA5_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA5_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA5_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA5_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA5_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA5_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA5_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA5_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA5_POWER_CNTL_IDLE +#define SDMA5_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA5_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA5_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA5_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA5_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA5_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA5_RELAX_ORDERING_LUT +#define SDMA5_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA5_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA5_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA5_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA5_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA5_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA5_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA5_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA5_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA5_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA5_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA5_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA5_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA5_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA5_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA5_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA5_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA5_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA5_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA5_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA5_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA5_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA5_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA5_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA5_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA5_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA5_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA5_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA5_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA5_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA5_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA5_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA5_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA5_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA5_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA5_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA5_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA5_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA5_CHICKEN_BITS_2 +#define SDMA5_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA5_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA5_STATUS3_REG +#define SDMA5_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA5_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA5_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA5_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA5_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA5_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA5_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA5_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA5_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA5_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA5_PHYSICAL_ADDR_LO +#define SDMA5_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA5_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA5_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA5_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA5_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA5_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA5_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA5_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA5_PHYSICAL_ADDR_HI +#define SDMA5_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA5_PHASE2_QUANTUM +#define SDMA5_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA5_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA5_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA5_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA5_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA5_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA5_ERROR_LOG +#define SDMA5_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA5_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA5_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA5_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA5_PUB_DUMMY_REG0 +#define SDMA5_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA5_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA5_PUB_DUMMY_REG1 +#define SDMA5_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA5_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA5_PUB_DUMMY_REG2 +#define SDMA5_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA5_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA5_PUB_DUMMY_REG3 +#define SDMA5_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA5_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA5_F32_COUNTER +#define SDMA5_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA5_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA5_UNBREAKABLE +#define SDMA5_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA5_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA5_PERFMON_CNTL +#define SDMA5_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA5_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA5_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA5_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA5_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA5_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA5_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA5_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA5_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA5_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA5_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA5_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA5_PERFCOUNTER0_RESULT +#define SDMA5_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA5_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA5_PERFCOUNTER1_RESULT +#define SDMA5_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA5_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA5_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA5_CRD_CNTL +#define SDMA5_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA5_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA5_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA5_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA5_GPU_IOV_VIOLATION_LOG +#define SDMA5_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA5_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA5_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA5_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA5_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA5_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA5_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA5_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA5_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA5_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA5_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA5_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA5_ULV_CNTL +#define SDMA5_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA5_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA5_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA5_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA5_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA5_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA5_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA5_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA5_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA5_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA5_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA5_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA5_EA_DBIT_ADDR_DATA +#define SDMA5_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA5_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA5_EA_DBIT_ADDR_INDEX +#define SDMA5_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA5_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA5_GPU_IOV_VIOLATION_LOG2 +#define SDMA5_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA5_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA5_GFX_RB_CNTL +#define SDMA5_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_GFX_RB_BASE +#define SDMA5_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_BASE_HI +#define SDMA5_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_GFX_RB_RPTR +#define SDMA5_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_RPTR_HI +#define SDMA5_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_WPTR +#define SDMA5_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_WPTR_HI +#define SDMA5_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_WPTR_POLL_CNTL +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_GFX_RB_RPTR_ADDR_HI +#define SDMA5_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_RPTR_ADDR_LO +#define SDMA5_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_GFX_IB_CNTL +#define SDMA5_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_GFX_IB_RPTR +#define SDMA5_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_GFX_IB_OFFSET +#define SDMA5_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_GFX_IB_BASE_LO +#define SDMA5_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_GFX_IB_BASE_HI +#define SDMA5_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_GFX_IB_SIZE +#define SDMA5_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_GFX_SKIP_CNTL +#define SDMA5_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_GFX_CONTEXT_STATUS +#define SDMA5_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_GFX_DOORBELL +#define SDMA5_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_GFX_CONTEXT_CNTL +#define SDMA5_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA5_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA5_GFX_STATUS +#define SDMA5_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_GFX_DOORBELL_LOG +#define SDMA5_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_GFX_WATERMARK +#define SDMA5_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_GFX_DOORBELL_OFFSET +#define SDMA5_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_GFX_CSA_ADDR_LO +#define SDMA5_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_GFX_CSA_ADDR_HI +#define SDMA5_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_GFX_IB_SUB_REMAIN +#define SDMA5_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_GFX_PREEMPT +#define SDMA5_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_GFX_DUMMY_REG +#define SDMA5_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_GFX_RB_AQL_CNTL +#define SDMA5_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_GFX_MINOR_PTR_UPDATE +#define SDMA5_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_GFX_MIDCMD_DATA0 +#define SDMA5_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA1 +#define SDMA5_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA2 +#define SDMA5_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA3 +#define SDMA5_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA4 +#define SDMA5_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA5 +#define SDMA5_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA6 +#define SDMA5_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA7 +#define SDMA5_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA8 +#define SDMA5_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_CNTL +#define SDMA5_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_PAGE_RB_CNTL +#define SDMA5_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_PAGE_RB_BASE +#define SDMA5_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_BASE_HI +#define SDMA5_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_PAGE_RB_RPTR +#define SDMA5_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_RPTR_HI +#define SDMA5_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_WPTR +#define SDMA5_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_WPTR_HI +#define SDMA5_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_WPTR_POLL_CNTL +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_PAGE_RB_RPTR_ADDR_HI +#define SDMA5_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_RPTR_ADDR_LO +#define SDMA5_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_PAGE_IB_CNTL +#define SDMA5_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_PAGE_IB_RPTR +#define SDMA5_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_PAGE_IB_OFFSET +#define SDMA5_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_PAGE_IB_BASE_LO +#define SDMA5_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_PAGE_IB_BASE_HI +#define SDMA5_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_PAGE_IB_SIZE +#define SDMA5_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_PAGE_SKIP_CNTL +#define SDMA5_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_PAGE_CONTEXT_STATUS +#define SDMA5_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_PAGE_DOORBELL +#define SDMA5_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_PAGE_STATUS +#define SDMA5_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_PAGE_DOORBELL_LOG +#define SDMA5_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_PAGE_WATERMARK +#define SDMA5_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_PAGE_DOORBELL_OFFSET +#define SDMA5_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_PAGE_CSA_ADDR_LO +#define SDMA5_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_PAGE_CSA_ADDR_HI +#define SDMA5_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_PAGE_IB_SUB_REMAIN +#define SDMA5_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_PAGE_PREEMPT +#define SDMA5_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_PAGE_DUMMY_REG +#define SDMA5_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_PAGE_RB_AQL_CNTL +#define SDMA5_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_PAGE_MINOR_PTR_UPDATE +#define SDMA5_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_PAGE_MIDCMD_DATA0 +#define SDMA5_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA1 +#define SDMA5_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA2 +#define SDMA5_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA3 +#define SDMA5_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA4 +#define SDMA5_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA5 +#define SDMA5_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA6 +#define SDMA5_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA7 +#define SDMA5_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA8 +#define SDMA5_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_CNTL +#define SDMA5_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC0_RB_CNTL +#define SDMA5_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC0_RB_BASE +#define SDMA5_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_BASE_HI +#define SDMA5_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC0_RB_RPTR +#define SDMA5_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_RPTR_HI +#define SDMA5_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_WPTR +#define SDMA5_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_WPTR_HI +#define SDMA5_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_WPTR_POLL_CNTL +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC0_RB_RPTR_ADDR_HI +#define SDMA5_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_RPTR_ADDR_LO +#define SDMA5_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC0_IB_CNTL +#define SDMA5_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC0_IB_RPTR +#define SDMA5_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC0_IB_OFFSET +#define SDMA5_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC0_IB_BASE_LO +#define SDMA5_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC0_IB_BASE_HI +#define SDMA5_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC0_IB_SIZE +#define SDMA5_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC0_SKIP_CNTL +#define SDMA5_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC0_CONTEXT_STATUS +#define SDMA5_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC0_DOORBELL +#define SDMA5_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC0_STATUS +#define SDMA5_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC0_DOORBELL_LOG +#define SDMA5_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC0_WATERMARK +#define SDMA5_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC0_DOORBELL_OFFSET +#define SDMA5_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC0_CSA_ADDR_LO +#define SDMA5_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC0_CSA_ADDR_HI +#define SDMA5_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC0_IB_SUB_REMAIN +#define SDMA5_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC0_PREEMPT +#define SDMA5_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC0_DUMMY_REG +#define SDMA5_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC0_RB_AQL_CNTL +#define SDMA5_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC0_MINOR_PTR_UPDATE +#define SDMA5_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC0_MIDCMD_DATA0 +#define SDMA5_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA1 +#define SDMA5_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA2 +#define SDMA5_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA3 +#define SDMA5_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA4 +#define SDMA5_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA5 +#define SDMA5_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA6 +#define SDMA5_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA7 +#define SDMA5_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA8 +#define SDMA5_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_CNTL +#define SDMA5_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC1_RB_CNTL +#define SDMA5_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC1_RB_BASE +#define SDMA5_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_BASE_HI +#define SDMA5_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC1_RB_RPTR +#define SDMA5_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_RPTR_HI +#define SDMA5_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_WPTR +#define SDMA5_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_WPTR_HI +#define SDMA5_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_WPTR_POLL_CNTL +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC1_RB_RPTR_ADDR_HI +#define SDMA5_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_RPTR_ADDR_LO +#define SDMA5_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC1_IB_CNTL +#define SDMA5_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC1_IB_RPTR +#define SDMA5_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC1_IB_OFFSET +#define SDMA5_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC1_IB_BASE_LO +#define SDMA5_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC1_IB_BASE_HI +#define SDMA5_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC1_IB_SIZE +#define SDMA5_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC1_SKIP_CNTL +#define SDMA5_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC1_CONTEXT_STATUS +#define SDMA5_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC1_DOORBELL +#define SDMA5_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC1_STATUS +#define SDMA5_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC1_DOORBELL_LOG +#define SDMA5_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC1_WATERMARK +#define SDMA5_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC1_DOORBELL_OFFSET +#define SDMA5_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC1_CSA_ADDR_LO +#define SDMA5_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC1_CSA_ADDR_HI +#define SDMA5_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC1_IB_SUB_REMAIN +#define SDMA5_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC1_PREEMPT +#define SDMA5_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC1_DUMMY_REG +#define SDMA5_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC1_RB_AQL_CNTL +#define SDMA5_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC1_MINOR_PTR_UPDATE +#define SDMA5_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC1_MIDCMD_DATA0 +#define SDMA5_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA1 +#define SDMA5_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA2 +#define SDMA5_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA3 +#define SDMA5_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA4 +#define SDMA5_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA5 +#define SDMA5_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA6 +#define SDMA5_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA7 +#define SDMA5_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA8 +#define SDMA5_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_CNTL +#define SDMA5_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC2_RB_CNTL +#define SDMA5_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC2_RB_BASE +#define SDMA5_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_BASE_HI +#define SDMA5_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC2_RB_RPTR +#define SDMA5_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_RPTR_HI +#define SDMA5_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_WPTR +#define SDMA5_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_WPTR_HI +#define SDMA5_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_WPTR_POLL_CNTL +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC2_RB_RPTR_ADDR_HI +#define SDMA5_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_RPTR_ADDR_LO +#define SDMA5_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC2_IB_CNTL +#define SDMA5_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC2_IB_RPTR +#define SDMA5_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC2_IB_OFFSET +#define SDMA5_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC2_IB_BASE_LO +#define SDMA5_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC2_IB_BASE_HI +#define SDMA5_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC2_IB_SIZE +#define SDMA5_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC2_SKIP_CNTL +#define SDMA5_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC2_CONTEXT_STATUS +#define SDMA5_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC2_DOORBELL +#define SDMA5_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC2_STATUS +#define SDMA5_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC2_DOORBELL_LOG +#define SDMA5_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC2_WATERMARK +#define SDMA5_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC2_DOORBELL_OFFSET +#define SDMA5_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC2_CSA_ADDR_LO +#define SDMA5_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC2_CSA_ADDR_HI +#define SDMA5_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC2_IB_SUB_REMAIN +#define SDMA5_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC2_PREEMPT +#define SDMA5_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC2_DUMMY_REG +#define SDMA5_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC2_RB_AQL_CNTL +#define SDMA5_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC2_MINOR_PTR_UPDATE +#define SDMA5_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC2_MIDCMD_DATA0 +#define SDMA5_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA1 +#define SDMA5_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA2 +#define SDMA5_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA3 +#define SDMA5_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA4 +#define SDMA5_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA5 +#define SDMA5_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA6 +#define SDMA5_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA7 +#define SDMA5_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA8 +#define SDMA5_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_CNTL +#define SDMA5_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC3_RB_CNTL +#define SDMA5_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC3_RB_BASE +#define SDMA5_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_BASE_HI +#define SDMA5_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC3_RB_RPTR +#define SDMA5_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_RPTR_HI +#define SDMA5_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_WPTR +#define SDMA5_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_WPTR_HI +#define SDMA5_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_WPTR_POLL_CNTL +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC3_RB_RPTR_ADDR_HI +#define SDMA5_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_RPTR_ADDR_LO +#define SDMA5_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC3_IB_CNTL +#define SDMA5_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC3_IB_RPTR +#define SDMA5_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC3_IB_OFFSET +#define SDMA5_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC3_IB_BASE_LO +#define SDMA5_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC3_IB_BASE_HI +#define SDMA5_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC3_IB_SIZE +#define SDMA5_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC3_SKIP_CNTL +#define SDMA5_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC3_CONTEXT_STATUS +#define SDMA5_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC3_DOORBELL +#define SDMA5_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC3_STATUS +#define SDMA5_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC3_DOORBELL_LOG +#define SDMA5_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC3_WATERMARK +#define SDMA5_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC3_DOORBELL_OFFSET +#define SDMA5_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC3_CSA_ADDR_LO +#define SDMA5_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC3_CSA_ADDR_HI +#define SDMA5_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC3_IB_SUB_REMAIN +#define SDMA5_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC3_PREEMPT +#define SDMA5_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC3_DUMMY_REG +#define SDMA5_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC3_RB_AQL_CNTL +#define SDMA5_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC3_MINOR_PTR_UPDATE +#define SDMA5_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC3_MIDCMD_DATA0 +#define SDMA5_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA1 +#define SDMA5_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA2 +#define SDMA5_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA3 +#define SDMA5_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA4 +#define SDMA5_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA5 +#define SDMA5_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA6 +#define SDMA5_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA7 +#define SDMA5_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA8 +#define SDMA5_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_CNTL +#define SDMA5_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC4_RB_CNTL +#define SDMA5_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC4_RB_BASE +#define SDMA5_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_BASE_HI +#define SDMA5_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC4_RB_RPTR +#define SDMA5_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_RPTR_HI +#define SDMA5_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_WPTR +#define SDMA5_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_WPTR_HI +#define SDMA5_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_WPTR_POLL_CNTL +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC4_RB_RPTR_ADDR_HI +#define SDMA5_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_RPTR_ADDR_LO +#define SDMA5_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC4_IB_CNTL +#define SDMA5_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC4_IB_RPTR +#define SDMA5_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC4_IB_OFFSET +#define SDMA5_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC4_IB_BASE_LO +#define SDMA5_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC4_IB_BASE_HI +#define SDMA5_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC4_IB_SIZE +#define SDMA5_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC4_SKIP_CNTL +#define SDMA5_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC4_CONTEXT_STATUS +#define SDMA5_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC4_DOORBELL +#define SDMA5_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC4_STATUS +#define SDMA5_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC4_DOORBELL_LOG +#define SDMA5_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC4_WATERMARK +#define SDMA5_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC4_DOORBELL_OFFSET +#define SDMA5_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC4_CSA_ADDR_LO +#define SDMA5_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC4_CSA_ADDR_HI +#define SDMA5_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC4_IB_SUB_REMAIN +#define SDMA5_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC4_PREEMPT +#define SDMA5_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC4_DUMMY_REG +#define SDMA5_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC4_RB_AQL_CNTL +#define SDMA5_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC4_MINOR_PTR_UPDATE +#define SDMA5_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC4_MIDCMD_DATA0 +#define SDMA5_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA1 +#define SDMA5_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA2 +#define SDMA5_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA3 +#define SDMA5_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA4 +#define SDMA5_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA5 +#define SDMA5_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA6 +#define SDMA5_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA7 +#define SDMA5_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA8 +#define SDMA5_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_CNTL +#define SDMA5_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC5_RB_CNTL +#define SDMA5_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC5_RB_BASE +#define SDMA5_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_BASE_HI +#define SDMA5_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC5_RB_RPTR +#define SDMA5_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_RPTR_HI +#define SDMA5_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_WPTR +#define SDMA5_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_WPTR_HI +#define SDMA5_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_WPTR_POLL_CNTL +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC5_RB_RPTR_ADDR_HI +#define SDMA5_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_RPTR_ADDR_LO +#define SDMA5_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC5_IB_CNTL +#define SDMA5_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC5_IB_RPTR +#define SDMA5_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC5_IB_OFFSET +#define SDMA5_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC5_IB_BASE_LO +#define SDMA5_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC5_IB_BASE_HI +#define SDMA5_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC5_IB_SIZE +#define SDMA5_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC5_SKIP_CNTL +#define SDMA5_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC5_CONTEXT_STATUS +#define SDMA5_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC5_DOORBELL +#define SDMA5_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC5_STATUS +#define SDMA5_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC5_DOORBELL_LOG +#define SDMA5_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC5_WATERMARK +#define SDMA5_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC5_DOORBELL_OFFSET +#define SDMA5_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC5_CSA_ADDR_LO +#define SDMA5_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC5_CSA_ADDR_HI +#define SDMA5_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC5_IB_SUB_REMAIN +#define SDMA5_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC5_PREEMPT +#define SDMA5_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC5_DUMMY_REG +#define SDMA5_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC5_RB_AQL_CNTL +#define SDMA5_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC5_MINOR_PTR_UPDATE +#define SDMA5_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC5_MIDCMD_DATA0 +#define SDMA5_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA1 +#define SDMA5_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA2 +#define SDMA5_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA3 +#define SDMA5_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA4 +#define SDMA5_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA5 +#define SDMA5_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA6 +#define SDMA5_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA7 +#define SDMA5_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA8 +#define SDMA5_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_CNTL +#define SDMA5_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC6_RB_CNTL +#define SDMA5_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC6_RB_BASE +#define SDMA5_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_BASE_HI +#define SDMA5_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC6_RB_RPTR +#define SDMA5_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_RPTR_HI +#define SDMA5_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_WPTR +#define SDMA5_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_WPTR_HI +#define SDMA5_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_WPTR_POLL_CNTL +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC6_RB_RPTR_ADDR_HI +#define SDMA5_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_RPTR_ADDR_LO +#define SDMA5_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC6_IB_CNTL +#define SDMA5_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC6_IB_RPTR +#define SDMA5_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC6_IB_OFFSET +#define SDMA5_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC6_IB_BASE_LO +#define SDMA5_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC6_IB_BASE_HI +#define SDMA5_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC6_IB_SIZE +#define SDMA5_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC6_SKIP_CNTL +#define SDMA5_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC6_CONTEXT_STATUS +#define SDMA5_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC6_DOORBELL +#define SDMA5_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC6_STATUS +#define SDMA5_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC6_DOORBELL_LOG +#define SDMA5_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC6_WATERMARK +#define SDMA5_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC6_DOORBELL_OFFSET +#define SDMA5_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC6_CSA_ADDR_LO +#define SDMA5_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC6_CSA_ADDR_HI +#define SDMA5_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC6_IB_SUB_REMAIN +#define SDMA5_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC6_PREEMPT +#define SDMA5_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC6_DUMMY_REG +#define SDMA5_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC6_RB_AQL_CNTL +#define SDMA5_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC6_MINOR_PTR_UPDATE +#define SDMA5_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC6_MIDCMD_DATA0 +#define SDMA5_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA1 +#define SDMA5_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA2 +#define SDMA5_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA3 +#define SDMA5_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA4 +#define SDMA5_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA5 +#define SDMA5_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA6 +#define SDMA5_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA7 +#define SDMA5_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA8 +#define SDMA5_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_CNTL +#define SDMA5_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC7_RB_CNTL +#define SDMA5_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC7_RB_BASE +#define SDMA5_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_BASE_HI +#define SDMA5_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC7_RB_RPTR +#define SDMA5_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_RPTR_HI +#define SDMA5_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_WPTR +#define SDMA5_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_WPTR_HI +#define SDMA5_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_WPTR_POLL_CNTL +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC7_RB_RPTR_ADDR_HI +#define SDMA5_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_RPTR_ADDR_LO +#define SDMA5_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC7_IB_CNTL +#define SDMA5_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC7_IB_RPTR +#define SDMA5_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC7_IB_OFFSET +#define SDMA5_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC7_IB_BASE_LO +#define SDMA5_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC7_IB_BASE_HI +#define SDMA5_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC7_IB_SIZE +#define SDMA5_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC7_SKIP_CNTL +#define SDMA5_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC7_CONTEXT_STATUS +#define SDMA5_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC7_DOORBELL +#define SDMA5_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC7_STATUS +#define SDMA5_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC7_DOORBELL_LOG +#define SDMA5_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC7_WATERMARK +#define SDMA5_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC7_DOORBELL_OFFSET +#define SDMA5_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC7_CSA_ADDR_LO +#define SDMA5_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC7_CSA_ADDR_HI +#define SDMA5_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC7_IB_SUB_REMAIN +#define SDMA5_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC7_PREEMPT +#define SDMA5_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC7_DUMMY_REG +#define SDMA5_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC7_RB_AQL_CNTL +#define SDMA5_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC7_MINOR_PTR_UPDATE +#define SDMA5_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC7_MIDCMD_DATA0 +#define SDMA5_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA1 +#define SDMA5_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA2 +#define SDMA5_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA3 +#define SDMA5_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA4 +#define SDMA5_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA5 +#define SDMA5_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA6 +#define SDMA5_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA7 +#define SDMA5_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA8 +#define SDMA5_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_CNTL +#define SDMA5_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h new file mode 100644 index 0000000..ae12db2 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma6_4_2_2_OFFSET_HEADER +#define _sdma6_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma6_sdma6dec +// base address: 0x7c000 +#define mmSDMA6_UCODE_ADDR 0x0000 +#define mmSDMA6_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA6_UCODE_DATA 0x0001 +#define mmSDMA6_UCODE_DATA_BASE_IDX 1 +#define mmSDMA6_VM_CNTL 0x0004 +#define mmSDMA6_VM_CNTL_BASE_IDX 1 +#define mmSDMA6_VM_CTX_LO 0x0005 +#define mmSDMA6_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA6_VM_CTX_HI 0x0006 +#define mmSDMA6_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA6_ACTIVE_FCN_ID 0x0007 +#define mmSDMA6_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA6_VM_CTX_CNTL 0x0008 +#define mmSDMA6_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA6_VIRT_RESET_REQ 0x0009 +#define mmSDMA6_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA6_VF_ENABLE 0x000a +#define mmSDMA6_VF_ENABLE_BASE_IDX 1 +#define mmSDMA6_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA6_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA6_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA6_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA6_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA6_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA6_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA6_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA6_PUB_REG_TYPE0 0x000f +#define mmSDMA6_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA6_PUB_REG_TYPE1 0x0010 +#define mmSDMA6_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA6_PUB_REG_TYPE2 0x0011 +#define mmSDMA6_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA6_PUB_REG_TYPE3 0x0012 +#define mmSDMA6_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA6_MMHUB_CNTL 0x0013 +#define mmSDMA6_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA6_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA6_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA6_POWER_CNTL 0x001a +#define mmSDMA6_POWER_CNTL_BASE_IDX 1 +#define mmSDMA6_CLK_CTRL 0x001b +#define mmSDMA6_CLK_CTRL_BASE_IDX 1 +#define mmSDMA6_CNTL 0x001c +#define mmSDMA6_CNTL_BASE_IDX 1 +#define mmSDMA6_CHICKEN_BITS 0x001d +#define mmSDMA6_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA6_GB_ADDR_CONFIG 0x001e +#define mmSDMA6_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA6_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA6_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA6_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA6_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA6_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA6_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA6_RB_RPTR_FETCH 0x0022 +#define mmSDMA6_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA6_IB_OFFSET_FETCH 0x0023 +#define mmSDMA6_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA6_PROGRAM 0x0024 +#define mmSDMA6_PROGRAM_BASE_IDX 1 +#define mmSDMA6_STATUS_REG 0x0025 +#define mmSDMA6_STATUS_REG_BASE_IDX 1 +#define mmSDMA6_STATUS1_REG 0x0026 +#define mmSDMA6_STATUS1_REG_BASE_IDX 1 +#define mmSDMA6_RD_BURST_CNTL 0x0027 +#define mmSDMA6_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA6_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA6_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA6_UCODE_CHECKSUM 0x0029 +#define mmSDMA6_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA6_F32_CNTL 0x002a +#define mmSDMA6_F32_CNTL_BASE_IDX 1 +#define mmSDMA6_FREEZE 0x002b +#define mmSDMA6_FREEZE_BASE_IDX 1 +#define mmSDMA6_PHASE0_QUANTUM 0x002c +#define mmSDMA6_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA6_PHASE1_QUANTUM 0x002d +#define mmSDMA6_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA6_EDC_CONFIG 0x0032 +#define mmSDMA6_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA6_BA_THRESHOLD 0x0033 +#define mmSDMA6_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA6_ID 0x0034 +#define mmSDMA6_ID_BASE_IDX 1 +#define mmSDMA6_VERSION 0x0035 +#define mmSDMA6_VERSION_BASE_IDX 1 +#define mmSDMA6_EDC_COUNTER 0x0036 +#define mmSDMA6_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA6_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA6_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA6_STATUS2_REG 0x0038 +#define mmSDMA6_STATUS2_REG_BASE_IDX 1 +#define mmSDMA6_ATOMIC_CNTL 0x0039 +#define mmSDMA6_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA6_ATOMIC_PREOP_LO 0x003a +#define mmSDMA6_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA6_ATOMIC_PREOP_HI 0x003b +#define mmSDMA6_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA6_UTCL1_CNTL 0x003c +#define mmSDMA6_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA6_UTCL1_WATERMK 0x003d +#define mmSDMA6_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA6_UTCL1_RD_STATUS 0x003e +#define mmSDMA6_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA6_UTCL1_WR_STATUS 0x003f +#define mmSDMA6_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA6_UTCL1_INV0 0x0040 +#define mmSDMA6_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA6_UTCL1_INV1 0x0041 +#define mmSDMA6_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA6_UTCL1_INV2 0x0042 +#define mmSDMA6_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA6_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA6_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA6_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA6_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA6_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA6_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA6_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA6_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA6_UTCL1_TIMEOUT 0x0047 +#define mmSDMA6_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA6_UTCL1_PAGE 0x0048 +#define mmSDMA6_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA6_POWER_CNTL_IDLE 0x0049 +#define mmSDMA6_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA6_RELAX_ORDERING_LUT 0x004a +#define mmSDMA6_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA6_CHICKEN_BITS_2 0x004b +#define mmSDMA6_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA6_STATUS3_REG 0x004c +#define mmSDMA6_STATUS3_REG_BASE_IDX 1 +#define mmSDMA6_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA6_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA6_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_PHASE2_QUANTUM 0x004f +#define mmSDMA6_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA6_ERROR_LOG 0x0050 +#define mmSDMA6_ERROR_LOG_BASE_IDX 1 +#define mmSDMA6_PUB_DUMMY_REG0 0x0051 +#define mmSDMA6_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA6_PUB_DUMMY_REG1 0x0052 +#define mmSDMA6_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA6_PUB_DUMMY_REG2 0x0053 +#define mmSDMA6_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA6_PUB_DUMMY_REG3 0x0054 +#define mmSDMA6_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA6_F32_COUNTER 0x0055 +#define mmSDMA6_F32_COUNTER_BASE_IDX 1 +#define mmSDMA6_UNBREAKABLE 0x0056 +#define mmSDMA6_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA6_PERFMON_CNTL 0x0057 +#define mmSDMA6_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA6_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA6_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA6_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA6_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA6_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA6_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA6_CRD_CNTL 0x005b +#define mmSDMA6_CRD_CNTL_BASE_IDX 1 +#define mmSDMA6_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA6_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA6_ULV_CNTL 0x005e +#define mmSDMA6_ULV_CNTL_BASE_IDX 1 +#define mmSDMA6_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA6_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA6_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA6_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA6_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA6_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA6_GFX_RB_CNTL 0x0080 +#define mmSDMA6_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_RB_BASE 0x0081 +#define mmSDMA6_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA6_GFX_RB_BASE_HI 0x0082 +#define mmSDMA6_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_GFX_RB_RPTR 0x0083 +#define mmSDMA6_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA6_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_GFX_RB_WPTR 0x0085 +#define mmSDMA6_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA6_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA6_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA6_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA6_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_GFX_IB_CNTL 0x008a +#define mmSDMA6_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_IB_RPTR 0x008b +#define mmSDMA6_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_GFX_IB_OFFSET 0x008c +#define mmSDMA6_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_GFX_IB_BASE_LO 0x008d +#define mmSDMA6_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_GFX_IB_BASE_HI 0x008e +#define mmSDMA6_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_GFX_IB_SIZE 0x008f +#define mmSDMA6_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_GFX_SKIP_CNTL 0x0090 +#define mmSDMA6_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA6_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_GFX_DOORBELL 0x0092 +#define mmSDMA6_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA6_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA6_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_STATUS 0x00a8 +#define mmSDMA6_GFX_STATUS_BASE_IDX 1 +#define mmSDMA6_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA6_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_GFX_WATERMARK 0x00aa +#define mmSDMA6_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA6_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA6_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA6_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA6_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA6_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_GFX_PREEMPT 0x00b0 +#define mmSDMA6_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA6_GFX_DUMMY_REG 0x00b1 +#define mmSDMA6_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA6_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA6_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA6_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA6_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA6_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA6_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA6_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA6_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA6_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA6_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA6_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA6_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_CNTL 0x00d8 +#define mmSDMA6_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_BASE 0x00d9 +#define mmSDMA6_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_BASE_HI 0x00da +#define mmSDMA6_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_RPTR 0x00db +#define mmSDMA6_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA6_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_WPTR 0x00dd +#define mmSDMA6_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA6_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA6_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA6_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA6_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_CNTL 0x00e2 +#define mmSDMA6_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_RPTR 0x00e3 +#define mmSDMA6_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA6_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA6_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA6_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_SIZE 0x00e7 +#define mmSDMA6_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA6_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA6_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_PAGE_DOORBELL 0x00ea +#define mmSDMA6_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA6_PAGE_STATUS 0x0100 +#define mmSDMA6_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA6_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA6_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_PAGE_WATERMARK 0x0102 +#define mmSDMA6_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA6_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA6_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA6_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA6_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA6_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_PAGE_PREEMPT 0x0108 +#define mmSDMA6_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA6_PAGE_DUMMY_REG 0x0109 +#define mmSDMA6_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA6_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA6_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA6_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA6_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA6_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA6_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA6_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA6_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA6_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA6_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA6_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA6_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_CNTL 0x0130 +#define mmSDMA6_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_BASE 0x0131 +#define mmSDMA6_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA6_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_RPTR 0x0133 +#define mmSDMA6_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA6_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_WPTR 0x0135 +#define mmSDMA6_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA6_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA6_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA6_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA6_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_CNTL 0x013a +#define mmSDMA6_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_RPTR 0x013b +#define mmSDMA6_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_OFFSET 0x013c +#define mmSDMA6_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_BASE_LO 0x013d +#define mmSDMA6_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_BASE_HI 0x013e +#define mmSDMA6_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_SIZE 0x013f +#define mmSDMA6_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA6_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA6_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC0_DOORBELL 0x0142 +#define mmSDMA6_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC0_STATUS 0x0158 +#define mmSDMA6_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA6_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC0_WATERMARK 0x015a +#define mmSDMA6_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA6_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA6_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA6_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA6_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC0_PREEMPT 0x0160 +#define mmSDMA6_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC0_DUMMY_REG 0x0161 +#define mmSDMA6_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA6_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA6_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA6_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA6_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA6_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA6_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA6_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA6_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA6_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA6_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA6_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA6_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_CNTL 0x0188 +#define mmSDMA6_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_BASE 0x0189 +#define mmSDMA6_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_BASE_HI 0x018a +#define mmSDMA6_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_RPTR 0x018b +#define mmSDMA6_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA6_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_WPTR 0x018d +#define mmSDMA6_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA6_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA6_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA6_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA6_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_CNTL 0x0192 +#define mmSDMA6_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_RPTR 0x0193 +#define mmSDMA6_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_OFFSET 0x0194 +#define mmSDMA6_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA6_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA6_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_SIZE 0x0197 +#define mmSDMA6_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA6_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA6_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC1_DOORBELL 0x019a +#define mmSDMA6_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC1_STATUS 0x01b0 +#define mmSDMA6_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA6_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC1_WATERMARK 0x01b2 +#define mmSDMA6_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA6_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA6_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA6_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA6_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC1_PREEMPT 0x01b8 +#define mmSDMA6_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA6_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA6_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA6_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA6_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA6_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA6_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA6_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA6_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA6_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA6_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA6_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA6_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA6_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_CNTL 0x01e0 +#define mmSDMA6_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_BASE 0x01e1 +#define mmSDMA6_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA6_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_RPTR 0x01e3 +#define mmSDMA6_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA6_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_WPTR 0x01e5 +#define mmSDMA6_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA6_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA6_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA6_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA6_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_CNTL 0x01ea +#define mmSDMA6_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_RPTR 0x01eb +#define mmSDMA6_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_OFFSET 0x01ec +#define mmSDMA6_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA6_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA6_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_SIZE 0x01ef +#define mmSDMA6_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA6_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA6_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC2_DOORBELL 0x01f2 +#define mmSDMA6_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC2_STATUS 0x0208 +#define mmSDMA6_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA6_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC2_WATERMARK 0x020a +#define mmSDMA6_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA6_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA6_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA6_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA6_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC2_PREEMPT 0x0210 +#define mmSDMA6_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC2_DUMMY_REG 0x0211 +#define mmSDMA6_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA6_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA6_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA6_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA6_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA6_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA6_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA6_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA6_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA6_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA6_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA6_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA6_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_CNTL 0x0238 +#define mmSDMA6_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_BASE 0x0239 +#define mmSDMA6_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_BASE_HI 0x023a +#define mmSDMA6_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_RPTR 0x023b +#define mmSDMA6_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA6_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_WPTR 0x023d +#define mmSDMA6_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA6_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA6_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA6_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA6_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_CNTL 0x0242 +#define mmSDMA6_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_RPTR 0x0243 +#define mmSDMA6_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_OFFSET 0x0244 +#define mmSDMA6_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA6_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA6_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_SIZE 0x0247 +#define mmSDMA6_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA6_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA6_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC3_DOORBELL 0x024a +#define mmSDMA6_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC3_STATUS 0x0260 +#define mmSDMA6_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA6_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC3_WATERMARK 0x0262 +#define mmSDMA6_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA6_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA6_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA6_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA6_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC3_PREEMPT 0x0268 +#define mmSDMA6_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC3_DUMMY_REG 0x0269 +#define mmSDMA6_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA6_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA6_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA6_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA6_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA6_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA6_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA6_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA6_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA6_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA6_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA6_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA6_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_CNTL 0x0290 +#define mmSDMA6_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_BASE 0x0291 +#define mmSDMA6_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA6_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_RPTR 0x0293 +#define mmSDMA6_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA6_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_WPTR 0x0295 +#define mmSDMA6_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA6_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA6_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA6_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA6_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_CNTL 0x029a +#define mmSDMA6_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_RPTR 0x029b +#define mmSDMA6_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_OFFSET 0x029c +#define mmSDMA6_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_BASE_LO 0x029d +#define mmSDMA6_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_BASE_HI 0x029e +#define mmSDMA6_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_SIZE 0x029f +#define mmSDMA6_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA6_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA6_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC4_DOORBELL 0x02a2 +#define mmSDMA6_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC4_STATUS 0x02b8 +#define mmSDMA6_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA6_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC4_WATERMARK 0x02ba +#define mmSDMA6_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA6_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA6_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA6_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA6_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC4_PREEMPT 0x02c0 +#define mmSDMA6_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA6_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA6_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA6_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA6_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA6_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA6_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA6_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA6_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA6_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA6_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA6_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA6_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA6_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_CNTL 0x02e8 +#define mmSDMA6_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_BASE 0x02e9 +#define mmSDMA6_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA6_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_RPTR 0x02eb +#define mmSDMA6_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA6_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_WPTR 0x02ed +#define mmSDMA6_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA6_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA6_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA6_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA6_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_CNTL 0x02f2 +#define mmSDMA6_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_RPTR 0x02f3 +#define mmSDMA6_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA6_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA6_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA6_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_SIZE 0x02f7 +#define mmSDMA6_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA6_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA6_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC5_DOORBELL 0x02fa +#define mmSDMA6_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC5_STATUS 0x0310 +#define mmSDMA6_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA6_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC5_WATERMARK 0x0312 +#define mmSDMA6_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA6_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA6_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA6_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA6_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC5_PREEMPT 0x0318 +#define mmSDMA6_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC5_DUMMY_REG 0x0319 +#define mmSDMA6_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA6_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA6_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA6_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA6_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA6_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA6_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA6_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA6_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA6_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA6_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA6_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA6_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_CNTL 0x0340 +#define mmSDMA6_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_BASE 0x0341 +#define mmSDMA6_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA6_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_RPTR 0x0343 +#define mmSDMA6_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA6_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_WPTR 0x0345 +#define mmSDMA6_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA6_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA6_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA6_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA6_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_CNTL 0x034a +#define mmSDMA6_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_RPTR 0x034b +#define mmSDMA6_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_OFFSET 0x034c +#define mmSDMA6_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_BASE_LO 0x034d +#define mmSDMA6_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_BASE_HI 0x034e +#define mmSDMA6_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_SIZE 0x034f +#define mmSDMA6_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA6_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA6_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC6_DOORBELL 0x0352 +#define mmSDMA6_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC6_STATUS 0x0368 +#define mmSDMA6_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA6_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC6_WATERMARK 0x036a +#define mmSDMA6_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA6_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA6_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA6_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA6_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC6_PREEMPT 0x0370 +#define mmSDMA6_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC6_DUMMY_REG 0x0371 +#define mmSDMA6_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA6_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA6_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA6_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA6_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA6_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA6_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA6_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA6_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA6_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA6_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA6_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA6_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_CNTL 0x0398 +#define mmSDMA6_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_BASE 0x0399 +#define mmSDMA6_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_BASE_HI 0x039a +#define mmSDMA6_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_RPTR 0x039b +#define mmSDMA6_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA6_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_WPTR 0x039d +#define mmSDMA6_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA6_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA6_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA6_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA6_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_CNTL 0x03a2 +#define mmSDMA6_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_RPTR 0x03a3 +#define mmSDMA6_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA6_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA6_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA6_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_SIZE 0x03a7 +#define mmSDMA6_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA6_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA6_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC7_DOORBELL 0x03aa +#define mmSDMA6_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC7_STATUS 0x03c0 +#define mmSDMA6_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA6_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC7_WATERMARK 0x03c2 +#define mmSDMA6_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA6_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA6_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA6_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA6_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC7_PREEMPT 0x03c8 +#define mmSDMA6_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA6_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA6_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA6_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA6_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA6_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA6_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA6_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA6_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA6_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA6_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA6_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA6_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA6_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h new file mode 100644 index 0000000..55569f5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma6_4_2_2_SH_MASK_HEADER +#define _sdma6_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma6_sdma6dec +//SDMA6_UCODE_ADDR +#define SDMA6_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA6_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA6_UCODE_DATA +#define SDMA6_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA6_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA6_VM_CNTL +#define SDMA6_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA6_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA6_VM_CTX_LO +#define SDMA6_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA6_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_VM_CTX_HI +#define SDMA6_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA6_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_ACTIVE_FCN_ID +#define SDMA6_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA6_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA6_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA6_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA6_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA6_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA6_VM_CTX_CNTL +#define SDMA6_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA6_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA6_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA6_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA6_VIRT_RESET_REQ +#define SDMA6_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA6_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA6_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA6_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA6_VF_ENABLE +#define SDMA6_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA6_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA6_CONTEXT_REG_TYPE0 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE__SHIFT 0x1 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_CNTL__SHIFT 0xa +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_RPTR__SHIFT 0xb +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_SIZE__SHIFT 0xf +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_DOORBELL__SHIFT 0x12 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE_MASK 0x00000002L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_DOORBELL_MASK 0x00040000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA6_CONTEXT_REG_TYPE1 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_STATUS__SHIFT 0x8 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_WATERMARK__SHIFT 0xa +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA6_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_PREEMPT__SHIFT 0x10 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA6_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_STATUS_MASK 0x00000100L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_WATERMARK_MASK 0x00000400L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA6_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_PREEMPT_MASK 0x00010000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA6_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA6_CONTEXT_REG_TYPE2 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA6_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA6_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA6_CONTEXT_REG_TYPE3 +#define SDMA6_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA6_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA6_PUB_REG_TYPE0 +#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_ADDR__SHIFT 0x0 +#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_DATA__SHIFT 0x1 +#define SDMA6_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CNTL__SHIFT 0x4 +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_LO__SHIFT 0x5 +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_HI__SHIFT 0x6 +#define SDMA6_PUB_REG_TYPE0__SDMA6_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA6_PUB_REG_TYPE0__SDMA6_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA6_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA6_PUB_REG_TYPE0__SDMA6_MMHUB_CNTL__SHIFT 0x13 +#define SDMA6_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA6_PUB_REG_TYPE0__SDMA6_POWER_CNTL__SHIFT 0x1a +#define SDMA6_PUB_REG_TYPE0__SDMA6_CLK_CTRL__SHIFT 0x1b +#define SDMA6_PUB_REG_TYPE0__SDMA6_CNTL__SHIFT 0x1c +#define SDMA6_PUB_REG_TYPE0__SDMA6_CHICKEN_BITS__SHIFT 0x1d +#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_ADDR_MASK 0x00000001L +#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_DATA_MASK 0x00000002L +#define SDMA6_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CNTL_MASK 0x00000010L +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_LO_MASK 0x00000020L +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_HI_MASK 0x00000040L +#define SDMA6_PUB_REG_TYPE0__SDMA6_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA6_PUB_REG_TYPE0__SDMA6_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA6_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_MMHUB_CNTL_MASK 0x00080000L +#define SDMA6_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_POWER_CNTL_MASK 0x04000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CLK_CTRL_MASK 0x08000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CNTL_MASK 0x10000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CHICKEN_BITS_MASK 0x20000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA6_PUB_REG_TYPE1 +#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA6_PUB_REG_TYPE1__SDMA6_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA6_PUB_REG_TYPE1__SDMA6_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA6_PUB_REG_TYPE1__SDMA6_PROGRAM__SHIFT 0x4 +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS_REG__SHIFT 0x5 +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS1_REG__SHIFT 0x6 +#define SDMA6_PUB_REG_TYPE1__SDMA6_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA6_PUB_REG_TYPE1__SDMA6_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA6_PUB_REG_TYPE1__SDMA6_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA6_PUB_REG_TYPE1__SDMA6_F32_CNTL__SHIFT 0xa +#define SDMA6_PUB_REG_TYPE1__SDMA6_FREEZE__SHIFT 0xb +#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA6_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_CONFIG__SHIFT 0x12 +#define SDMA6_PUB_REG_TYPE1__SDMA6_BA_THRESHOLD__SHIFT 0x13 +#define SDMA6_PUB_REG_TYPE1__SDMA6_ID__SHIFT 0x14 +#define SDMA6_PUB_REG_TYPE1__SDMA6_VERSION__SHIFT 0x15 +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER__SHIFT 0x16 +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS2_REG__SHIFT 0x18 +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_CNTL__SHIFT 0x1c +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA6_PUB_REG_TYPE1__SDMA6_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA6_PUB_REG_TYPE1__SDMA6_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA6_PUB_REG_TYPE1__SDMA6_PROGRAM_MASK 0x00000010L +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS_REG_MASK 0x00000020L +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS1_REG_MASK 0x00000040L +#define SDMA6_PUB_REG_TYPE1__SDMA6_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA6_PUB_REG_TYPE1__SDMA6_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA6_PUB_REG_TYPE1__SDMA6_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA6_PUB_REG_TYPE1__SDMA6_F32_CNTL_MASK 0x00000400L +#define SDMA6_PUB_REG_TYPE1__SDMA6_FREEZE_MASK 0x00000800L +#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA6_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_CONFIG_MASK 0x00040000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_BA_THRESHOLD_MASK 0x00080000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_ID_MASK 0x00100000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_VERSION_MASK 0x00200000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER_MASK 0x00400000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS2_REG_MASK 0x01000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_CNTL_MASK 0x10000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA6_PUB_REG_TYPE2 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV0__SHIFT 0x0 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV1__SHIFT 0x1 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV2__SHIFT 0x2 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_PAGE__SHIFT 0x8 +#define SDMA6_PUB_REG_TYPE2__SDMA6_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA6_PUB_REG_TYPE2__SDMA6_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA6_PUB_REG_TYPE2__SDMA6_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA6_PUB_REG_TYPE2__SDMA6_STATUS3_REG__SHIFT 0xc +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA6_PUB_REG_TYPE2__SDMA6_ERROR_LOG__SHIFT 0x10 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA6_PUB_REG_TYPE2__SDMA6_F32_COUNTER__SHIFT 0x15 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UNBREAKABLE__SHIFT 0x16 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFMON_CNTL__SHIFT 0x17 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA6_PUB_REG_TYPE2__SDMA6_CRD_CNTL__SHIFT 0x1b +#define SDMA6_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA6_PUB_REG_TYPE2__SDMA6_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA6_PUB_REG_TYPE2__SDMA6_ULV_CNTL__SHIFT 0x1e +#define SDMA6_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV0_MASK 0x00000001L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV1_MASK 0x00000002L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV2_MASK 0x00000004L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_PAGE_MASK 0x00000100L +#define SDMA6_PUB_REG_TYPE2__SDMA6_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA6_PUB_REG_TYPE2__SDMA6_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA6_PUB_REG_TYPE2__SDMA6_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA6_PUB_REG_TYPE2__SDMA6_STATUS3_REG_MASK 0x00001000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_ERROR_LOG_MASK 0x00010000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_F32_COUNTER_MASK 0x00200000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UNBREAKABLE_MASK 0x00400000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFMON_CNTL_MASK 0x00800000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_CRD_CNTL_MASK 0x08000000L +#define SDMA6_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_ULV_CNTL_MASK 0x40000000L +#define SDMA6_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA6_PUB_REG_TYPE3 +#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA6_PUB_REG_TYPE3__SDMA6_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA6_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA6_PUB_REG_TYPE3__SDMA6_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA6_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA6_MMHUB_CNTL +#define SDMA6_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA6_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA6_CONTEXT_GROUP_BOUNDARY +#define SDMA6_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA6_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA6_POWER_CNTL +#define SDMA6_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA6_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA6_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA6_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA6_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA6_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA6_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA6_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA6_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA6_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA6_CLK_CTRL +#define SDMA6_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA6_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA6_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA6_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA6_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA6_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA6_CNTL +#define SDMA6_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA6_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA6_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA6_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA6_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA6_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA6_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA6_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA6_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA6_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA6_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA6_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA6_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA6_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA6_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA6_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA6_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA6_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA6_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA6_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA6_CHICKEN_BITS +#define SDMA6_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA6_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA6_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA6_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA6_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA6_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA6_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA6_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA6_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA6_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA6_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA6_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA6_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA6_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA6_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA6_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA6_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA6_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA6_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA6_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA6_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA6_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA6_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA6_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA6_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA6_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA6_GB_ADDR_CONFIG +#define SDMA6_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA6_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA6_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA6_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA6_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA6_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA6_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA6_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA6_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA6_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA6_GB_ADDR_CONFIG_READ +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA6_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA6_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA6_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA6_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA6_RB_RPTR_FETCH_HI +#define SDMA6_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA6_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA6_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA6_RB_RPTR_FETCH +#define SDMA6_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA6_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA6_IB_OFFSET_FETCH +#define SDMA6_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA6_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA6_PROGRAM +#define SDMA6_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA6_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA6_STATUS_REG +#define SDMA6_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA6_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA6_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA6_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA6_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA6_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA6_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA6_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA6_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA6_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA6_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA6_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA6_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA6_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA6_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA6_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA6_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA6_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA6_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA6_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA6_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA6_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA6_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA6_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA6_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA6_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA6_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA6_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA6_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA6_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA6_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA6_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA6_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA6_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA6_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA6_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA6_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA6_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA6_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA6_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA6_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA6_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA6_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA6_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA6_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA6_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA6_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA6_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA6_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA6_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA6_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA6_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA6_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA6_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA6_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA6_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA6_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA6_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA6_STATUS1_REG +#define SDMA6_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA6_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA6_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA6_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA6_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA6_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA6_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA6_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA6_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA6_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA6_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA6_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA6_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA6_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA6_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA6_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA6_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA6_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA6_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA6_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA6_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA6_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA6_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA6_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA6_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA6_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA6_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA6_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA6_RD_BURST_CNTL +#define SDMA6_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA6_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA6_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA6_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA6_HBM_PAGE_CONFIG +#define SDMA6_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA6_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA6_UCODE_CHECKSUM +#define SDMA6_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA6_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA6_F32_CNTL +#define SDMA6_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA6_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA6_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA6_F32_CNTL__STEP_MASK 0x00000002L +//SDMA6_FREEZE +#define SDMA6_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA6_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA6_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA6_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA6_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA6_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA6_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA6_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA6_PHASE0_QUANTUM +#define SDMA6_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA6_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA6_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA6_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA6_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA6_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA6_PHASE1_QUANTUM +#define SDMA6_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA6_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA6_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA6_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA6_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA6_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA6_EDC_CONFIG +#define SDMA6_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA6_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA6_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA6_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA6_BA_THRESHOLD +#define SDMA6_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA6_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA6_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA6_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA6_ID +#define SDMA6_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA6_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA6_VERSION +#define SDMA6_VERSION__MINVER__SHIFT 0x0 +#define SDMA6_VERSION__MAJVER__SHIFT 0x8 +#define SDMA6_VERSION__REV__SHIFT 0x10 +#define SDMA6_VERSION__MINVER_MASK 0x0000007FL +#define SDMA6_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA6_VERSION__REV_MASK 0x003F0000L +//SDMA6_EDC_COUNTER +#define SDMA6_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA6_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA6_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA6_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA6_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA6_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA6_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA6_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA6_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA6_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA6_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA6_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA6_EDC_COUNTER_CLEAR +#define SDMA6_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA6_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA6_STATUS2_REG +#define SDMA6_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA6_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA6_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA6_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA6_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA6_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA6_ATOMIC_CNTL +#define SDMA6_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA6_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA6_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA6_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA6_ATOMIC_PREOP_LO +#define SDMA6_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA6_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA6_ATOMIC_PREOP_HI +#define SDMA6_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA6_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA6_UTCL1_CNTL +#define SDMA6_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA6_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA6_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA6_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA6_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA6_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA6_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA6_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA6_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA6_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA6_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA6_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA6_UTCL1_WATERMK +#define SDMA6_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA6_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA6_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA6_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA6_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA6_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA6_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA6_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA6_UTCL1_RD_STATUS +#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA6_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA6_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA6_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA6_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA6_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA6_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA6_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA6_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA6_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA6_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA6_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA6_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA6_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA6_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA6_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA6_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA6_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA6_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA6_UTCL1_WR_STATUS +#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA6_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA6_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA6_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA6_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA6_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA6_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA6_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA6_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA6_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA6_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA6_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA6_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA6_UTCL1_INV0 +#define SDMA6_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA6_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA6_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA6_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA6_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA6_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA6_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA6_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA6_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA6_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA6_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA6_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA6_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA6_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA6_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA6_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA6_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA6_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA6_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA6_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA6_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA6_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA6_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA6_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA6_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA6_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA6_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA6_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA6_UTCL1_INV1 +#define SDMA6_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA6_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA6_UTCL1_INV2 +#define SDMA6_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA6_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA6_UTCL1_RD_XNACK0 +#define SDMA6_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA6_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA6_UTCL1_RD_XNACK1 +#define SDMA6_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA6_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA6_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA6_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA6_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA6_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA6_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA6_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA6_UTCL1_WR_XNACK0 +#define SDMA6_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA6_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA6_UTCL1_WR_XNACK1 +#define SDMA6_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA6_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA6_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA6_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA6_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA6_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA6_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA6_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA6_UTCL1_TIMEOUT +#define SDMA6_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA6_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA6_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA6_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA6_UTCL1_PAGE +#define SDMA6_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA6_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA6_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA6_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA6_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA6_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA6_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA6_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA6_POWER_CNTL_IDLE +#define SDMA6_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA6_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA6_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA6_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA6_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA6_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA6_RELAX_ORDERING_LUT +#define SDMA6_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA6_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA6_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA6_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA6_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA6_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA6_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA6_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA6_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA6_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA6_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA6_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA6_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA6_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA6_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA6_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA6_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA6_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA6_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA6_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA6_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA6_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA6_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA6_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA6_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA6_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA6_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA6_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA6_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA6_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA6_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA6_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA6_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA6_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA6_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA6_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA6_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA6_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA6_CHICKEN_BITS_2 +#define SDMA6_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA6_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA6_STATUS3_REG +#define SDMA6_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA6_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA6_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA6_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA6_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA6_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA6_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA6_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA6_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA6_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA6_PHYSICAL_ADDR_LO +#define SDMA6_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA6_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA6_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA6_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA6_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA6_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA6_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA6_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA6_PHYSICAL_ADDR_HI +#define SDMA6_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA6_PHASE2_QUANTUM +#define SDMA6_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA6_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA6_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA6_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA6_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA6_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA6_ERROR_LOG +#define SDMA6_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA6_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA6_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA6_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA6_PUB_DUMMY_REG0 +#define SDMA6_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA6_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA6_PUB_DUMMY_REG1 +#define SDMA6_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA6_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA6_PUB_DUMMY_REG2 +#define SDMA6_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA6_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA6_PUB_DUMMY_REG3 +#define SDMA6_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA6_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA6_F32_COUNTER +#define SDMA6_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA6_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA6_UNBREAKABLE +#define SDMA6_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA6_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA6_PERFMON_CNTL +#define SDMA6_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA6_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA6_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA6_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA6_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA6_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA6_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA6_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA6_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA6_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA6_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA6_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA6_PERFCOUNTER0_RESULT +#define SDMA6_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA6_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA6_PERFCOUNTER1_RESULT +#define SDMA6_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA6_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA6_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA6_CRD_CNTL +#define SDMA6_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA6_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA6_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA6_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA6_GPU_IOV_VIOLATION_LOG +#define SDMA6_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA6_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA6_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA6_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA6_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA6_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA6_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA6_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA6_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA6_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA6_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA6_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA6_ULV_CNTL +#define SDMA6_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA6_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA6_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA6_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA6_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA6_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA6_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA6_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA6_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA6_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA6_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA6_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA6_EA_DBIT_ADDR_DATA +#define SDMA6_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA6_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA6_EA_DBIT_ADDR_INDEX +#define SDMA6_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA6_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA6_GPU_IOV_VIOLATION_LOG2 +#define SDMA6_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA6_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA6_GFX_RB_CNTL +#define SDMA6_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_GFX_RB_BASE +#define SDMA6_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_BASE_HI +#define SDMA6_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_GFX_RB_RPTR +#define SDMA6_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_RPTR_HI +#define SDMA6_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_WPTR +#define SDMA6_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_WPTR_HI +#define SDMA6_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_WPTR_POLL_CNTL +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_GFX_RB_RPTR_ADDR_HI +#define SDMA6_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_RPTR_ADDR_LO +#define SDMA6_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_GFX_IB_CNTL +#define SDMA6_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_GFX_IB_RPTR +#define SDMA6_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_GFX_IB_OFFSET +#define SDMA6_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_GFX_IB_BASE_LO +#define SDMA6_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_GFX_IB_BASE_HI +#define SDMA6_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_GFX_IB_SIZE +#define SDMA6_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_GFX_SKIP_CNTL +#define SDMA6_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_GFX_CONTEXT_STATUS +#define SDMA6_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_GFX_DOORBELL +#define SDMA6_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_GFX_CONTEXT_CNTL +#define SDMA6_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA6_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA6_GFX_STATUS +#define SDMA6_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_GFX_DOORBELL_LOG +#define SDMA6_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_GFX_WATERMARK +#define SDMA6_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_GFX_DOORBELL_OFFSET +#define SDMA6_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_GFX_CSA_ADDR_LO +#define SDMA6_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_GFX_CSA_ADDR_HI +#define SDMA6_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_GFX_IB_SUB_REMAIN +#define SDMA6_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_GFX_PREEMPT +#define SDMA6_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_GFX_DUMMY_REG +#define SDMA6_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA6_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA6_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_GFX_RB_AQL_CNTL +#define SDMA6_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_GFX_MINOR_PTR_UPDATE +#define SDMA6_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_GFX_MIDCMD_DATA0 +#define SDMA6_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA1 +#define SDMA6_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA2 +#define SDMA6_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA3 +#define SDMA6_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA4 +#define SDMA6_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA5 +#define SDMA6_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA6 +#define SDMA6_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA7 +#define SDMA6_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA8 +#define SDMA6_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_CNTL +#define SDMA6_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_PAGE_RB_CNTL +#define SDMA6_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_PAGE_RB_BASE +#define SDMA6_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_BASE_HI +#define SDMA6_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_PAGE_RB_RPTR +#define SDMA6_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_RPTR_HI +#define SDMA6_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_WPTR +#define SDMA6_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_WPTR_HI +#define SDMA6_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_WPTR_POLL_CNTL +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_PAGE_RB_RPTR_ADDR_HI +#define SDMA6_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_RPTR_ADDR_LO +#define SDMA6_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_PAGE_IB_CNTL +#define SDMA6_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_PAGE_IB_RPTR +#define SDMA6_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_PAGE_IB_OFFSET +#define SDMA6_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_PAGE_IB_BASE_LO +#define SDMA6_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_PAGE_IB_BASE_HI +#define SDMA6_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_PAGE_IB_SIZE +#define SDMA6_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_PAGE_SKIP_CNTL +#define SDMA6_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_PAGE_CONTEXT_STATUS +#define SDMA6_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_PAGE_DOORBELL +#define SDMA6_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_PAGE_STATUS +#define SDMA6_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_PAGE_DOORBELL_LOG +#define SDMA6_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_PAGE_WATERMARK +#define SDMA6_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_PAGE_DOORBELL_OFFSET +#define SDMA6_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_PAGE_CSA_ADDR_LO +#define SDMA6_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_PAGE_CSA_ADDR_HI +#define SDMA6_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_PAGE_IB_SUB_REMAIN +#define SDMA6_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_PAGE_PREEMPT +#define SDMA6_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_PAGE_DUMMY_REG +#define SDMA6_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_PAGE_RB_AQL_CNTL +#define SDMA6_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_PAGE_MINOR_PTR_UPDATE +#define SDMA6_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_PAGE_MIDCMD_DATA0 +#define SDMA6_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA1 +#define SDMA6_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA2 +#define SDMA6_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA3 +#define SDMA6_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA4 +#define SDMA6_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA5 +#define SDMA6_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA6 +#define SDMA6_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA7 +#define SDMA6_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA8 +#define SDMA6_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_CNTL +#define SDMA6_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC0_RB_CNTL +#define SDMA6_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC0_RB_BASE +#define SDMA6_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_BASE_HI +#define SDMA6_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC0_RB_RPTR +#define SDMA6_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_RPTR_HI +#define SDMA6_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_WPTR +#define SDMA6_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_WPTR_HI +#define SDMA6_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_WPTR_POLL_CNTL +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC0_RB_RPTR_ADDR_HI +#define SDMA6_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_RPTR_ADDR_LO +#define SDMA6_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC0_IB_CNTL +#define SDMA6_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC0_IB_RPTR +#define SDMA6_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC0_IB_OFFSET +#define SDMA6_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC0_IB_BASE_LO +#define SDMA6_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC0_IB_BASE_HI +#define SDMA6_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC0_IB_SIZE +#define SDMA6_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC0_SKIP_CNTL +#define SDMA6_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC0_CONTEXT_STATUS +#define SDMA6_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC0_DOORBELL +#define SDMA6_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC0_STATUS +#define SDMA6_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC0_DOORBELL_LOG +#define SDMA6_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC0_WATERMARK +#define SDMA6_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC0_DOORBELL_OFFSET +#define SDMA6_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC0_CSA_ADDR_LO +#define SDMA6_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC0_CSA_ADDR_HI +#define SDMA6_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC0_IB_SUB_REMAIN +#define SDMA6_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC0_PREEMPT +#define SDMA6_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC0_DUMMY_REG +#define SDMA6_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC0_RB_AQL_CNTL +#define SDMA6_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC0_MINOR_PTR_UPDATE +#define SDMA6_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC0_MIDCMD_DATA0 +#define SDMA6_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA1 +#define SDMA6_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA2 +#define SDMA6_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA3 +#define SDMA6_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA4 +#define SDMA6_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA5 +#define SDMA6_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA6 +#define SDMA6_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA7 +#define SDMA6_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA8 +#define SDMA6_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_CNTL +#define SDMA6_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC1_RB_CNTL +#define SDMA6_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC1_RB_BASE +#define SDMA6_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_BASE_HI +#define SDMA6_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC1_RB_RPTR +#define SDMA6_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_RPTR_HI +#define SDMA6_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_WPTR +#define SDMA6_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_WPTR_HI +#define SDMA6_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_WPTR_POLL_CNTL +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC1_RB_RPTR_ADDR_HI +#define SDMA6_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_RPTR_ADDR_LO +#define SDMA6_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC1_IB_CNTL +#define SDMA6_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC1_IB_RPTR +#define SDMA6_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC1_IB_OFFSET +#define SDMA6_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC1_IB_BASE_LO +#define SDMA6_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC1_IB_BASE_HI +#define SDMA6_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC1_IB_SIZE +#define SDMA6_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC1_SKIP_CNTL +#define SDMA6_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC1_CONTEXT_STATUS +#define SDMA6_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC1_DOORBELL +#define SDMA6_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC1_STATUS +#define SDMA6_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC1_DOORBELL_LOG +#define SDMA6_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC1_WATERMARK +#define SDMA6_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC1_DOORBELL_OFFSET +#define SDMA6_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC1_CSA_ADDR_LO +#define SDMA6_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC1_CSA_ADDR_HI +#define SDMA6_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC1_IB_SUB_REMAIN +#define SDMA6_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC1_PREEMPT +#define SDMA6_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC1_DUMMY_REG +#define SDMA6_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC1_RB_AQL_CNTL +#define SDMA6_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC1_MINOR_PTR_UPDATE +#define SDMA6_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC1_MIDCMD_DATA0 +#define SDMA6_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA1 +#define SDMA6_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA2 +#define SDMA6_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA3 +#define SDMA6_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA4 +#define SDMA6_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA5 +#define SDMA6_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA6 +#define SDMA6_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA7 +#define SDMA6_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA8 +#define SDMA6_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_CNTL +#define SDMA6_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC2_RB_CNTL +#define SDMA6_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC2_RB_BASE +#define SDMA6_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_BASE_HI +#define SDMA6_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC2_RB_RPTR +#define SDMA6_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_RPTR_HI +#define SDMA6_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_WPTR +#define SDMA6_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_WPTR_HI +#define SDMA6_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_WPTR_POLL_CNTL +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC2_RB_RPTR_ADDR_HI +#define SDMA6_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_RPTR_ADDR_LO +#define SDMA6_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC2_IB_CNTL +#define SDMA6_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC2_IB_RPTR +#define SDMA6_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC2_IB_OFFSET +#define SDMA6_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC2_IB_BASE_LO +#define SDMA6_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC2_IB_BASE_HI +#define SDMA6_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC2_IB_SIZE +#define SDMA6_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC2_SKIP_CNTL +#define SDMA6_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC2_CONTEXT_STATUS +#define SDMA6_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC2_DOORBELL +#define SDMA6_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC2_STATUS +#define SDMA6_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC2_DOORBELL_LOG +#define SDMA6_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC2_WATERMARK +#define SDMA6_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC2_DOORBELL_OFFSET +#define SDMA6_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC2_CSA_ADDR_LO +#define SDMA6_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC2_CSA_ADDR_HI +#define SDMA6_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC2_IB_SUB_REMAIN +#define SDMA6_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC2_PREEMPT +#define SDMA6_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC2_DUMMY_REG +#define SDMA6_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC2_RB_AQL_CNTL +#define SDMA6_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC2_MINOR_PTR_UPDATE +#define SDMA6_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC2_MIDCMD_DATA0 +#define SDMA6_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA1 +#define SDMA6_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA2 +#define SDMA6_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA3 +#define SDMA6_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA4 +#define SDMA6_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA5 +#define SDMA6_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA6 +#define SDMA6_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA7 +#define SDMA6_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA8 +#define SDMA6_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_CNTL +#define SDMA6_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC3_RB_CNTL +#define SDMA6_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC3_RB_BASE +#define SDMA6_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_BASE_HI +#define SDMA6_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC3_RB_RPTR +#define SDMA6_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_RPTR_HI +#define SDMA6_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_WPTR +#define SDMA6_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_WPTR_HI +#define SDMA6_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_WPTR_POLL_CNTL +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC3_RB_RPTR_ADDR_HI +#define SDMA6_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_RPTR_ADDR_LO +#define SDMA6_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC3_IB_CNTL +#define SDMA6_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC3_IB_RPTR +#define SDMA6_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC3_IB_OFFSET +#define SDMA6_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC3_IB_BASE_LO +#define SDMA6_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC3_IB_BASE_HI +#define SDMA6_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC3_IB_SIZE +#define SDMA6_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC3_SKIP_CNTL +#define SDMA6_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC3_CONTEXT_STATUS +#define SDMA6_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC3_DOORBELL +#define SDMA6_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC3_STATUS +#define SDMA6_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC3_DOORBELL_LOG +#define SDMA6_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC3_WATERMARK +#define SDMA6_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC3_DOORBELL_OFFSET +#define SDMA6_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC3_CSA_ADDR_LO +#define SDMA6_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC3_CSA_ADDR_HI +#define SDMA6_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC3_IB_SUB_REMAIN +#define SDMA6_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC3_PREEMPT +#define SDMA6_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC3_DUMMY_REG +#define SDMA6_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC3_RB_AQL_CNTL +#define SDMA6_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC3_MINOR_PTR_UPDATE +#define SDMA6_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC3_MIDCMD_DATA0 +#define SDMA6_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA1 +#define SDMA6_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA2 +#define SDMA6_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA3 +#define SDMA6_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA4 +#define SDMA6_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA5 +#define SDMA6_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA6 +#define SDMA6_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA7 +#define SDMA6_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA8 +#define SDMA6_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_CNTL +#define SDMA6_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC4_RB_CNTL +#define SDMA6_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC4_RB_BASE +#define SDMA6_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_BASE_HI +#define SDMA6_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC4_RB_RPTR +#define SDMA6_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_RPTR_HI +#define SDMA6_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_WPTR +#define SDMA6_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_WPTR_HI +#define SDMA6_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_WPTR_POLL_CNTL +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC4_RB_RPTR_ADDR_HI +#define SDMA6_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_RPTR_ADDR_LO +#define SDMA6_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC4_IB_CNTL +#define SDMA6_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC4_IB_RPTR +#define SDMA6_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC4_IB_OFFSET +#define SDMA6_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC4_IB_BASE_LO +#define SDMA6_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC4_IB_BASE_HI +#define SDMA6_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC4_IB_SIZE +#define SDMA6_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC4_SKIP_CNTL +#define SDMA6_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC4_CONTEXT_STATUS +#define SDMA6_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC4_DOORBELL +#define SDMA6_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC4_STATUS +#define SDMA6_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC4_DOORBELL_LOG +#define SDMA6_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC4_WATERMARK +#define SDMA6_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC4_DOORBELL_OFFSET +#define SDMA6_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC4_CSA_ADDR_LO +#define SDMA6_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC4_CSA_ADDR_HI +#define SDMA6_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC4_IB_SUB_REMAIN +#define SDMA6_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC4_PREEMPT +#define SDMA6_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC4_DUMMY_REG +#define SDMA6_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC4_RB_AQL_CNTL +#define SDMA6_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC4_MINOR_PTR_UPDATE +#define SDMA6_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC4_MIDCMD_DATA0 +#define SDMA6_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA1 +#define SDMA6_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA2 +#define SDMA6_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA3 +#define SDMA6_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA4 +#define SDMA6_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA5 +#define SDMA6_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA6 +#define SDMA6_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA7 +#define SDMA6_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA8 +#define SDMA6_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_CNTL +#define SDMA6_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC5_RB_CNTL +#define SDMA6_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC5_RB_BASE +#define SDMA6_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_BASE_HI +#define SDMA6_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC5_RB_RPTR +#define SDMA6_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_RPTR_HI +#define SDMA6_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_WPTR +#define SDMA6_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_WPTR_HI +#define SDMA6_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_WPTR_POLL_CNTL +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC5_RB_RPTR_ADDR_HI +#define SDMA6_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_RPTR_ADDR_LO +#define SDMA6_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC5_IB_CNTL +#define SDMA6_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC5_IB_RPTR +#define SDMA6_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC5_IB_OFFSET +#define SDMA6_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC5_IB_BASE_LO +#define SDMA6_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC5_IB_BASE_HI +#define SDMA6_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC5_IB_SIZE +#define SDMA6_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC5_SKIP_CNTL +#define SDMA6_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC5_CONTEXT_STATUS +#define SDMA6_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC5_DOORBELL +#define SDMA6_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC5_STATUS +#define SDMA6_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC5_DOORBELL_LOG +#define SDMA6_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC5_WATERMARK +#define SDMA6_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC5_DOORBELL_OFFSET +#define SDMA6_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC5_CSA_ADDR_LO +#define SDMA6_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC5_CSA_ADDR_HI +#define SDMA6_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC5_IB_SUB_REMAIN +#define SDMA6_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC5_PREEMPT +#define SDMA6_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC5_DUMMY_REG +#define SDMA6_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC5_RB_AQL_CNTL +#define SDMA6_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC5_MINOR_PTR_UPDATE +#define SDMA6_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC5_MIDCMD_DATA0 +#define SDMA6_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA1 +#define SDMA6_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA2 +#define SDMA6_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA3 +#define SDMA6_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA4 +#define SDMA6_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA5 +#define SDMA6_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA6 +#define SDMA6_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA7 +#define SDMA6_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA8 +#define SDMA6_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_CNTL +#define SDMA6_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC6_RB_CNTL +#define SDMA6_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC6_RB_BASE +#define SDMA6_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_BASE_HI +#define SDMA6_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC6_RB_RPTR +#define SDMA6_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_RPTR_HI +#define SDMA6_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_WPTR +#define SDMA6_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_WPTR_HI +#define SDMA6_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_WPTR_POLL_CNTL +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC6_RB_RPTR_ADDR_HI +#define SDMA6_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_RPTR_ADDR_LO +#define SDMA6_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC6_IB_CNTL +#define SDMA6_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC6_IB_RPTR +#define SDMA6_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC6_IB_OFFSET +#define SDMA6_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC6_IB_BASE_LO +#define SDMA6_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC6_IB_BASE_HI +#define SDMA6_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC6_IB_SIZE +#define SDMA6_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC6_SKIP_CNTL +#define SDMA6_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC6_CONTEXT_STATUS +#define SDMA6_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC6_DOORBELL +#define SDMA6_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC6_STATUS +#define SDMA6_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC6_DOORBELL_LOG +#define SDMA6_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC6_WATERMARK +#define SDMA6_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC6_DOORBELL_OFFSET +#define SDMA6_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC6_CSA_ADDR_LO +#define SDMA6_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC6_CSA_ADDR_HI +#define SDMA6_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC6_IB_SUB_REMAIN +#define SDMA6_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC6_PREEMPT +#define SDMA6_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC6_DUMMY_REG +#define SDMA6_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC6_RB_AQL_CNTL +#define SDMA6_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC6_MINOR_PTR_UPDATE +#define SDMA6_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC6_MIDCMD_DATA0 +#define SDMA6_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA1 +#define SDMA6_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA2 +#define SDMA6_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA3 +#define SDMA6_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA4 +#define SDMA6_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA5 +#define SDMA6_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA6 +#define SDMA6_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA7 +#define SDMA6_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA8 +#define SDMA6_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_CNTL +#define SDMA6_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC7_RB_CNTL +#define SDMA6_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC7_RB_BASE +#define SDMA6_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_BASE_HI +#define SDMA6_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC7_RB_RPTR +#define SDMA6_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_RPTR_HI +#define SDMA6_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_WPTR +#define SDMA6_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_WPTR_HI +#define SDMA6_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_WPTR_POLL_CNTL +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC7_RB_RPTR_ADDR_HI +#define SDMA6_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_RPTR_ADDR_LO +#define SDMA6_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC7_IB_CNTL +#define SDMA6_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC7_IB_RPTR +#define SDMA6_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC7_IB_OFFSET +#define SDMA6_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC7_IB_BASE_LO +#define SDMA6_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC7_IB_BASE_HI +#define SDMA6_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC7_IB_SIZE +#define SDMA6_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC7_SKIP_CNTL +#define SDMA6_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC7_CONTEXT_STATUS +#define SDMA6_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC7_DOORBELL +#define SDMA6_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC7_STATUS +#define SDMA6_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC7_DOORBELL_LOG +#define SDMA6_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC7_WATERMARK +#define SDMA6_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC7_DOORBELL_OFFSET +#define SDMA6_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC7_CSA_ADDR_LO +#define SDMA6_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC7_CSA_ADDR_HI +#define SDMA6_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC7_IB_SUB_REMAIN +#define SDMA6_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC7_PREEMPT +#define SDMA6_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC7_DUMMY_REG +#define SDMA6_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC7_RB_AQL_CNTL +#define SDMA6_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC7_MINOR_PTR_UPDATE +#define SDMA6_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC7_MIDCMD_DATA0 +#define SDMA6_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA1 +#define SDMA6_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA2 +#define SDMA6_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA3 +#define SDMA6_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA4 +#define SDMA6_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA5 +#define SDMA6_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA6 +#define SDMA6_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA7 +#define SDMA6_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA8 +#define SDMA6_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_CNTL +#define SDMA6_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h new file mode 100644 index 0000000..10f3872 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma7_4_2_2_OFFSET_HEADER +#define _sdma7_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma7_sdma7dec +// base address: 0x7d000 +#define mmSDMA7_UCODE_ADDR 0x0000 +#define mmSDMA7_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA7_UCODE_DATA 0x0001 +#define mmSDMA7_UCODE_DATA_BASE_IDX 1 +#define mmSDMA7_VM_CNTL 0x0004 +#define mmSDMA7_VM_CNTL_BASE_IDX 1 +#define mmSDMA7_VM_CTX_LO 0x0005 +#define mmSDMA7_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA7_VM_CTX_HI 0x0006 +#define mmSDMA7_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA7_ACTIVE_FCN_ID 0x0007 +#define mmSDMA7_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA7_VM_CTX_CNTL 0x0008 +#define mmSDMA7_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA7_VIRT_RESET_REQ 0x0009 +#define mmSDMA7_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA7_VF_ENABLE 0x000a +#define mmSDMA7_VF_ENABLE_BASE_IDX 1 +#define mmSDMA7_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA7_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA7_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA7_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA7_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA7_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA7_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA7_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA7_PUB_REG_TYPE0 0x000f +#define mmSDMA7_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA7_PUB_REG_TYPE1 0x0010 +#define mmSDMA7_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA7_PUB_REG_TYPE2 0x0011 +#define mmSDMA7_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA7_PUB_REG_TYPE3 0x0012 +#define mmSDMA7_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA7_MMHUB_CNTL 0x0013 +#define mmSDMA7_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA7_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA7_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA7_POWER_CNTL 0x001a +#define mmSDMA7_POWER_CNTL_BASE_IDX 1 +#define mmSDMA7_CLK_CTRL 0x001b +#define mmSDMA7_CLK_CTRL_BASE_IDX 1 +#define mmSDMA7_CNTL 0x001c +#define mmSDMA7_CNTL_BASE_IDX 1 +#define mmSDMA7_CHICKEN_BITS 0x001d +#define mmSDMA7_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA7_GB_ADDR_CONFIG 0x001e +#define mmSDMA7_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA7_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA7_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA7_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA7_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA7_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA7_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA7_RB_RPTR_FETCH 0x0022 +#define mmSDMA7_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA7_IB_OFFSET_FETCH 0x0023 +#define mmSDMA7_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA7_PROGRAM 0x0024 +#define mmSDMA7_PROGRAM_BASE_IDX 1 +#define mmSDMA7_STATUS_REG 0x0025 +#define mmSDMA7_STATUS_REG_BASE_IDX 1 +#define mmSDMA7_STATUS1_REG 0x0026 +#define mmSDMA7_STATUS1_REG_BASE_IDX 1 +#define mmSDMA7_RD_BURST_CNTL 0x0027 +#define mmSDMA7_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA7_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA7_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA7_UCODE_CHECKSUM 0x0029 +#define mmSDMA7_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA7_F32_CNTL 0x002a +#define mmSDMA7_F32_CNTL_BASE_IDX 1 +#define mmSDMA7_FREEZE 0x002b +#define mmSDMA7_FREEZE_BASE_IDX 1 +#define mmSDMA7_PHASE0_QUANTUM 0x002c +#define mmSDMA7_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA7_PHASE1_QUANTUM 0x002d +#define mmSDMA7_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA7_EDC_CONFIG 0x0032 +#define mmSDMA7_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA7_BA_THRESHOLD 0x0033 +#define mmSDMA7_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA7_ID 0x0034 +#define mmSDMA7_ID_BASE_IDX 1 +#define mmSDMA7_VERSION 0x0035 +#define mmSDMA7_VERSION_BASE_IDX 1 +#define mmSDMA7_EDC_COUNTER 0x0036 +#define mmSDMA7_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA7_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA7_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA7_STATUS2_REG 0x0038 +#define mmSDMA7_STATUS2_REG_BASE_IDX 1 +#define mmSDMA7_ATOMIC_CNTL 0x0039 +#define mmSDMA7_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA7_ATOMIC_PREOP_LO 0x003a +#define mmSDMA7_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA7_ATOMIC_PREOP_HI 0x003b +#define mmSDMA7_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA7_UTCL1_CNTL 0x003c +#define mmSDMA7_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA7_UTCL1_WATERMK 0x003d +#define mmSDMA7_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA7_UTCL1_RD_STATUS 0x003e +#define mmSDMA7_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA7_UTCL1_WR_STATUS 0x003f +#define mmSDMA7_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA7_UTCL1_INV0 0x0040 +#define mmSDMA7_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA7_UTCL1_INV1 0x0041 +#define mmSDMA7_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA7_UTCL1_INV2 0x0042 +#define mmSDMA7_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA7_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA7_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA7_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA7_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA7_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA7_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA7_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA7_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA7_UTCL1_TIMEOUT 0x0047 +#define mmSDMA7_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA7_UTCL1_PAGE 0x0048 +#define mmSDMA7_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA7_POWER_CNTL_IDLE 0x0049 +#define mmSDMA7_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA7_RELAX_ORDERING_LUT 0x004a +#define mmSDMA7_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA7_CHICKEN_BITS_2 0x004b +#define mmSDMA7_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA7_STATUS3_REG 0x004c +#define mmSDMA7_STATUS3_REG_BASE_IDX 1 +#define mmSDMA7_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA7_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA7_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_PHASE2_QUANTUM 0x004f +#define mmSDMA7_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA7_ERROR_LOG 0x0050 +#define mmSDMA7_ERROR_LOG_BASE_IDX 1 +#define mmSDMA7_PUB_DUMMY_REG0 0x0051 +#define mmSDMA7_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA7_PUB_DUMMY_REG1 0x0052 +#define mmSDMA7_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA7_PUB_DUMMY_REG2 0x0053 +#define mmSDMA7_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA7_PUB_DUMMY_REG3 0x0054 +#define mmSDMA7_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA7_F32_COUNTER 0x0055 +#define mmSDMA7_F32_COUNTER_BASE_IDX 1 +#define mmSDMA7_UNBREAKABLE 0x0056 +#define mmSDMA7_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA7_PERFMON_CNTL 0x0057 +#define mmSDMA7_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA7_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA7_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA7_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA7_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA7_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA7_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA7_CRD_CNTL 0x005b +#define mmSDMA7_CRD_CNTL_BASE_IDX 1 +#define mmSDMA7_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA7_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA7_ULV_CNTL 0x005e +#define mmSDMA7_ULV_CNTL_BASE_IDX 1 +#define mmSDMA7_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA7_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA7_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA7_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA7_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA7_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA7_GFX_RB_CNTL 0x0080 +#define mmSDMA7_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_RB_BASE 0x0081 +#define mmSDMA7_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA7_GFX_RB_BASE_HI 0x0082 +#define mmSDMA7_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_GFX_RB_RPTR 0x0083 +#define mmSDMA7_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA7_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_GFX_RB_WPTR 0x0085 +#define mmSDMA7_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA7_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA7_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA7_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA7_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_GFX_IB_CNTL 0x008a +#define mmSDMA7_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_IB_RPTR 0x008b +#define mmSDMA7_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_GFX_IB_OFFSET 0x008c +#define mmSDMA7_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_GFX_IB_BASE_LO 0x008d +#define mmSDMA7_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_GFX_IB_BASE_HI 0x008e +#define mmSDMA7_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_GFX_IB_SIZE 0x008f +#define mmSDMA7_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_GFX_SKIP_CNTL 0x0090 +#define mmSDMA7_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA7_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_GFX_DOORBELL 0x0092 +#define mmSDMA7_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA7_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA7_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_STATUS 0x00a8 +#define mmSDMA7_GFX_STATUS_BASE_IDX 1 +#define mmSDMA7_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA7_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_GFX_WATERMARK 0x00aa +#define mmSDMA7_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA7_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA7_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA7_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA7_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA7_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_GFX_PREEMPT 0x00b0 +#define mmSDMA7_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA7_GFX_DUMMY_REG 0x00b1 +#define mmSDMA7_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA7_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA7_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA7_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA7_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA7_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA7_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA7_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA7_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA7_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA7_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA7_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA7_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_CNTL 0x00d8 +#define mmSDMA7_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_BASE 0x00d9 +#define mmSDMA7_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_BASE_HI 0x00da +#define mmSDMA7_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_RPTR 0x00db +#define mmSDMA7_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA7_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_WPTR 0x00dd +#define mmSDMA7_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA7_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA7_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA7_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA7_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_CNTL 0x00e2 +#define mmSDMA7_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_RPTR 0x00e3 +#define mmSDMA7_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA7_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA7_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA7_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_SIZE 0x00e7 +#define mmSDMA7_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA7_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA7_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_PAGE_DOORBELL 0x00ea +#define mmSDMA7_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA7_PAGE_STATUS 0x0100 +#define mmSDMA7_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA7_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA7_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_PAGE_WATERMARK 0x0102 +#define mmSDMA7_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA7_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA7_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA7_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA7_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA7_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_PAGE_PREEMPT 0x0108 +#define mmSDMA7_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA7_PAGE_DUMMY_REG 0x0109 +#define mmSDMA7_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA7_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA7_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA7_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA7_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA7_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA7_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA7_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA7_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA7_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA7_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA7_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA7_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_CNTL 0x0130 +#define mmSDMA7_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_BASE 0x0131 +#define mmSDMA7_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA7_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_RPTR 0x0133 +#define mmSDMA7_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA7_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_WPTR 0x0135 +#define mmSDMA7_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA7_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA7_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA7_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA7_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_CNTL 0x013a +#define mmSDMA7_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_RPTR 0x013b +#define mmSDMA7_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_OFFSET 0x013c +#define mmSDMA7_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_BASE_LO 0x013d +#define mmSDMA7_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_BASE_HI 0x013e +#define mmSDMA7_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_SIZE 0x013f +#define mmSDMA7_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA7_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA7_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC0_DOORBELL 0x0142 +#define mmSDMA7_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC0_STATUS 0x0158 +#define mmSDMA7_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA7_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC0_WATERMARK 0x015a +#define mmSDMA7_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA7_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA7_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA7_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA7_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC0_PREEMPT 0x0160 +#define mmSDMA7_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC0_DUMMY_REG 0x0161 +#define mmSDMA7_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA7_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA7_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA7_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA7_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA7_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA7_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA7_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA7_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA7_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA7_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA7_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA7_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_CNTL 0x0188 +#define mmSDMA7_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_BASE 0x0189 +#define mmSDMA7_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_BASE_HI 0x018a +#define mmSDMA7_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_RPTR 0x018b +#define mmSDMA7_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA7_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_WPTR 0x018d +#define mmSDMA7_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA7_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA7_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA7_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA7_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_CNTL 0x0192 +#define mmSDMA7_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_RPTR 0x0193 +#define mmSDMA7_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_OFFSET 0x0194 +#define mmSDMA7_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA7_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA7_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_SIZE 0x0197 +#define mmSDMA7_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA7_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA7_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC1_DOORBELL 0x019a +#define mmSDMA7_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC1_STATUS 0x01b0 +#define mmSDMA7_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA7_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC1_WATERMARK 0x01b2 +#define mmSDMA7_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA7_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA7_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA7_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA7_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC1_PREEMPT 0x01b8 +#define mmSDMA7_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA7_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA7_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA7_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA7_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA7_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA7_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA7_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA7_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA7_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA7_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA7_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA7_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA7_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_CNTL 0x01e0 +#define mmSDMA7_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_BASE 0x01e1 +#define mmSDMA7_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA7_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_RPTR 0x01e3 +#define mmSDMA7_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA7_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_WPTR 0x01e5 +#define mmSDMA7_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA7_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA7_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA7_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA7_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_CNTL 0x01ea +#define mmSDMA7_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_RPTR 0x01eb +#define mmSDMA7_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_OFFSET 0x01ec +#define mmSDMA7_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA7_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA7_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_SIZE 0x01ef +#define mmSDMA7_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA7_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA7_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC2_DOORBELL 0x01f2 +#define mmSDMA7_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC2_STATUS 0x0208 +#define mmSDMA7_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA7_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC2_WATERMARK 0x020a +#define mmSDMA7_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA7_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA7_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA7_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA7_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC2_PREEMPT 0x0210 +#define mmSDMA7_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC2_DUMMY_REG 0x0211 +#define mmSDMA7_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA7_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA7_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA7_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA7_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA7_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA7_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA7_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA7_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA7_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA7_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA7_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA7_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_CNTL 0x0238 +#define mmSDMA7_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_BASE 0x0239 +#define mmSDMA7_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_BASE_HI 0x023a +#define mmSDMA7_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_RPTR 0x023b +#define mmSDMA7_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA7_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_WPTR 0x023d +#define mmSDMA7_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA7_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA7_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA7_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA7_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_CNTL 0x0242 +#define mmSDMA7_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_RPTR 0x0243 +#define mmSDMA7_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_OFFSET 0x0244 +#define mmSDMA7_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA7_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA7_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_SIZE 0x0247 +#define mmSDMA7_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA7_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA7_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC3_DOORBELL 0x024a +#define mmSDMA7_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC3_STATUS 0x0260 +#define mmSDMA7_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA7_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC3_WATERMARK 0x0262 +#define mmSDMA7_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA7_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA7_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA7_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA7_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC3_PREEMPT 0x0268 +#define mmSDMA7_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC3_DUMMY_REG 0x0269 +#define mmSDMA7_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA7_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA7_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA7_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA7_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA7_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA7_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA7_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA7_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA7_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA7_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA7_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA7_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_CNTL 0x0290 +#define mmSDMA7_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_BASE 0x0291 +#define mmSDMA7_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA7_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_RPTR 0x0293 +#define mmSDMA7_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA7_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_WPTR 0x0295 +#define mmSDMA7_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA7_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA7_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA7_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA7_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_CNTL 0x029a +#define mmSDMA7_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_RPTR 0x029b +#define mmSDMA7_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_OFFSET 0x029c +#define mmSDMA7_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_BASE_LO 0x029d +#define mmSDMA7_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_BASE_HI 0x029e +#define mmSDMA7_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_SIZE 0x029f +#define mmSDMA7_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA7_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA7_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC4_DOORBELL 0x02a2 +#define mmSDMA7_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC4_STATUS 0x02b8 +#define mmSDMA7_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA7_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC4_WATERMARK 0x02ba +#define mmSDMA7_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA7_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA7_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA7_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA7_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC4_PREEMPT 0x02c0 +#define mmSDMA7_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA7_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA7_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA7_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA7_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA7_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA7_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA7_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA7_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA7_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA7_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA7_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA7_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA7_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_CNTL 0x02e8 +#define mmSDMA7_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_BASE 0x02e9 +#define mmSDMA7_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA7_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_RPTR 0x02eb +#define mmSDMA7_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA7_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_WPTR 0x02ed +#define mmSDMA7_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA7_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA7_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA7_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA7_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_CNTL 0x02f2 +#define mmSDMA7_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_RPTR 0x02f3 +#define mmSDMA7_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA7_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA7_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA7_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_SIZE 0x02f7 +#define mmSDMA7_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA7_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA7_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC5_DOORBELL 0x02fa +#define mmSDMA7_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC5_STATUS 0x0310 +#define mmSDMA7_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA7_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC5_WATERMARK 0x0312 +#define mmSDMA7_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA7_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA7_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA7_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA7_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC5_PREEMPT 0x0318 +#define mmSDMA7_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC5_DUMMY_REG 0x0319 +#define mmSDMA7_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA7_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA7_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA7_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA7_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA7_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA7_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA7_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA7_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA7_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA7_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA7_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA7_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_CNTL 0x0340 +#define mmSDMA7_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_BASE 0x0341 +#define mmSDMA7_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA7_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_RPTR 0x0343 +#define mmSDMA7_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA7_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_WPTR 0x0345 +#define mmSDMA7_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA7_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA7_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA7_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA7_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_CNTL 0x034a +#define mmSDMA7_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_RPTR 0x034b +#define mmSDMA7_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_OFFSET 0x034c +#define mmSDMA7_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_BASE_LO 0x034d +#define mmSDMA7_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_BASE_HI 0x034e +#define mmSDMA7_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_SIZE 0x034f +#define mmSDMA7_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA7_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA7_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC6_DOORBELL 0x0352 +#define mmSDMA7_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC6_STATUS 0x0368 +#define mmSDMA7_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA7_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC6_WATERMARK 0x036a +#define mmSDMA7_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA7_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA7_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA7_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA7_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC6_PREEMPT 0x0370 +#define mmSDMA7_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC6_DUMMY_REG 0x0371 +#define mmSDMA7_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA7_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA7_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA7_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA7_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA7_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA7_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA7_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA7_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA7_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA7_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA7_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA7_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_CNTL 0x0398 +#define mmSDMA7_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_BASE 0x0399 +#define mmSDMA7_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_BASE_HI 0x039a +#define mmSDMA7_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_RPTR 0x039b +#define mmSDMA7_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA7_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_WPTR 0x039d +#define mmSDMA7_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA7_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA7_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA7_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA7_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_CNTL 0x03a2 +#define mmSDMA7_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_RPTR 0x03a3 +#define mmSDMA7_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA7_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA7_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA7_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_SIZE 0x03a7 +#define mmSDMA7_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA7_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA7_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC7_DOORBELL 0x03aa +#define mmSDMA7_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC7_STATUS 0x03c0 +#define mmSDMA7_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA7_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC7_WATERMARK 0x03c2 +#define mmSDMA7_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA7_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA7_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA7_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA7_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC7_PREEMPT 0x03c8 +#define mmSDMA7_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA7_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA7_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA7_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA7_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA7_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA7_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA7_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA7_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA7_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA7_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA7_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA7_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA7_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h new file mode 100644 index 0000000..4b56d8c6 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma7_4_2_2_SH_MASK_HEADER +#define _sdma7_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma7_sdma7dec +//SDMA7_UCODE_ADDR +#define SDMA7_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA7_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA7_UCODE_DATA +#define SDMA7_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA7_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA7_VM_CNTL +#define SDMA7_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA7_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA7_VM_CTX_LO +#define SDMA7_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA7_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_VM_CTX_HI +#define SDMA7_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA7_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_ACTIVE_FCN_ID +#define SDMA7_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA7_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA7_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA7_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA7_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA7_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA7_VM_CTX_CNTL +#define SDMA7_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA7_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA7_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA7_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA7_VIRT_RESET_REQ +#define SDMA7_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA7_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA7_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA7_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA7_VF_ENABLE +#define SDMA7_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA7_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA7_CONTEXT_REG_TYPE0 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE__SHIFT 0x1 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_CNTL__SHIFT 0xa +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_RPTR__SHIFT 0xb +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_SIZE__SHIFT 0xf +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_DOORBELL__SHIFT 0x12 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_MASK 0x00000002L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_DOORBELL_MASK 0x00040000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA7_CONTEXT_REG_TYPE1 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_STATUS__SHIFT 0x8 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_WATERMARK__SHIFT 0xa +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA7_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_PREEMPT__SHIFT 0x10 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA7_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_STATUS_MASK 0x00000100L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_WATERMARK_MASK 0x00000400L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA7_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_PREEMPT_MASK 0x00010000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA7_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA7_CONTEXT_REG_TYPE2 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA7_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA7_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA7_CONTEXT_REG_TYPE3 +#define SDMA7_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA7_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA7_PUB_REG_TYPE0 +#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_ADDR__SHIFT 0x0 +#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_DATA__SHIFT 0x1 +#define SDMA7_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CNTL__SHIFT 0x4 +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_LO__SHIFT 0x5 +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_HI__SHIFT 0x6 +#define SDMA7_PUB_REG_TYPE0__SDMA7_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA7_PUB_REG_TYPE0__SDMA7_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA7_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA7_PUB_REG_TYPE0__SDMA7_MMHUB_CNTL__SHIFT 0x13 +#define SDMA7_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA7_PUB_REG_TYPE0__SDMA7_POWER_CNTL__SHIFT 0x1a +#define SDMA7_PUB_REG_TYPE0__SDMA7_CLK_CTRL__SHIFT 0x1b +#define SDMA7_PUB_REG_TYPE0__SDMA7_CNTL__SHIFT 0x1c +#define SDMA7_PUB_REG_TYPE0__SDMA7_CHICKEN_BITS__SHIFT 0x1d +#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_ADDR_MASK 0x00000001L +#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_DATA_MASK 0x00000002L +#define SDMA7_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CNTL_MASK 0x00000010L +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_LO_MASK 0x00000020L +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_HI_MASK 0x00000040L +#define SDMA7_PUB_REG_TYPE0__SDMA7_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA7_PUB_REG_TYPE0__SDMA7_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA7_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_MMHUB_CNTL_MASK 0x00080000L +#define SDMA7_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_POWER_CNTL_MASK 0x04000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CLK_CTRL_MASK 0x08000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CNTL_MASK 0x10000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CHICKEN_BITS_MASK 0x20000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA7_PUB_REG_TYPE1 +#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA7_PUB_REG_TYPE1__SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA7_PUB_REG_TYPE1__SDMA7_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA7_PUB_REG_TYPE1__SDMA7_PROGRAM__SHIFT 0x4 +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS_REG__SHIFT 0x5 +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS1_REG__SHIFT 0x6 +#define SDMA7_PUB_REG_TYPE1__SDMA7_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA7_PUB_REG_TYPE1__SDMA7_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA7_PUB_REG_TYPE1__SDMA7_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA7_PUB_REG_TYPE1__SDMA7_F32_CNTL__SHIFT 0xa +#define SDMA7_PUB_REG_TYPE1__SDMA7_FREEZE__SHIFT 0xb +#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA7_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_CONFIG__SHIFT 0x12 +#define SDMA7_PUB_REG_TYPE1__SDMA7_BA_THRESHOLD__SHIFT 0x13 +#define SDMA7_PUB_REG_TYPE1__SDMA7_ID__SHIFT 0x14 +#define SDMA7_PUB_REG_TYPE1__SDMA7_VERSION__SHIFT 0x15 +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER__SHIFT 0x16 +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS2_REG__SHIFT 0x18 +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_CNTL__SHIFT 0x1c +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA7_PUB_REG_TYPE1__SDMA7_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA7_PUB_REG_TYPE1__SDMA7_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA7_PUB_REG_TYPE1__SDMA7_PROGRAM_MASK 0x00000010L +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS_REG_MASK 0x00000020L +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS1_REG_MASK 0x00000040L +#define SDMA7_PUB_REG_TYPE1__SDMA7_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA7_PUB_REG_TYPE1__SDMA7_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA7_PUB_REG_TYPE1__SDMA7_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA7_PUB_REG_TYPE1__SDMA7_F32_CNTL_MASK 0x00000400L +#define SDMA7_PUB_REG_TYPE1__SDMA7_FREEZE_MASK 0x00000800L +#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA7_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_CONFIG_MASK 0x00040000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_BA_THRESHOLD_MASK 0x00080000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_ID_MASK 0x00100000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_VERSION_MASK 0x00200000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_MASK 0x00400000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS2_REG_MASK 0x01000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_CNTL_MASK 0x10000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA7_PUB_REG_TYPE2 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV0__SHIFT 0x0 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV1__SHIFT 0x1 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV2__SHIFT 0x2 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_PAGE__SHIFT 0x8 +#define SDMA7_PUB_REG_TYPE2__SDMA7_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA7_PUB_REG_TYPE2__SDMA7_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA7_PUB_REG_TYPE2__SDMA7_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA7_PUB_REG_TYPE2__SDMA7_STATUS3_REG__SHIFT 0xc +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA7_PUB_REG_TYPE2__SDMA7_ERROR_LOG__SHIFT 0x10 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA7_PUB_REG_TYPE2__SDMA7_F32_COUNTER__SHIFT 0x15 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UNBREAKABLE__SHIFT 0x16 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFMON_CNTL__SHIFT 0x17 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA7_PUB_REG_TYPE2__SDMA7_CRD_CNTL__SHIFT 0x1b +#define SDMA7_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA7_PUB_REG_TYPE2__SDMA7_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA7_PUB_REG_TYPE2__SDMA7_ULV_CNTL__SHIFT 0x1e +#define SDMA7_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV0_MASK 0x00000001L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV1_MASK 0x00000002L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV2_MASK 0x00000004L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_PAGE_MASK 0x00000100L +#define SDMA7_PUB_REG_TYPE2__SDMA7_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA7_PUB_REG_TYPE2__SDMA7_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA7_PUB_REG_TYPE2__SDMA7_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA7_PUB_REG_TYPE2__SDMA7_STATUS3_REG_MASK 0x00001000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_ERROR_LOG_MASK 0x00010000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_F32_COUNTER_MASK 0x00200000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UNBREAKABLE_MASK 0x00400000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFMON_CNTL_MASK 0x00800000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_CRD_CNTL_MASK 0x08000000L +#define SDMA7_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_ULV_CNTL_MASK 0x40000000L +#define SDMA7_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA7_PUB_REG_TYPE3 +#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA7_PUB_REG_TYPE3__SDMA7_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA7_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA7_PUB_REG_TYPE3__SDMA7_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA7_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA7_MMHUB_CNTL +#define SDMA7_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA7_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA7_CONTEXT_GROUP_BOUNDARY +#define SDMA7_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA7_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA7_POWER_CNTL +#define SDMA7_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA7_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA7_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA7_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA7_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA7_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA7_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA7_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA7_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA7_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA7_CLK_CTRL +#define SDMA7_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA7_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA7_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA7_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA7_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA7_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA7_CNTL +#define SDMA7_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA7_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA7_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA7_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA7_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA7_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA7_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA7_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA7_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA7_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA7_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA7_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA7_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA7_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA7_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA7_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA7_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA7_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA7_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA7_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA7_CHICKEN_BITS +#define SDMA7_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA7_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA7_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA7_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA7_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA7_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA7_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA7_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA7_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA7_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA7_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA7_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA7_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA7_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA7_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA7_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA7_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA7_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA7_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA7_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA7_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA7_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA7_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA7_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA7_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA7_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA7_GB_ADDR_CONFIG +#define SDMA7_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA7_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA7_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA7_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA7_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA7_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA7_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA7_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA7_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA7_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA7_GB_ADDR_CONFIG_READ +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA7_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA7_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA7_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA7_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA7_RB_RPTR_FETCH_HI +#define SDMA7_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA7_RB_RPTR_FETCH +#define SDMA7_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA7_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA7_IB_OFFSET_FETCH +#define SDMA7_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA7_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA7_PROGRAM +#define SDMA7_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA7_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA7_STATUS_REG +#define SDMA7_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA7_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA7_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA7_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA7_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA7_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA7_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA7_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA7_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA7_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA7_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA7_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA7_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA7_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA7_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA7_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA7_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA7_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA7_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA7_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA7_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA7_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA7_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA7_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA7_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA7_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA7_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA7_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA7_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA7_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA7_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA7_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA7_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA7_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA7_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA7_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA7_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA7_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA7_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA7_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA7_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA7_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA7_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA7_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA7_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA7_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA7_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA7_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA7_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA7_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA7_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA7_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA7_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA7_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA7_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA7_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA7_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA7_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA7_STATUS1_REG +#define SDMA7_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA7_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA7_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA7_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA7_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA7_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA7_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA7_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA7_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA7_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA7_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA7_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA7_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA7_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA7_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA7_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA7_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA7_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA7_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA7_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA7_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA7_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA7_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA7_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA7_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA7_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA7_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA7_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA7_RD_BURST_CNTL +#define SDMA7_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA7_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA7_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA7_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA7_HBM_PAGE_CONFIG +#define SDMA7_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA7_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA7_UCODE_CHECKSUM +#define SDMA7_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA7_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA7_F32_CNTL +#define SDMA7_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA7_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA7_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA7_F32_CNTL__STEP_MASK 0x00000002L +//SDMA7_FREEZE +#define SDMA7_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA7_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA7_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA7_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA7_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA7_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA7_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA7_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA7_PHASE0_QUANTUM +#define SDMA7_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA7_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA7_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA7_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA7_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA7_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA7_PHASE1_QUANTUM +#define SDMA7_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA7_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA7_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA7_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA7_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA7_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA7_EDC_CONFIG +#define SDMA7_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA7_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA7_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA7_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA7_BA_THRESHOLD +#define SDMA7_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA7_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA7_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA7_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA7_ID +#define SDMA7_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA7_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA7_VERSION +#define SDMA7_VERSION__MINVER__SHIFT 0x0 +#define SDMA7_VERSION__MAJVER__SHIFT 0x8 +#define SDMA7_VERSION__REV__SHIFT 0x10 +#define SDMA7_VERSION__MINVER_MASK 0x0000007FL +#define SDMA7_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA7_VERSION__REV_MASK 0x003F0000L +//SDMA7_EDC_COUNTER +#define SDMA7_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA7_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA7_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA7_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA7_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA7_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA7_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA7_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA7_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA7_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA7_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA7_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA7_EDC_COUNTER_CLEAR +#define SDMA7_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA7_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA7_STATUS2_REG +#define SDMA7_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA7_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA7_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA7_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA7_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA7_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA7_ATOMIC_CNTL +#define SDMA7_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA7_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA7_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA7_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA7_ATOMIC_PREOP_LO +#define SDMA7_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA7_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA7_ATOMIC_PREOP_HI +#define SDMA7_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA7_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA7_UTCL1_CNTL +#define SDMA7_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA7_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA7_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA7_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA7_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA7_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA7_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA7_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA7_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA7_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA7_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA7_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA7_UTCL1_WATERMK +#define SDMA7_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA7_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA7_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA7_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA7_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA7_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA7_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA7_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA7_UTCL1_RD_STATUS +#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA7_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA7_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA7_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA7_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA7_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA7_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA7_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA7_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA7_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA7_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA7_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA7_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA7_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA7_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA7_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA7_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA7_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA7_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA7_UTCL1_WR_STATUS +#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA7_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA7_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA7_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA7_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA7_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA7_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA7_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA7_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA7_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA7_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA7_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA7_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA7_UTCL1_INV0 +#define SDMA7_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA7_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA7_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA7_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA7_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA7_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA7_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA7_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA7_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA7_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA7_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA7_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA7_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA7_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA7_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA7_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA7_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA7_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA7_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA7_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA7_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA7_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA7_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA7_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA7_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA7_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA7_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA7_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA7_UTCL1_INV1 +#define SDMA7_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA7_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA7_UTCL1_INV2 +#define SDMA7_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA7_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA7_UTCL1_RD_XNACK0 +#define SDMA7_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA7_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA7_UTCL1_RD_XNACK1 +#define SDMA7_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA7_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA7_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA7_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA7_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA7_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA7_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA7_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA7_UTCL1_WR_XNACK0 +#define SDMA7_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA7_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA7_UTCL1_WR_XNACK1 +#define SDMA7_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA7_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA7_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA7_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA7_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA7_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA7_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA7_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA7_UTCL1_TIMEOUT +#define SDMA7_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA7_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA7_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA7_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA7_UTCL1_PAGE +#define SDMA7_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA7_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA7_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA7_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA7_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA7_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA7_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA7_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA7_POWER_CNTL_IDLE +#define SDMA7_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA7_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA7_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA7_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA7_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA7_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA7_RELAX_ORDERING_LUT +#define SDMA7_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA7_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA7_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA7_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA7_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA7_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA7_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA7_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA7_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA7_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA7_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA7_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA7_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA7_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA7_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA7_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA7_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA7_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA7_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA7_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA7_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA7_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA7_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA7_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA7_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA7_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA7_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA7_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA7_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA7_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA7_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA7_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA7_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA7_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA7_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA7_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA7_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA7_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA7_CHICKEN_BITS_2 +#define SDMA7_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA7_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA7_STATUS3_REG +#define SDMA7_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA7_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA7_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA7_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA7_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA7_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA7_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA7_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA7_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA7_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA7_PHYSICAL_ADDR_LO +#define SDMA7_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA7_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA7_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA7_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA7_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA7_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA7_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA7_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA7_PHYSICAL_ADDR_HI +#define SDMA7_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA7_PHASE2_QUANTUM +#define SDMA7_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA7_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA7_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA7_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA7_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA7_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA7_ERROR_LOG +#define SDMA7_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA7_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA7_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA7_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA7_PUB_DUMMY_REG0 +#define SDMA7_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA7_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA7_PUB_DUMMY_REG1 +#define SDMA7_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA7_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA7_PUB_DUMMY_REG2 +#define SDMA7_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA7_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA7_PUB_DUMMY_REG3 +#define SDMA7_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA7_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA7_F32_COUNTER +#define SDMA7_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA7_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA7_UNBREAKABLE +#define SDMA7_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA7_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA7_PERFMON_CNTL +#define SDMA7_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA7_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA7_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA7_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA7_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA7_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA7_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA7_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA7_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA7_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA7_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA7_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA7_PERFCOUNTER0_RESULT +#define SDMA7_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA7_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA7_PERFCOUNTER1_RESULT +#define SDMA7_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA7_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA7_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA7_CRD_CNTL +#define SDMA7_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA7_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA7_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA7_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA7_GPU_IOV_VIOLATION_LOG +#define SDMA7_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA7_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA7_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA7_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA7_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA7_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA7_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA7_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA7_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA7_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA7_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA7_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA7_ULV_CNTL +#define SDMA7_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA7_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA7_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA7_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA7_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA7_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA7_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA7_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA7_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA7_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA7_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA7_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA7_EA_DBIT_ADDR_DATA +#define SDMA7_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA7_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA7_EA_DBIT_ADDR_INDEX +#define SDMA7_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA7_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA7_GPU_IOV_VIOLATION_LOG2 +#define SDMA7_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA7_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA7_GFX_RB_CNTL +#define SDMA7_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_GFX_RB_BASE +#define SDMA7_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_BASE_HI +#define SDMA7_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_GFX_RB_RPTR +#define SDMA7_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_RPTR_HI +#define SDMA7_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_WPTR +#define SDMA7_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_WPTR_HI +#define SDMA7_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_WPTR_POLL_CNTL +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_GFX_RB_RPTR_ADDR_HI +#define SDMA7_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_RPTR_ADDR_LO +#define SDMA7_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_GFX_IB_CNTL +#define SDMA7_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_GFX_IB_RPTR +#define SDMA7_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_GFX_IB_OFFSET +#define SDMA7_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_GFX_IB_BASE_LO +#define SDMA7_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_GFX_IB_BASE_HI +#define SDMA7_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_GFX_IB_SIZE +#define SDMA7_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_GFX_SKIP_CNTL +#define SDMA7_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_GFX_CONTEXT_STATUS +#define SDMA7_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_GFX_DOORBELL +#define SDMA7_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_GFX_CONTEXT_CNTL +#define SDMA7_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA7_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA7_GFX_STATUS +#define SDMA7_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_GFX_DOORBELL_LOG +#define SDMA7_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_GFX_WATERMARK +#define SDMA7_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_GFX_DOORBELL_OFFSET +#define SDMA7_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_GFX_CSA_ADDR_LO +#define SDMA7_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_GFX_CSA_ADDR_HI +#define SDMA7_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_GFX_IB_SUB_REMAIN +#define SDMA7_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_GFX_PREEMPT +#define SDMA7_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_GFX_DUMMY_REG +#define SDMA7_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_GFX_RB_AQL_CNTL +#define SDMA7_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_GFX_MINOR_PTR_UPDATE +#define SDMA7_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_GFX_MIDCMD_DATA0 +#define SDMA7_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA1 +#define SDMA7_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA2 +#define SDMA7_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA3 +#define SDMA7_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA4 +#define SDMA7_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA5 +#define SDMA7_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA6 +#define SDMA7_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA7 +#define SDMA7_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA8 +#define SDMA7_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_CNTL +#define SDMA7_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_PAGE_RB_CNTL +#define SDMA7_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_PAGE_RB_BASE +#define SDMA7_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_BASE_HI +#define SDMA7_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_PAGE_RB_RPTR +#define SDMA7_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_RPTR_HI +#define SDMA7_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_WPTR +#define SDMA7_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_WPTR_HI +#define SDMA7_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_WPTR_POLL_CNTL +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_PAGE_RB_RPTR_ADDR_HI +#define SDMA7_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_RPTR_ADDR_LO +#define SDMA7_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_PAGE_IB_CNTL +#define SDMA7_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_PAGE_IB_RPTR +#define SDMA7_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_PAGE_IB_OFFSET +#define SDMA7_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_PAGE_IB_BASE_LO +#define SDMA7_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_PAGE_IB_BASE_HI +#define SDMA7_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_PAGE_IB_SIZE +#define SDMA7_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_PAGE_SKIP_CNTL +#define SDMA7_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_PAGE_CONTEXT_STATUS +#define SDMA7_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_PAGE_DOORBELL +#define SDMA7_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_PAGE_STATUS +#define SDMA7_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_PAGE_DOORBELL_LOG +#define SDMA7_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_PAGE_WATERMARK +#define SDMA7_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_PAGE_DOORBELL_OFFSET +#define SDMA7_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_PAGE_CSA_ADDR_LO +#define SDMA7_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_PAGE_CSA_ADDR_HI +#define SDMA7_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_PAGE_IB_SUB_REMAIN +#define SDMA7_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_PAGE_PREEMPT +#define SDMA7_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_PAGE_DUMMY_REG +#define SDMA7_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_PAGE_RB_AQL_CNTL +#define SDMA7_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_PAGE_MINOR_PTR_UPDATE +#define SDMA7_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_PAGE_MIDCMD_DATA0 +#define SDMA7_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA1 +#define SDMA7_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA2 +#define SDMA7_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA3 +#define SDMA7_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA4 +#define SDMA7_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA5 +#define SDMA7_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA6 +#define SDMA7_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA7 +#define SDMA7_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA8 +#define SDMA7_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_CNTL +#define SDMA7_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC0_RB_CNTL +#define SDMA7_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC0_RB_BASE +#define SDMA7_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_BASE_HI +#define SDMA7_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC0_RB_RPTR +#define SDMA7_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_RPTR_HI +#define SDMA7_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_WPTR +#define SDMA7_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_WPTR_HI +#define SDMA7_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_WPTR_POLL_CNTL +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC0_RB_RPTR_ADDR_HI +#define SDMA7_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_RPTR_ADDR_LO +#define SDMA7_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC0_IB_CNTL +#define SDMA7_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC0_IB_RPTR +#define SDMA7_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC0_IB_OFFSET +#define SDMA7_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC0_IB_BASE_LO +#define SDMA7_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC0_IB_BASE_HI +#define SDMA7_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC0_IB_SIZE +#define SDMA7_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC0_SKIP_CNTL +#define SDMA7_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC0_CONTEXT_STATUS +#define SDMA7_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC0_DOORBELL +#define SDMA7_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC0_STATUS +#define SDMA7_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC0_DOORBELL_LOG +#define SDMA7_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC0_WATERMARK +#define SDMA7_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC0_DOORBELL_OFFSET +#define SDMA7_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC0_CSA_ADDR_LO +#define SDMA7_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC0_CSA_ADDR_HI +#define SDMA7_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC0_IB_SUB_REMAIN +#define SDMA7_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC0_PREEMPT +#define SDMA7_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC0_DUMMY_REG +#define SDMA7_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC0_RB_AQL_CNTL +#define SDMA7_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC0_MINOR_PTR_UPDATE +#define SDMA7_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC0_MIDCMD_DATA0 +#define SDMA7_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA1 +#define SDMA7_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA2 +#define SDMA7_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA3 +#define SDMA7_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA4 +#define SDMA7_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA5 +#define SDMA7_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA6 +#define SDMA7_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA7 +#define SDMA7_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA8 +#define SDMA7_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_CNTL +#define SDMA7_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC1_RB_CNTL +#define SDMA7_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC1_RB_BASE +#define SDMA7_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_BASE_HI +#define SDMA7_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC1_RB_RPTR +#define SDMA7_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_RPTR_HI +#define SDMA7_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_WPTR +#define SDMA7_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_WPTR_HI +#define SDMA7_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_WPTR_POLL_CNTL +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC1_RB_RPTR_ADDR_HI +#define SDMA7_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_RPTR_ADDR_LO +#define SDMA7_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC1_IB_CNTL +#define SDMA7_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC1_IB_RPTR +#define SDMA7_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC1_IB_OFFSET +#define SDMA7_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC1_IB_BASE_LO +#define SDMA7_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC1_IB_BASE_HI +#define SDMA7_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC1_IB_SIZE +#define SDMA7_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC1_SKIP_CNTL +#define SDMA7_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC1_CONTEXT_STATUS +#define SDMA7_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC1_DOORBELL +#define SDMA7_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC1_STATUS +#define SDMA7_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC1_DOORBELL_LOG +#define SDMA7_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC1_WATERMARK +#define SDMA7_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC1_DOORBELL_OFFSET +#define SDMA7_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC1_CSA_ADDR_LO +#define SDMA7_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC1_CSA_ADDR_HI +#define SDMA7_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC1_IB_SUB_REMAIN +#define SDMA7_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC1_PREEMPT +#define SDMA7_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC1_DUMMY_REG +#define SDMA7_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC1_RB_AQL_CNTL +#define SDMA7_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC1_MINOR_PTR_UPDATE +#define SDMA7_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC1_MIDCMD_DATA0 +#define SDMA7_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA1 +#define SDMA7_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA2 +#define SDMA7_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA3 +#define SDMA7_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA4 +#define SDMA7_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA5 +#define SDMA7_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA6 +#define SDMA7_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA7 +#define SDMA7_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA8 +#define SDMA7_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_CNTL +#define SDMA7_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC2_RB_CNTL +#define SDMA7_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC2_RB_BASE +#define SDMA7_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_BASE_HI +#define SDMA7_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC2_RB_RPTR +#define SDMA7_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_RPTR_HI +#define SDMA7_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_WPTR +#define SDMA7_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_WPTR_HI +#define SDMA7_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_WPTR_POLL_CNTL +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC2_RB_RPTR_ADDR_HI +#define SDMA7_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_RPTR_ADDR_LO +#define SDMA7_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC2_IB_CNTL +#define SDMA7_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC2_IB_RPTR +#define SDMA7_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC2_IB_OFFSET +#define SDMA7_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC2_IB_BASE_LO +#define SDMA7_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC2_IB_BASE_HI +#define SDMA7_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC2_IB_SIZE +#define SDMA7_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC2_SKIP_CNTL +#define SDMA7_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC2_CONTEXT_STATUS +#define SDMA7_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC2_DOORBELL +#define SDMA7_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC2_STATUS +#define SDMA7_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC2_DOORBELL_LOG +#define SDMA7_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC2_WATERMARK +#define SDMA7_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC2_DOORBELL_OFFSET +#define SDMA7_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC2_CSA_ADDR_LO +#define SDMA7_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC2_CSA_ADDR_HI +#define SDMA7_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC2_IB_SUB_REMAIN +#define SDMA7_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC2_PREEMPT +#define SDMA7_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC2_DUMMY_REG +#define SDMA7_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC2_RB_AQL_CNTL +#define SDMA7_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC2_MINOR_PTR_UPDATE +#define SDMA7_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC2_MIDCMD_DATA0 +#define SDMA7_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA1 +#define SDMA7_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA2 +#define SDMA7_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA3 +#define SDMA7_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA4 +#define SDMA7_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA5 +#define SDMA7_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA6 +#define SDMA7_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA7 +#define SDMA7_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA8 +#define SDMA7_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_CNTL +#define SDMA7_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC3_RB_CNTL +#define SDMA7_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC3_RB_BASE +#define SDMA7_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_BASE_HI +#define SDMA7_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC3_RB_RPTR +#define SDMA7_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_RPTR_HI +#define SDMA7_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_WPTR +#define SDMA7_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_WPTR_HI +#define SDMA7_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_WPTR_POLL_CNTL +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC3_RB_RPTR_ADDR_HI +#define SDMA7_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_RPTR_ADDR_LO +#define SDMA7_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC3_IB_CNTL +#define SDMA7_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC3_IB_RPTR +#define SDMA7_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC3_IB_OFFSET +#define SDMA7_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC3_IB_BASE_LO +#define SDMA7_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC3_IB_BASE_HI +#define SDMA7_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC3_IB_SIZE +#define SDMA7_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC3_SKIP_CNTL +#define SDMA7_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC3_CONTEXT_STATUS +#define SDMA7_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC3_DOORBELL +#define SDMA7_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC3_STATUS +#define SDMA7_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC3_DOORBELL_LOG +#define SDMA7_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC3_WATERMARK +#define SDMA7_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC3_DOORBELL_OFFSET +#define SDMA7_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC3_CSA_ADDR_LO +#define SDMA7_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC3_CSA_ADDR_HI +#define SDMA7_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC3_IB_SUB_REMAIN +#define SDMA7_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC3_PREEMPT +#define SDMA7_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC3_DUMMY_REG +#define SDMA7_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC3_RB_AQL_CNTL +#define SDMA7_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC3_MINOR_PTR_UPDATE +#define SDMA7_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC3_MIDCMD_DATA0 +#define SDMA7_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA1 +#define SDMA7_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA2 +#define SDMA7_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA3 +#define SDMA7_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA4 +#define SDMA7_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA5 +#define SDMA7_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA6 +#define SDMA7_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA7 +#define SDMA7_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA8 +#define SDMA7_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_CNTL +#define SDMA7_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC4_RB_CNTL +#define SDMA7_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC4_RB_BASE +#define SDMA7_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_BASE_HI +#define SDMA7_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC4_RB_RPTR +#define SDMA7_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_RPTR_HI +#define SDMA7_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_WPTR +#define SDMA7_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_WPTR_HI +#define SDMA7_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_WPTR_POLL_CNTL +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC4_RB_RPTR_ADDR_HI +#define SDMA7_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_RPTR_ADDR_LO +#define SDMA7_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC4_IB_CNTL +#define SDMA7_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC4_IB_RPTR +#define SDMA7_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC4_IB_OFFSET +#define SDMA7_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC4_IB_BASE_LO +#define SDMA7_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC4_IB_BASE_HI +#define SDMA7_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC4_IB_SIZE +#define SDMA7_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC4_SKIP_CNTL +#define SDMA7_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC4_CONTEXT_STATUS +#define SDMA7_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC4_DOORBELL +#define SDMA7_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC4_STATUS +#define SDMA7_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC4_DOORBELL_LOG +#define SDMA7_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC4_WATERMARK +#define SDMA7_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC4_DOORBELL_OFFSET +#define SDMA7_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC4_CSA_ADDR_LO +#define SDMA7_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC4_CSA_ADDR_HI +#define SDMA7_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC4_IB_SUB_REMAIN +#define SDMA7_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC4_PREEMPT +#define SDMA7_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC4_DUMMY_REG +#define SDMA7_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC4_RB_AQL_CNTL +#define SDMA7_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC4_MINOR_PTR_UPDATE +#define SDMA7_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC4_MIDCMD_DATA0 +#define SDMA7_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA1 +#define SDMA7_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA2 +#define SDMA7_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA3 +#define SDMA7_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA4 +#define SDMA7_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA5 +#define SDMA7_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA6 +#define SDMA7_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA7 +#define SDMA7_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA8 +#define SDMA7_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_CNTL +#define SDMA7_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC5_RB_CNTL +#define SDMA7_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC5_RB_BASE +#define SDMA7_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_BASE_HI +#define SDMA7_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC5_RB_RPTR +#define SDMA7_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_RPTR_HI +#define SDMA7_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_WPTR +#define SDMA7_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_WPTR_HI +#define SDMA7_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_WPTR_POLL_CNTL +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC5_RB_RPTR_ADDR_HI +#define SDMA7_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_RPTR_ADDR_LO +#define SDMA7_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC5_IB_CNTL +#define SDMA7_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC5_IB_RPTR +#define SDMA7_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC5_IB_OFFSET +#define SDMA7_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC5_IB_BASE_LO +#define SDMA7_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC5_IB_BASE_HI +#define SDMA7_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC5_IB_SIZE +#define SDMA7_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC5_SKIP_CNTL +#define SDMA7_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC5_CONTEXT_STATUS +#define SDMA7_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC5_DOORBELL +#define SDMA7_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC5_STATUS +#define SDMA7_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC5_DOORBELL_LOG +#define SDMA7_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC5_WATERMARK +#define SDMA7_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC5_DOORBELL_OFFSET +#define SDMA7_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC5_CSA_ADDR_LO +#define SDMA7_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC5_CSA_ADDR_HI +#define SDMA7_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC5_IB_SUB_REMAIN +#define SDMA7_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC5_PREEMPT +#define SDMA7_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC5_DUMMY_REG +#define SDMA7_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC5_RB_AQL_CNTL +#define SDMA7_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC5_MINOR_PTR_UPDATE +#define SDMA7_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC5_MIDCMD_DATA0 +#define SDMA7_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA1 +#define SDMA7_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA2 +#define SDMA7_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA3 +#define SDMA7_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA4 +#define SDMA7_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA5 +#define SDMA7_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA6 +#define SDMA7_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA7 +#define SDMA7_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA8 +#define SDMA7_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_CNTL +#define SDMA7_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC6_RB_CNTL +#define SDMA7_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC6_RB_BASE +#define SDMA7_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_BASE_HI +#define SDMA7_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC6_RB_RPTR +#define SDMA7_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_RPTR_HI +#define SDMA7_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_WPTR +#define SDMA7_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_WPTR_HI +#define SDMA7_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_WPTR_POLL_CNTL +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC6_RB_RPTR_ADDR_HI +#define SDMA7_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_RPTR_ADDR_LO +#define SDMA7_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC6_IB_CNTL +#define SDMA7_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC6_IB_RPTR +#define SDMA7_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC6_IB_OFFSET +#define SDMA7_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC6_IB_BASE_LO +#define SDMA7_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC6_IB_BASE_HI +#define SDMA7_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC6_IB_SIZE +#define SDMA7_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC6_SKIP_CNTL +#define SDMA7_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC6_CONTEXT_STATUS +#define SDMA7_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC6_DOORBELL +#define SDMA7_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC6_STATUS +#define SDMA7_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC6_DOORBELL_LOG +#define SDMA7_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC6_WATERMARK +#define SDMA7_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC6_DOORBELL_OFFSET +#define SDMA7_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC6_CSA_ADDR_LO +#define SDMA7_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC6_CSA_ADDR_HI +#define SDMA7_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC6_IB_SUB_REMAIN +#define SDMA7_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC6_PREEMPT +#define SDMA7_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC6_DUMMY_REG +#define SDMA7_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC6_RB_AQL_CNTL +#define SDMA7_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC6_MINOR_PTR_UPDATE +#define SDMA7_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC6_MIDCMD_DATA0 +#define SDMA7_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA1 +#define SDMA7_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA2 +#define SDMA7_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA3 +#define SDMA7_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA4 +#define SDMA7_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA5 +#define SDMA7_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA6 +#define SDMA7_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA7 +#define SDMA7_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA8 +#define SDMA7_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_CNTL +#define SDMA7_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC7_RB_CNTL +#define SDMA7_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC7_RB_BASE +#define SDMA7_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_BASE_HI +#define SDMA7_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC7_RB_RPTR +#define SDMA7_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_RPTR_HI +#define SDMA7_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_WPTR +#define SDMA7_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_WPTR_HI +#define SDMA7_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_WPTR_POLL_CNTL +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC7_RB_RPTR_ADDR_HI +#define SDMA7_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_RPTR_ADDR_LO +#define SDMA7_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC7_IB_CNTL +#define SDMA7_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC7_IB_RPTR +#define SDMA7_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC7_IB_OFFSET +#define SDMA7_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC7_IB_BASE_LO +#define SDMA7_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC7_IB_BASE_HI +#define SDMA7_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC7_IB_SIZE +#define SDMA7_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC7_SKIP_CNTL +#define SDMA7_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC7_CONTEXT_STATUS +#define SDMA7_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC7_DOORBELL +#define SDMA7_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC7_STATUS +#define SDMA7_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC7_DOORBELL_LOG +#define SDMA7_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC7_WATERMARK +#define SDMA7_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC7_DOORBELL_OFFSET +#define SDMA7_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC7_CSA_ADDR_LO +#define SDMA7_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC7_CSA_ADDR_HI +#define SDMA7_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC7_IB_SUB_REMAIN +#define SDMA7_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC7_PREEMPT +#define SDMA7_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC7_DUMMY_REG +#define SDMA7_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC7_RB_AQL_CNTL +#define SDMA7_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC7_MINOR_PTR_UPDATE +#define SDMA7_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC7_MIDCMD_DATA0 +#define SDMA7_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA1 +#define SDMA7_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA2 +#define SDMA7_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA3 +#define SDMA7_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA4 +#define SDMA7_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA5 +#define SDMA7_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA6 +#define SDMA7_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA7 +#define SDMA7_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA8 +#define SDMA7_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_CNTL +#define SDMA7_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif -- 2.7.4