From 4f14153494fe766b061dfec3eda6ed61d6156adb Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Sat, 20 Jan 2018 07:50:57 +0000
Subject: [PATCH] [X86] Add test cases for failures to use movzx due to various
 issues with demanded bits.

D42265 and D42313 should help with some of these.

llvm-svn: 323030
---
 llvm/test/CodeGen/X86/zext-demanded.ll | 108 +++++++++++++++++++++++++++++++++
 1 file changed, 108 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/zext-demanded.ll

diff --git a/llvm/test/CodeGen/X86/zext-demanded.ll b/llvm/test/CodeGen/X86/zext-demanded.ll
new file mode 100644
index 0000000..e142c6d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/zext-demanded.ll
@@ -0,0 +1,108 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+; Various tests for ands that should be implemented with movzx, but aren't due
+; demanded bits shortcomings.
+
+; The backend will insert a zext to promote the shift to i32.
+; TODO: we should be able to use movzx here.
+define i16 @test1(i16 %x) {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andl $65534, %edi # imm = 0xFFFE
+; CHECK-NEXT:    shrl %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %y = lshr i16 %x, 1
+  ret i16 %y
+}
+
+; TODO: we should be able to use movzx here.
+define i32 @test2(i32 %x) {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andl $65534, %edi # imm = 0xFFFE
+; CHECK-NEXT:    shrl %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %y = and i32 %x, 65535
+  %z = lshr i32 %y, 1
+  ret i32 %z
+}
+
+; TODO: We need to stop moving the and across the shift to get a movzx
+define i32 @test3(i32 %x) {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrl %edi
+; CHECK-NEXT:    andl $127, %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %y = and i32 %x, 255
+  %z = lshr i32 %y, 1
+  ret i32 %z
+}
+
+; TODO: We need to stop moving the and across the shift to get a movzx
+define i16 @test4(i16 %x) {
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrl %edi
+; CHECK-NEXT:    andl $127, %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %y = and i16 %x, 255
+  %z = lshr i16 %y, 1
+  ret i16 %z
+}
+
+; TODO: We need to stop moving the and across the shift to get a movzx
+define i16 @test5(i16 %x) {
+; CHECK-LABEL: test5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrl $9, %edi
+; CHECK-NEXT:    andl $127, %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %y = lshr i16 %x, 9
+  ret i16 %y
+}
+
+; TODO: We need to stop moving the and across the shift to get a movzx
+define i32 @test6(i32 %x) {
+; CHECK-LABEL: test6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrl $9, %edi
+; CHECK-NEXT:    andl $127, %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %y = and i32 %x, 65535
+  %z = lshr i32 %y, 9
+  ret i32 %z
+}
+
+; TODO: We could turn this and into a zero extend.
+define i32 @test7(i32 %x) {
+; CHECK-LABEL: test7:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def %edi killed %edi def %rdi
+; CHECK-NEXT:    andl $65534, %edi # imm = 0xFFFE
+; CHECK-NEXT:    leal 1(%rdi), %eax
+; CHECK-NEXT:    retq
+  %y = and i32 %x, 65534
+  %z = or i32 %y, 1
+  ret i32 %z
+}
+
+; We actually get a movzx on this one, but only because we canonicalize the and
+; after the or before SimplifyDemandedBits messes it up.
+define i32 @test8(i32 %x) {
+; CHECK-LABEL: test8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    orl $1, %edi
+; CHECK-NEXT:    movzwl %di, %eax
+; CHECK-NEXT:    retq
+  %y = and i32 %x, 65535
+  %z = or i32 %y, 1
+  ret i32 %z
+}
-- 
2.7.4