From 4ea611bca02c4e5ff783e73476d7b8f63766696e Mon Sep 17 00:00:00 2001
From: Georg Lehmann <dadschoorse@gmail.com>
Date: Tue, 26 Sep 2023 17:13:12 +0200
Subject: [PATCH] aco: fix p_extract with v1 dst and s1 operand

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: f14023666ca ("aco: Allow p_extract to have different definition and operand sizes.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25403>
---
 src/amd/compiler/aco_lower_to_hw_instr.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/compiler/aco_lower_to_hw_instr.cpp b/src/amd/compiler/aco_lower_to_hw_instr.cpp
index ba49e38..a8d7e3b 100644
--- a/src/amd/compiler/aco_lower_to_hw_instr.cpp
+++ b/src/amd/compiler/aco_lower_to_hw_instr.cpp
@@ -2615,7 +2615,7 @@ lower_to_hw_instr(Program* program)
                      bld.sop2(signext ? aco_opcode::s_bfe_i32 : aco_opcode::s_bfe_u32, dst,
                               bld.def(s1, scc), op, Operand::c32((bits << 16) | offset));
                   }
-               } else if ((dst.regClass() == v1 && op.regClass() == v1) ||
+               } else if ((dst.regClass() == v1 && op.physReg().byte() == 0) ||
                           ctx.program->gfx_level <= GFX7) {
                   assert(op.physReg().byte() == 0 && dst.physReg().byte() == 0);
                   if (offset == (32 - bits) && op.regClass() != s1) {
-- 
2.7.4