From 4e52efcc4311a1985fb53b41ee123f6583c9e404 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Thu, 12 May 2022 17:57:24 -0500 Subject: [PATCH] radv: Use VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT for render loops This commit fixes dEQP-VK.rasterization.rasterization_order_attachment_access.format on GFX9 because changing the layout for Vulkan feedback loops will trigger a fast-clear eliminate. Though, the root cause is unrelated to that and it's because the CMASK/FMASK initialization on GFX9 is currently broken for TC-compatible images (there is a TODO somewhere). Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/ci/radv-raven-aco-fails.txt | 12 ---- src/amd/ci/radv-renoir-aco-fails.txt | 12 ---- src/amd/ci/radv-vega10-aco-fails.txt | 12 ---- src/amd/vulkan/radv_cmd_buffer.c | 109 ++++++++++++++-------------------- src/amd/vulkan/radv_image.c | 14 ++--- src/amd/vulkan/radv_meta_clear.c | 36 ++++++----- src/amd/vulkan/radv_meta_copy.c | 12 ++-- src/amd/vulkan/radv_meta_resolve.c | 14 ++--- src/amd/vulkan/radv_meta_resolve_cs.c | 6 +- src/amd/vulkan/radv_pass.c | 9 +-- src/amd/vulkan/radv_private.h | 10 +--- 11 files changed, 93 insertions(+), 153 deletions(-) diff --git a/src/amd/ci/radv-raven-aco-fails.txt b/src/amd/ci/radv-raven-aco-fails.txt index c4205cd..01491c5 100644 --- a/src/amd/ci/radv-raven-aco-fails.txt +++ b/src/amd/ci/radv-raven-aco-fails.txt @@ -1,17 +1,5 @@ # The following are a guess, based on Renoir dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_4_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_4_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_4_samples_8.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_8_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_8_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_8_samples_8.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_4_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_4_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_4_samples_8.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_8_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_8_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_8_samples_8.multi_draw_barriers,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail diff --git a/src/amd/ci/radv-renoir-aco-fails.txt b/src/amd/ci/radv-renoir-aco-fails.txt index d465a85..ab037b2 100644 --- a/src/amd/ci/radv-renoir-aco-fails.txt +++ b/src/amd/ci/radv-renoir-aco-fails.txt @@ -19,18 +19,6 @@ dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_r dEQP-VK.dynamic_rendering.basic.2_secondary_2_primary_cmdbuffers_resuming,Fail dEQP-VK.dynamic_rendering.basic.2_secondary_cmdbuffers_resuming,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_4_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_4_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_4_samples_8.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_8_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_8_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_8_samples_8.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_4_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_4_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_4_samples_8.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_8_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_8_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_8_samples_8.multi_draw_barriers,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail diff --git a/src/amd/ci/radv-vega10-aco-fails.txt b/src/amd/ci/radv-vega10-aco-fails.txt index 0ef50ee..3ac2afa 100644 --- a/src/amd/ci/radv-vega10-aco-fails.txt +++ b/src/amd/ci/radv-vega10-aco-fails.txt @@ -19,18 +19,6 @@ dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_r dEQP-VK.dynamic_rendering.basic.2_secondary_2_primary_cmdbuffers_resuming,Fail dEQP-VK.dynamic_rendering.basic.2_secondary_cmdbuffers_resuming,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_4_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_4_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_4_samples_8.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_8_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_8_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_float.attachments_8_samples_8.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_4_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_4_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_4_samples_8.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_8_samples_2.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_8_samples_4.multi_draw_barriers,Fail -dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.attachments_8_samples_8.multi_draw_barriers,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 2b19247..e821577 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -36,6 +36,7 @@ #include "vk_util.h" #include "vk_enum_defines.h" #include "vk_common_entrypoints.h" +#include "vk_render_pass.h" #include "ac_debug.h" #include "ac_shader_args.h" @@ -55,10 +56,10 @@ enum { }; static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, VkImageLayout src_layout, - bool src_render_loop, VkImageLayout dst_layout, - bool dst_render_loop, uint32_t src_family_index, - uint32_t dst_family_index, const VkImageSubresourceRange *range, + struct radv_image *image, + VkImageLayout src_layout, VkImageLayout dst_layout, + uint32_t src_family_index, uint32_t dst_family_index, + const VkImageSubresourceRange *range, struct radv_sample_locations_state *sample_locs); static void radv_set_rt_stack_size(struct radv_cmd_buffer *cmd_buffer, uint32_t size); @@ -1866,7 +1867,7 @@ radv_emit_color_write_enable(struct radv_cmd_buffer *cmd_buffer) static void radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, struct radv_color_buffer_info *cb, struct radv_image_view *iview, - VkImageLayout layout, bool in_render_loop) + VkImageLayout layout) { bool is_vi = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX8; uint32_t cb_fdcc_control = cb->cb_dcc_control; @@ -1874,7 +1875,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, struct radv_image *image = iview->image; if (!radv_layout_dcc_compressed( - cmd_buffer->device, image, iview->vk.base_mip_level, layout, in_render_loop, + cmd_buffer->device, image, iview->vk.base_mip_level, layout, radv_image_queue_family_mask(image, cmd_buffer->qf, cmd_buffer->qf))) { if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) { @@ -1997,7 +1998,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, static void radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_info *ds, const struct radv_image_view *iview, VkImageLayout layout, - bool in_render_loop, bool requires_cond_exec) + bool requires_cond_exec) { const struct radv_image *image = iview->image; uint32_t db_z_info = ds->db_z_info; @@ -2008,7 +2009,7 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_ return; if (!radv_layout_is_htile_compressed( - cmd_buffer->device, image, layout, in_render_loop, + cmd_buffer->device, image, layout, radv_image_queue_family_mask(image, cmd_buffer->qf, cmd_buffer->qf))) { db_z_info &= C_028040_TILE_SURFACE_ENABLE; @@ -2041,7 +2042,7 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_ static void radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_info *ds, - struct radv_image_view *iview, VkImageLayout layout, bool in_render_loop) + struct radv_image_view *iview, VkImageLayout layout) { const struct radv_image *image = iview->image; uint32_t db_z_info = ds->db_z_info; @@ -2049,7 +2050,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_ uint32_t db_htile_surface = ds->db_htile_surface; if (!radv_layout_is_htile_compressed( - cmd_buffer->device, image, layout, in_render_loop, + cmd_buffer->device, image, layout, radv_image_queue_family_mask(image, cmd_buffer->qf, cmd_buffer->qf))) { db_z_info &= C_028040_TILE_SURFACE_ENABLE; @@ -2128,7 +2129,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_ } /* Update the ZRANGE_PRECISION value for the TC-compat bug. */ - radv_update_zrange_precision(cmd_buffer, ds, iview, layout, in_render_loop, true); + radv_update_zrange_precision(cmd_buffer, ds, iview, layout, true); radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, ds->pa_su_poly_offset_db_fmt_cntl); @@ -2174,10 +2175,9 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer, */ if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && ds_clear_value.depth == 0.0) { VkImageLayout layout = subpass->depth_stencil_attachment->layout; - bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop; radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds, iview, - layout, in_render_loop, false); + layout, false); } cmd_buffer->state.context_roll_without_scissor_emitted = true; @@ -2650,7 +2650,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) int idx = subpass->color_attachments[i].attachment; struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview; VkImageLayout layout = subpass->color_attachments[i].layout; - bool in_render_loop = subpass->color_attachments[i].in_render_loop; radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->image->bindings[0].bo); @@ -2668,8 +2667,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) iview->image->bindings[plane_id].bo); } - radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout, - in_render_loop); + radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout); radv_load_color_clear_metadata(cmd_buffer, iview, i); @@ -2689,16 +2687,14 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) if (subpass->depth_stencil_attachment) { int idx = subpass->depth_stencil_attachment->attachment; VkImageLayout layout = subpass->depth_stencil_attachment->layout; - bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop; struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview; radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->image->bindings[0].bo); - radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, - in_render_loop); + radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout); if (radv_layout_is_htile_compressed( - cmd_buffer->device, iview->image, layout, in_render_loop, + cmd_buffer->device, iview->image, layout, radv_image_queue_family_mask(iview->image, cmd_buffer->qf, cmd_buffer->qf))) { /* Only load the depth/stencil fast clear values when @@ -2737,7 +2733,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, htile_buffer->bo); - radv_emit_fb_ds_state(cmd_buffer, &ds, &iview, layout, false); + radv_emit_fb_ds_state(cmd_buffer, &ds, &iview, layout); radv_image_view_finish(&iview); } else { @@ -4539,25 +4535,21 @@ radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer, range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT; radv_handle_image_transition(cmd_buffer, view->image, cmd_buffer->state.attachments[idx].current_layout, - cmd_buffer->state.attachments[idx].current_in_render_loop, - att.layout, att.in_render_loop, 0, 0, &range, sample_locs); + att.layout, 0, 0, &range, sample_locs); /* Stencil-only transitions. */ range.aspectMask = VK_IMAGE_ASPECT_STENCIL_BIT; radv_handle_image_transition( cmd_buffer, view->image, cmd_buffer->state.attachments[idx].current_stencil_layout, - cmd_buffer->state.attachments[idx].current_in_render_loop, att.stencil_layout, - att.in_render_loop, 0, 0, &range, sample_locs); + att.stencil_layout, 0, 0, &range, sample_locs); } else { radv_handle_image_transition(cmd_buffer, view->image, cmd_buffer->state.attachments[idx].current_layout, - cmd_buffer->state.attachments[idx].current_in_render_loop, - att.layout, att.in_render_loop, 0, 0, &range, sample_locs); + att.layout, 0, 0, &range, sample_locs); } cmd_buffer->state.attachments[idx].current_layout = att.layout; cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout; - cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop; } void @@ -4699,7 +4691,6 @@ radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer, struct radv } state->attachments[i].current_layout = att->initial_layout; - state->attachments[i].current_in_render_loop = false; state->attachments[i].current_stencil_layout = att->stencil_initial_layout; state->attachments[i].sample_location.count = 0; @@ -9138,8 +9129,7 @@ radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, - VkImageLayout src_layout, bool src_render_loop, - VkImageLayout dst_layout, bool dst_render_loop, + VkImageLayout src_layout, VkImageLayout dst_layout, unsigned src_queue_mask, unsigned dst_queue_mask, const VkImageSubresourceRange *range, struct radv_sample_locations_state *sample_locs) @@ -9151,15 +9141,11 @@ radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { radv_initialize_htile(cmd_buffer, image, range); - } else if (!radv_layout_is_htile_compressed(device, image, src_layout, src_render_loop, - src_queue_mask) && - radv_layout_is_htile_compressed(device, image, dst_layout, dst_render_loop, - dst_queue_mask)) { + } else if (!radv_layout_is_htile_compressed(device, image, src_layout, src_queue_mask) && + radv_layout_is_htile_compressed(device, image, dst_layout, dst_queue_mask)) { radv_initialize_htile(cmd_buffer, image, range); - } else if (radv_layout_is_htile_compressed(device, image, src_layout, src_render_loop, - src_queue_mask) && - !radv_layout_is_htile_compressed(device, image, dst_layout, dst_render_loop, - dst_queue_mask)) { + } else if (radv_layout_is_htile_compressed(device, image, src_layout, src_queue_mask) && + !radv_layout_is_htile_compressed(device, image, dst_layout, dst_queue_mask)) { cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB | RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; @@ -9245,8 +9231,7 @@ radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, */ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, - VkImageLayout src_layout, bool src_render_loop, - VkImageLayout dst_layout, bool dst_render_loop, + VkImageLayout src_layout, VkImageLayout dst_layout, unsigned src_queue_mask, unsigned dst_queue_mask, const VkImageSubresourceRange *range) { @@ -9266,7 +9251,7 @@ radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i if (radv_image_is_tc_compat_cmask(image) || (radv_image_has_fmask(image) && radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel, dst_layout, - dst_render_loop, dst_queue_mask))) { + dst_queue_mask))) { value = 0xccccccccu; } else { value = 0xffffffffu; @@ -9289,7 +9274,7 @@ radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i uint32_t value = 0xffffffffu; /* Fully expanded mode. */ if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel, - dst_layout, dst_render_loop, dst_queue_mask)) { + dst_layout, dst_queue_mask)) { value = 0u; } @@ -9332,8 +9317,7 @@ radv_image_need_retile(const struct radv_image *image) */ static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, - VkImageLayout src_layout, bool src_render_loop, - VkImageLayout dst_layout, bool dst_render_loop, + VkImageLayout src_layout, VkImageLayout dst_layout, unsigned src_queue_mask, unsigned dst_queue_mask, const VkImageSubresourceRange *range) { @@ -9344,8 +9328,8 @@ radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra return; if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { - radv_init_color_image_metadata(cmd_buffer, image, src_layout, src_render_loop, dst_layout, - dst_render_loop, src_queue_mask, dst_queue_mask, range); + radv_init_color_image_metadata(cmd_buffer, image, src_layout, dst_layout, + src_queue_mask, dst_queue_mask, range); if (radv_image_need_retile(image)) radv_retile_transition(cmd_buffer, image, src_layout, dst_layout, dst_queue_mask); @@ -9356,15 +9340,15 @@ radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) { cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, range, 0xffffffffu); } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel, - src_layout, src_render_loop, src_queue_mask) && + src_layout, src_queue_mask) && !radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel, - dst_layout, dst_render_loop, dst_queue_mask)) { + dst_layout, dst_queue_mask)) { radv_decompress_dcc(cmd_buffer, image, range); dcc_decompressed = true; } else if (radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel, - src_layout, src_render_loop, src_queue_mask) && + src_layout, src_queue_mask) && !radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel, - dst_layout, dst_render_loop, dst_queue_mask)) { + dst_layout, dst_queue_mask)) { radv_fast_clear_flush_image_inplace(cmd_buffer, image, range); fast_clear_flushed = true; } @@ -9373,9 +9357,9 @@ radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra radv_retile_transition(cmd_buffer, image, src_layout, dst_layout, dst_queue_mask); } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) { if (radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel, - src_layout, src_render_loop, src_queue_mask) && + src_layout, src_queue_mask) && !radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel, - dst_layout, dst_render_loop, dst_queue_mask)) { + dst_layout, dst_queue_mask)) { radv_fast_clear_flush_image_inplace(cmd_buffer, image, range); fast_clear_flushed = true; } @@ -9411,9 +9395,9 @@ radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, - VkImageLayout src_layout, bool src_render_loop, - VkImageLayout dst_layout, bool dst_render_loop, uint32_t src_family_index, - uint32_t dst_family_index, const VkImageSubresourceRange *range, + VkImageLayout src_layout, VkImageLayout dst_layout, + uint32_t src_family_index, uint32_t dst_family_index, + const VkImageSubresourceRange *range, struct radv_sample_locations_state *sample_locs) { enum radv_queue_family src_qf = vk_queue_to_radv(cmd_buffer->device->physical_device, src_family_index); @@ -9442,16 +9426,15 @@ radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_ima unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_qf, cmd_buffer->qf); - if (src_layout == dst_layout && src_render_loop == dst_render_loop && src_queue_mask == dst_queue_mask) + if (src_layout == dst_layout && src_queue_mask == dst_queue_mask) return; if (vk_format_has_depth(image->vk.format)) { - radv_handle_depth_image_transition(cmd_buffer, image, src_layout, src_render_loop, dst_layout, - dst_render_loop, src_queue_mask, dst_queue_mask, range, - sample_locs); + radv_handle_depth_image_transition(cmd_buffer, image, src_layout, dst_layout, + src_queue_mask, dst_queue_mask, range, sample_locs); } else { - radv_handle_color_image_transition(cmd_buffer, image, src_layout, src_render_loop, dst_layout, - dst_render_loop, src_queue_mask, dst_queue_mask, range); + radv_handle_color_image_transition(cmd_buffer, image, src_layout, dst_layout, + src_queue_mask, dst_queue_mask, range); } } @@ -9547,9 +9530,7 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_inf radv_handle_image_transition( cmd_buffer, image, dep_info->pImageMemoryBarriers[i].oldLayout, - false, /* Outside of a renderpass we are never in a renderloop */ dep_info->pImageMemoryBarriers[i].newLayout, - false, /* Outside of a renderpass we are never in a renderloop */ dep_info->pImageMemoryBarriers[i].srcQueueFamilyIndex, dep_info->pImageMemoryBarriers[i].dstQueueFamilyIndex, &dep_info->pImageMemoryBarriers[i].subresourceRange, sample_locs_info ? &sample_locations : NULL); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index fa3ff0d..6fa3c3e 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -34,6 +34,7 @@ #include "radv_radeon_winsys.h" #include "sid.h" #include "vk_format.h" +#include "vk_render_pass.h" #include "vk_util.h" #include "gfx10_format_table.h" @@ -2212,7 +2213,7 @@ radv_image_view_finish(struct radv_image_view *iview) bool radv_layout_is_htile_compressed(const struct radv_device *device, const struct radv_image *image, - VkImageLayout layout, bool in_render_loop, unsigned queue_mask) + VkImageLayout layout, unsigned queue_mask) { switch (layout) { case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL: @@ -2236,7 +2237,7 @@ radv_layout_is_htile_compressed(const struct radv_device *device, const struct r * queue is likely broken for eg. depth/stencil copies. */ if (radv_image_is_tc_compat_htile(image) && queue_mask & (1u << RADV_QUEUE_GENERAL) && - !in_render_loop && !device->instance->disable_tc_compat_htile_in_general) { + !device->instance->disable_tc_compat_htile_in_general) { return true; } else { return false; @@ -2266,11 +2267,11 @@ radv_layout_is_htile_compressed(const struct radv_device *device, const struct r bool radv_layout_can_fast_clear(const struct radv_device *device, const struct radv_image *image, - unsigned level, VkImageLayout layout, bool in_render_loop, + unsigned level, VkImageLayout layout, unsigned queue_mask) { if (radv_dcc_enabled(image, level) && - !radv_layout_dcc_compressed(device, image, level, layout, in_render_loop, queue_mask)) + !radv_layout_dcc_compressed(device, image, level, layout, queue_mask)) return false; if (!(image->vk.usage & RADV_IMAGE_USAGE_WRITE_BITS)) @@ -2289,8 +2290,7 @@ radv_layout_can_fast_clear(const struct radv_device *device, const struct radv_i bool radv_layout_dcc_compressed(const struct radv_device *device, const struct radv_image *image, - unsigned level, VkImageLayout layout, bool in_render_loop, - unsigned queue_mask) + unsigned level, VkImageLayout layout, unsigned queue_mask) { if (!radv_dcc_enabled(image, level)) return false; @@ -2308,7 +2308,7 @@ radv_layout_dcc_compressed(const struct radv_device *device, const struct radv_i (queue_mask & (1u << RADV_QUEUE_COMPUTE)) && !radv_image_use_dcc_image_stores(device, image)) return false; - if (in_render_loop || layout == VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT) { + if (layout == VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT) { /* Do not compress DCC with feedback loops because we can't read&write it without introducing * corruption. */ diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index e0e7c82..2bc6352 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -511,7 +511,7 @@ create_depthstencil_pipeline(struct radv_device *device, VkImageAspectFlags aspe static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer, const struct radv_image_view *iview, - VkImageAspectFlags aspects, VkImageLayout layout, bool in_render_loop, + VkImageAspectFlags aspects, VkImageLayout layout, const VkClearRect *clear_rect, VkClearDepthStencilValue clear_value) { if (!iview) @@ -530,7 +530,7 @@ depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer, const struct radv_ return false; if (radv_htile_enabled(iview->image, iview->vk.base_mip_level) && iview->vk.base_mip_level == 0 && iview->vk.base_array_layer == 0 && iview->vk.layer_count == iview->image->info.array_size && - radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, in_render_loop, + radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, queue_mask) && radv_image_extent_compare(iview->image, &iview->extent)) return true; @@ -540,10 +540,10 @@ depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer, const struct radv_ static VkPipeline pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_state *meta_state, const struct radv_image_view *iview, int samples_log2, - VkImageAspectFlags aspects, VkImageLayout layout, bool in_render_loop, + VkImageAspectFlags aspects, VkImageLayout layout, const VkClearRect *clear_rect, VkClearDepthStencilValue clear_value) { - bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, in_render_loop, + bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value); bool unrestricted = cmd_buffer->device->vk.enabled_extensions.EXT_depth_range_unrestricted; int index = fast ? DEPTH_CLEAR_FAST : DEPTH_CLEAR_SLOW; @@ -630,7 +630,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachm VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer, meta_state, iview, samples_log2, aspects, - ds_att->layout, ds_att->in_render_loop, clear_rect, clear_value); + ds_att->layout, clear_rect, clear_value); if (!pipeline) return; @@ -645,7 +645,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachm radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline); - if (depth_view_can_fast_clear(cmd_buffer, iview, aspects, ds_att->layout, ds_att->in_render_loop, + if (depth_view_can_fast_clear(cmd_buffer, iview, aspects, ds_att->layout, clear_rect, clear_value)) radv_update_ds_clear_metadata(cmd_buffer, iview, clear_value, aspects); @@ -809,7 +809,7 @@ radv_is_fast_clear_stencil_allowed(VkClearDepthStencilValue value) static bool radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_image_view *iview, - VkImageLayout image_layout, bool in_render_loop, + VkImageLayout image_layout, VkImageAspectFlags aspects, const VkClearRect *clear_rect, const VkClearDepthStencilValue clear_value, uint32_t view_mask) { @@ -817,7 +817,7 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_ return false; if (!radv_layout_is_htile_compressed( - cmd_buffer->device, iview->image, image_layout, in_render_loop, + cmd_buffer->device, iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->qf, cmd_buffer->qf))) return false; @@ -1706,7 +1706,7 @@ gfx11_get_fast_clear_parameters(struct radv_device *device, const struct radv_im static bool radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_image_view *iview, - VkImageLayout image_layout, bool in_render_loop, + VkImageLayout image_layout, const VkClearRect *clear_rect, VkClearColorValue clear_value, uint32_t view_mask) { @@ -1716,7 +1716,7 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_ return false; if (!radv_layout_can_fast_clear( - cmd_buffer->device, iview->image, iview->vk.base_mip_level, image_layout, in_render_loop, + cmd_buffer->device, iview->image, iview->vk.base_mip_level, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->qf, cmd_buffer->qf))) return false; @@ -1878,12 +1878,11 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachment *clear_at return; VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout; - bool in_render_loop = subpass->color_attachments[subpass_att].in_render_loop; const struct radv_image_view *iview = fb ? cmd_buffer->state.attachments[pass_att].iview : NULL; VkClearColorValue clear_value = clear_att->clearValue.color; - if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout, in_render_loop, clear_rect, + if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout, clear_rect, clear_value, view_mask)) { radv_fast_clear_color(cmd_buffer, iview, clear_att, subpass_att, pre_flush, post_flush); } else { @@ -1899,14 +1898,13 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachment *clear_at return; VkImageLayout image_layout = ds_att->layout; - bool in_render_loop = ds_att->in_render_loop; const struct radv_image_view *iview = fb ? cmd_buffer->state.attachments[ds_att->attachment].iview : NULL; VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil; assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)); - if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout, in_render_loop, aspects, + if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout, aspects, clear_rect, clear_value, view_mask)) { radv_fast_clear_depth(cmd_buffer, iview, clear_att, pre_flush, post_flush); } else { @@ -2148,7 +2146,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *im */ static bool radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, VkFormat format, - VkImageLayout image_layout, bool in_render_loop, + VkImageLayout image_layout, const VkImageSubresourceRange *range, const VkClearValue *clear_val) { struct radv_image_view iview; @@ -2192,14 +2190,14 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima }; if (vk_format_is_color(format)) { - if (radv_can_fast_clear_color(cmd_buffer, &iview, image_layout, in_render_loop, &clear_rect, + if (radv_can_fast_clear_color(cmd_buffer, &iview, image_layout, &clear_rect, clear_att.clearValue.color, 0)) { radv_fast_clear_color(cmd_buffer, &iview, &clear_att, clear_att.colorAttachment, NULL, NULL); fast_cleared = true; } } else { - if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout, in_render_loop, + if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout, range->aspectMask, &clear_rect, clear_att.clearValue.depthStencil, 0)) { radv_fast_clear_depth(cmd_buffer, &iview, &clear_att, NULL, NULL); @@ -2242,7 +2240,7 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag /* Don't use compressed image stores because they will use an incompatible format. */ if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel, - image_layout, false, queue_mask)) { + image_layout, queue_mask)) { disable_compression = cs; break; } @@ -2264,7 +2262,7 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag /* Try to perform a fast clear first, otherwise fallback to * the legacy path. */ - if (!cs && radv_fast_clear_range(cmd_buffer, image, format, image_layout, false, range, + if (!cs && radv_fast_clear_range(cmd_buffer, image, format, image_layout, range, &internal_clear_value)) { continue; } diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c index 74404ce..25f88b9 100644 --- a/src/amd/vulkan/radv_meta_copy.c +++ b/src/amd/vulkan/radv_meta_copy.c @@ -136,7 +136,7 @@ copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf cmd_buffer->qf); bool compressed = radv_layout_dcc_compressed(cmd_buffer->device, image, region->imageSubresource.mipLevel, - layout, false, queue_mask); + layout, queue_mask); if (compressed) { radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange){ @@ -285,7 +285,7 @@ copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf cmd_buffer->qf); bool compressed = radv_layout_dcc_compressed(cmd_buffer->device, image, region->imageSubresource.mipLevel, - layout, false, queue_mask); + layout, queue_mask); if (compressed) { radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange){ @@ -383,7 +383,7 @@ copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, cmd_buffer->qf); if (radv_layout_is_htile_compressed(cmd_buffer->device, dst_image, dst_image_layout, - false, queue_mask) && + queue_mask) && (region->dstOffset.x || region->dstOffset.y || region->dstOffset.z || region->extent.width != dst_image->info.width || region->extent.height != dst_image->info.height || @@ -433,12 +433,12 @@ copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, dst_image, cmd_buffer->qf, cmd_buffer->qf); bool dst_compressed = radv_layout_dcc_compressed(cmd_buffer->device, dst_image, region->dstSubresource.mipLevel, - dst_image_layout, false, dst_queue_mask); + dst_image_layout, dst_queue_mask); uint32_t src_queue_mask = radv_image_queue_family_mask( src_image, cmd_buffer->qf, cmd_buffer->qf); bool src_compressed = radv_layout_dcc_compressed(cmd_buffer->device, src_image, region->srcSubresource.mipLevel, - src_image_layout, false, src_queue_mask); + src_image_layout, src_queue_mask); bool need_dcc_sign_reinterpret = false; if (!src_compressed || @@ -537,7 +537,7 @@ copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, cmd_buffer->qf); if (radv_layout_is_htile_compressed(cmd_buffer->device, dst_image, dst_image_layout, - false, queue_mask)) { + queue_mask)) { cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE; diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index 96ab0ac..a42e34f 100644 --- a/src/amd/vulkan/radv_meta_resolve.c +++ b/src/amd/vulkan/radv_meta_resolve.c @@ -288,7 +288,7 @@ static void radv_pick_resolve_method_images(struct radv_device *device, struct radv_image *src_image, VkFormat src_format, struct radv_image *dest_image, unsigned dest_level, VkImageLayout dest_image_layout, - bool dest_render_loop, struct radv_cmd_buffer *cmd_buffer, + struct radv_cmd_buffer *cmd_buffer, enum radv_resolve_method *method) { @@ -302,7 +302,7 @@ radv_pick_resolve_method_images(struct radv_device *device, struct radv_image *s * TODO: Add support for layered and int to the fragment path. */ if (radv_layout_dcc_compressed(device, dest_image, dest_level, dest_image_layout, - dest_render_loop, queue_mask)) { + queue_mask)) { *method = RESOLVE_FRAGMENT; } else if (!image_hw_resolve_compat(device, src_image, dest_image)) { /* The micro tile mode only needs to match for the HW @@ -404,7 +404,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv cmd_buffer->qf); if (radv_layout_dcc_compressed(cmd_buffer->device, dst_image, region->dstSubresource.mipLevel, - dst_image_layout, false, queue_mask)) { + dst_image_layout, queue_mask)) { VkImageSubresourceRange range = { .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT, .baseMipLevel = region->dstSubresource.mipLevel, @@ -566,7 +566,7 @@ radv_CmdResolveImage2(VkCommandBuffer commandBuffer, const VkImageResolve2 *region = &pResolveImageInfo->pRegions[r]; radv_pick_resolve_method_images(cmd_buffer->device, src_image, src_image->vk.format, dst_image, - region->dstSubresource.mipLevel, dst_image_layout, false, + region->dstSubresource.mipLevel, dst_image_layout, cmd_buffer, &resolve_method); resolve_image(cmd_buffer, src_image, src_image_layout, dst_image, dst_image_layout, region, @@ -601,7 +601,7 @@ radv_cmd_buffer_resolve_subpass_hw(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->qf); if (radv_layout_dcc_compressed(cmd_buffer->device, dst_img, dest_iview->vk.base_mip_level, - dst_image_layout, false, queue_mask)) { + dst_image_layout, queue_mask)) { VkImageSubresourceRange range = { .aspectMask = dest_iview->vk.aspects, .baseMipLevel = dest_iview->vk.base_mip_level, @@ -666,7 +666,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer) radv_pick_resolve_method_images(cmd_buffer->device, src_iview->image, src_iview->vk.format, dst_iview->image, dst_iview->vk.base_mip_level, dst_att.layout, - dst_att.in_render_loop, cmd_buffer, &resolve_method); + cmd_buffer, &resolve_method); if ((src_iview->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && subpass->depth_resolve_mode != VK_RESOLVE_MODE_NONE) { @@ -733,7 +733,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer) radv_pick_resolve_method_images(cmd_buffer->device, src_img, src_iview->vk.format, dst_img, dst_iview->vk.base_mip_level, dest_att.layout, - dest_att.in_render_loop, cmd_buffer, &resolve_method); + cmd_buffer, &resolve_method); if (resolve_method == RESOLVE_FRAGMENT) { break; diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index 83e86e9..4da25c2 100644 --- a/src/amd/vulkan/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/radv_meta_resolve_cs.c @@ -681,7 +681,7 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_ if (!radv_image_use_dcc_image_stores(cmd_buffer->device, dest_image) && radv_layout_dcc_compressed(cmd_buffer->device, dest_image, region->dstSubresource.mipLevel, - dest_image_layout, false, queue_mask) && + dest_image_layout, queue_mask) && (region->dstOffset.x || region->dstOffset.y || region->dstOffset.z || region->extent.width != dest_image->info.width || region->extent.height != dest_image->info.height || @@ -764,7 +764,7 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_ if (!radv_image_use_dcc_image_stores(cmd_buffer->device, dest_image) && radv_layout_dcc_compressed(cmd_buffer->device, dest_image, region->dstSubresource.mipLevel, - dest_image_layout, false, queue_mask)) { + dest_image_layout, queue_mask)) { cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE; @@ -932,7 +932,7 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer, uint32_t queue_mask = radv_image_queue_family_mask(dst_image, cmd_buffer->qf, cmd_buffer->qf); - if (radv_layout_is_htile_compressed(cmd_buffer->device, dst_image, layout, false, queue_mask)) { + if (radv_layout_is_htile_compressed(cmd_buffer->device, dst_image, layout, queue_mask)) { VkImageSubresourceRange range = {0}; range.aspectMask = aspects; range.baseMipLevel = dst_iview->vk.base_mip_level; diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c index c731ede..c7caf73 100644 --- a/src/amd/vulkan/radv_pass.c +++ b/src/amd/vulkan/radv_pass.c @@ -26,6 +26,7 @@ */ #include "radv_private.h" +#include "vk_render_pass.h" #include "vk_util.h" static void @@ -288,15 +289,15 @@ radv_render_pass_compile(struct radv_render_pass *pass) for (uint32_t k = 0; k < subpass->color_count; ++k) { if (subpass->color_attachments[k].attachment == subpass->input_attachments[j].attachment) { - subpass->input_attachments[j].in_render_loop = true; - subpass->color_attachments[k].in_render_loop = true; + subpass->input_attachments[j].layout = VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT; + subpass->color_attachments[k].layout = VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT; } } if (subpass->depth_stencil_attachment && subpass->depth_stencil_attachment->attachment == subpass->input_attachments[j].attachment) { - subpass->input_attachments[j].in_render_loop = true; - subpass->depth_stencil_attachment->in_render_loop = true; + subpass->input_attachments[j].layout = VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT; + subpass->depth_stencil_attachment->layout = VK_IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT; } } } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 8151dc4..688f916 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1391,7 +1391,6 @@ struct radv_attachment_state { VkClearValue clear_value; VkImageLayout current_layout; VkImageLayout current_stencil_layout; - bool current_in_render_loop; struct radv_sample_locations_state sample_location; union { @@ -2279,15 +2278,13 @@ struct radv_image { */ bool radv_layout_is_htile_compressed(const struct radv_device *device, const struct radv_image *image, VkImageLayout layout, - bool in_render_loop, unsigned queue_mask); + unsigned queue_mask); bool radv_layout_can_fast_clear(const struct radv_device *device, const struct radv_image *image, - unsigned level, VkImageLayout layout, bool in_render_loop, - unsigned queue_mask); + unsigned level, VkImageLayout layout, unsigned queue_mask); bool radv_layout_dcc_compressed(const struct radv_device *device, const struct radv_image *image, - unsigned level, VkImageLayout layout, bool in_render_loop, - unsigned queue_mask); + unsigned level, VkImageLayout layout, unsigned queue_mask); bool radv_layout_fmask_compressed(const struct radv_device *device, const struct radv_image *image, VkImageLayout layout, unsigned queue_mask); @@ -2675,7 +2672,6 @@ struct radv_subpass_attachment { uint32_t attachment; VkImageLayout layout; VkImageLayout stencil_layout; - bool in_render_loop; }; struct radv_subpass { -- 2.7.4