From 4e38df18ea3fce41313bae3502c66c98952eb508 Mon Sep 17 00:00:00 2001 From: Daniel Cederman Date: Wed, 18 Jul 2018 09:25:33 +0000 Subject: [PATCH] [Sparc] Use the IntPair reg class for r constraints with value type f64 Summary: This is how it appears to be handled in GCC and it prevents a "Unknown mismatch" error in the SelectionDAGBuilder. Reviewers: venkatra, jyknight, jrtc27 Reviewed By: jyknight, jrtc27 Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D49218 llvm-svn: 337370 --- llvm/lib/Target/Sparc/SparcISelLowering.cpp | 2 +- llvm/test/CodeGen/SPARC/inlineasm.ll | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index b04c6b1..178bb53 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -3489,7 +3489,7 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, if (Constraint.size() == 1) { switch (Constraint[0]) { case 'r': - if (VT == MVT::v2i32) + if (VT == MVT::v2i32 || VT == MVT::f64) return std::make_pair(0U, &SP::IntPairRegClass); else return std::make_pair(0U, &SP::IntRegsRegClass); diff --git a/llvm/test/CodeGen/SPARC/inlineasm.ll b/llvm/test/CodeGen/SPARC/inlineasm.ll index a67a45e..12445ea9 100644 --- a/llvm/test/CodeGen/SPARC/inlineasm.ll +++ b/llvm/test/CodeGen/SPARC/inlineasm.ll @@ -130,3 +130,12 @@ entry: tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0) ret void } + +; CHECK-LABEL: test_constraint_r_f64: +; CHECK: std %o0, [%sp+96] +; CHECK: ldd [%sp+96], %f0 +define double @test_constraint_r_f64() { +entry: + %0 = call double asm sideeffect "", "=r"() + ret double %0 +} -- 2.7.4