From 4dfd2590dccaaa0999b7c99ba85ad236b463c1ac Mon Sep 17 00:00:00 2001 From: Aditya Nandakumar Date: Mon, 23 Oct 2017 22:53:04 +0000 Subject: [PATCH] [GISel][AArch64]: Fix illegal Generic copies in tests This is in preparation for a verifier check that makes sure copies are of the same size (when generic virtual registers are involved). llvm-svn: 316387 --- .../AArch64/GlobalISel/legalize-inserts.mir | 12 ++-- .../CodeGen/AArch64/GlobalISel/legalize-phi.mir | 12 ++-- .../GlobalISel/localizer-in-O0-pipeline.mir | 7 ++- .../CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir | 3 +- .../AArch64/GlobalISel/regbankselect-default.mir | 10 ++-- llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir | 4 +- .../CodeGen/AArch64/GlobalISel/select-constant.mir | 4 +- .../test/CodeGen/AArch64/GlobalISel/select-fma.mir | 4 +- .../test/CodeGen/AArch64/GlobalISel/select-imm.mir | 4 +- .../CodeGen/AArch64/GlobalISel/select-int-ext.mir | 65 +++++++++++++++------- .../AArch64/GlobalISel/select-int-ptr-casts.mir | 21 +++++-- .../CodeGen/AArch64/GlobalISel/select-load.mir | 28 +++++++--- .../test/CodeGen/AArch64/GlobalISel/select-phi.mir | 3 +- .../CodeGen/AArch64/GlobalISel/select-store.mir | 28 +++++++--- .../CodeGen/AArch64/GlobalISel/select-trunc.mir | 14 +++-- llvm/test/CodeGen/AArch64/GlobalISel/select.mir | 26 ++++++--- 16 files changed, 168 insertions(+), 77 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir index 917f181..16d9803 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir @@ -90,11 +90,13 @@ body: | ; A narrow insert gets surrounded by a G_ANYEXT/G_TRUNC pair. ; CHECK-LABEL: name: test_inserts_4 - ; CHECK: [[VALEXT:%[0-9]+]](s32) = G_ANYEXT %1(s8) - ; CHECK: [[VAL:%[0-9]+]](s32) = G_INSERT [[VALEXT]], %0(s1), 0 - ; CHECK: %3(s8) = G_TRUNC [[VAL]](s32) - %0:_(s1) = COPY %w0 - %1:_(s8) = COPY %w1 + ; CHECK: [[VALEXT:%[0-9]+]](s32) = COPY %2(s32) + ; CHECK: [[VAL:%[0-9]+]](s32) = G_INSERT [[VALEXT]], %1(s1), 0 + ; CHECK: %5(s8) = G_TRUNC [[VAL]](s32) + %4:_(s32) = COPY %w0 + %0:_(s1) = G_TRUNC %4 + %5:_(s32) = COPY %w1 + %1:_(s8) = G_TRUNC %5 %2:_(p0) = COPY %x2 %3:_(s8) = G_INSERT %1(s8), %0(s1), 0 G_STORE %3(s8), %2(p0) :: (store 1) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir index dd34790..2345b4d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir @@ -128,20 +128,22 @@ body: | bb.1: ; CHECK-LABEL: name: legalize_phi_ptr ; CHECK-LABEL: bb.0: - ; CHECK: %0(p0) = COPY %x0 - ; CHECK: %1(p0) = COPY %x1 - ; CHECK: %2(s1) = COPY %w2 + ; CHECK: [[A:%[0-9]+]](p0) = COPY %x0 + ; CHECK: [[B:%[0-9]+]](p0) = COPY %x1 + ; CHECK: [[CE:%[0-9]+]](s32) = COPY %w2 + ; CHECK: [[C:%[0-9]+]](s1) = G_TRUNC [[CE]] ; CHECK-LABEL: bb.1: ; CHECK-LABEL: bb.2: - ; CHECK: %3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1 + ; CHECK: %3(p0) = G_PHI [[A]](p0), %bb.0, [[B]](p0), %bb.1 ; CHECK: %x0 = COPY %3(p0) successors: %bb.2, %bb.3 liveins: %w2, %x0, %x1 %0(p0) = COPY %x0 %1(p0) = COPY %x1 - %2(s1) = COPY %w2 + %4(s32) = COPY %w2 + %2(s1) = G_TRUNC %4(s32) G_BRCOND %2(s1), %bb.2 G_BR %bb.3 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir index 28c926b..8e66932 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir @@ -41,15 +41,17 @@ registers: # CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' } # CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' } # CHECK-NEXT: - { id: 5, class: fpr, preferred-register: '' } +# CHECK-NEXT: - { id: 6, class: gpr, preferred-register: '' } # The localizer will create two new values to materialize the constants. -# OPTNONE-NEXT: - { id: 6, class: fpr, preferred-register: '' } # OPTNONE-NEXT: - { id: 7, class: fpr, preferred-register: '' } +# OPTNONE-NEXT: - { id: 8, class: fpr, preferred-register: '' } - { id: 0, class: fpr } - { id: 1, class: gpr } - { id: 2, class: fpr } - { id: 3, class: fpr } - { id: 4, class: fpr } - { id: 5, class: fpr } + - { id: 6, class: gpr } # First block remains untouched # CHECK: body @@ -76,7 +78,8 @@ body: | liveins: %s0, %w0 %0(s32) = COPY %s0 - %1(s1) = COPY %w0 + %6(s32) = COPY %w0 + %1(s1) = G_TRUNC %6 %4(s32) = G_FCONSTANT float 1.000000e+00 %5(s32) = G_FCONSTANT float 2.000000e+00 G_BRCOND %1(s1), %bb.1.true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir b/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir index 6ea651d..b675389 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir @@ -17,5 +17,6 @@ body: | %1:_(s64) = COPY %x1 %2:_(p0) = COPY %x2 %3:_(s128) = G_MERGE_VALUES %0, %1 - %d0 = COPY %3 + %4:_(s64) = G_TRUNC %3 + %d0 = COPY %4 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir index a99104f..62f04195 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir @@ -903,15 +903,16 @@ body: | ; CHECK-NEXT: id: 1, class: gpr ; CHECK-NEXT: id: 2, class: gpr ; CHECK-NEXT: id: 3, class: gpr - ; CHECK-NEXT: id: 4, class: _ + ; CHECK-NEXT: id: 4, class: gpr ; CHECK-NEXT: id: 5, class: _ ; CHECK: bb.0: ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: liveins: %w2, %x0, %x1 ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]](p0) = COPY %x1 - ; CHECK: [[COPY2:%[0-9]+]](s1) = COPY %w2 - ; CHECK: G_BRCOND [[COPY2]](s1), %bb.1 + ; CHECK: [[COPY2:%[0-9]+]](s32) = COPY %w2 + ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[COPY2]](s32) + ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1 ; CHECK: G_BR %bb.2 ; CHECK: bb.1: ; CHECK: successors: %bb.2(0x80000000) @@ -925,7 +926,8 @@ body: | %0(p0) = COPY %x0 %1(p0) = COPY %x1 - %2(s1) = COPY %w2 + %4(s32) = COPY %w2 + %2(s1) = G_TRUNC %4(s32) G_BRCOND %2(s1), %bb.1 G_BR %bb.2 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir index f46f190..cd49855 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir @@ -33,6 +33,7 @@ regBankSelected: true registers: - { id: 0, class: gpr } + - { id: 1, class: gpr } # CHECK: body: # CHECK: bb.0: @@ -41,7 +42,8 @@ registers: body: | bb.0: successors: %bb.0, %bb.1 - %0(s1) = COPY %w0 + %1(s32) = COPY %w0 + %0(s1) = G_TRUNC %1 G_BRCOND %0(s1), %bb.1 G_BR %bb.0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir index a9199f2..37c1b89 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir @@ -106,7 +106,7 @@ body: | bb.0: ; CHECK-LABEL: name: fconst_s64_0 ; CHECK: [[FMOVD0_:%[0-9]+]] = FMOVD0 - ; CHECK: %s0 = COPY [[FMOVD0_]] + ; CHECK: %x0 = COPY [[FMOVD0_]] %0(s64) = G_FCONSTANT double 0.0 - %s0 = COPY %0(s64) + %x0 = COPY %0(s64) ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir index 1d38f4f..5013a7b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir @@ -32,11 +32,11 @@ body: | ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 ; CHECK: [[COPY2:%[0-9]+]] = COPY %w2 ; CHECK: [[FMADDSrrr:%[0-9]+]] = FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]] - ; CHECK: %x0 = COPY [[FMADDSrrr]] + ; CHECK: %w0 = COPY [[FMADDSrrr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = COPY %w2 %3(s32) = G_FMA %0, %1, %2 - %x0 = COPY %3 + %w0 = COPY %3 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir index a89adc2..9dc9699 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir @@ -48,7 +48,7 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr64 ; CHECK: [[MOVi64imm:%[0-9]+]] = MOVi64imm 1234 - ; CHECK: %w0 = COPY [[MOVi64imm]] + ; CHECK: %x0 = COPY [[MOVi64imm]] %0(s64) = G_CONSTANT i64 1234 - %w0 = COPY %0(s64) + %x0 = COPY %0(s64) ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir index b7b7de4..8b1da70 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir @@ -60,12 +60,15 @@ body: | ; CHECK-LABEL: name: anyext_s32_from_s8 ; CHECK: registers: - ; CHECK-NEXT: id: 0, class: gpr32all + ; CHECK-NEXT: id: 0, class: gpr32 ; CHECK-NEXT: id: 1, class: gpr32all + ; CHECK-NEXT: id: 2, class: gpr32 ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] - ; CHECK: %w0 = COPY [[COPY1]] - %0(s8) = COPY %w0 + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]] + ; CHECK: %w0 = COPY [[COPY2]] + %2:gpr(s32) = COPY %w0 + %0(s8) = G_TRUNC %2 %1(s32) = G_ANYEXT %0 %w0 = COPY %1(s32) ... @@ -114,10 +117,13 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr32 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 - ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY]], 0, 15 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY1]], 0, 15 ; CHECK: %w0 = COPY [[UBFMWri]] - %0(s16) = COPY %w0 + %2:gpr(s32) = COPY %w0 + %0(s16) = G_TRUNC %2 %1(s32) = G_ZEXT %0 %w0 = COPY %1 ... @@ -139,10 +145,13 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr32 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 - ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY]], 0, 7 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY1]], 0, 15 ; CHECK: %w0 = COPY [[UBFMWri]] - %0(s8) = COPY %w0 + %2:gpr(s32) = COPY %w0 + %0(s16) = G_TRUNC %2 %1(s32) = G_ZEXT %0 %w0 = COPY %1(s32) ... @@ -164,12 +173,18 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr32 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK-NEXT: id: 3, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 - ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY]], 0, 7 - ; CHECK: %w0 = COPY [[UBFMWri]] - %0(s8) = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY1]], 0, 7 + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[UBFMWri]] + ; CHECK: %w0 = COPY [[COPY2]] + %2:gpr(s32) = COPY %w0 + %0(s8) = G_TRUNC %2 %1(s16) = G_ZEXT %0 - %w0 = COPY %1(s16) + %3:gpr(s32) = G_ANYEXT %1 + %w0 = COPY %3(s32) ... --- @@ -216,10 +231,13 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr32 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 - ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY]], 0, 15 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY1]], 0, 15 ; CHECK: %w0 = COPY [[SBFMWri]] - %0(s16) = COPY %w0 + %2:gpr(s32) = COPY %w0 + %0(s16) = G_TRUNC %2 %1(s32) = G_SEXT %0 %w0 = COPY %1 ... @@ -241,10 +259,13 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr32 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 - ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY]], 0, 7 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY1]], 0, 7 ; CHECK: %w0 = COPY [[SBFMWri]] - %0(s8) = COPY %w0 + %2:gpr(s32) = COPY %w0 + %0(s8) = G_TRUNC %2 %1(s32) = G_SEXT %0 %w0 = COPY %1(s32) ... @@ -266,10 +287,16 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr32 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK-NEXT: id: 3, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 - ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY]], 0, 7 - ; CHECK: %w0 = COPY [[SBFMWri]] - %0(s8) = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY1]], 0, 7 + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[SBFMWri]] + ; CHECK: %w0 = COPY [[COPY2]] + %2:gpr(s32) = COPY %w0 + %0(s8) = G_TRUNC %2 %1(s16) = G_SEXT %0 - %w0 = COPY %1(s16) + %3:gpr(s32) = G_ANYEXT %1 + %w0 = COPY %3(s32) ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir index 5856646..13c7b08 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir @@ -96,12 +96,15 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr64 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32 - ; CHECK: %w0 = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]] + ; CHECK: %w0 = COPY [[COPY2]] %0(p0) = COPY %x0 %1(s16) = G_PTRTOINT %0 - %w0 = COPY %1(s16) + %2:gpr(s32) = G_ANYEXT %1 + %w0 = COPY %2(s32) ... --- @@ -119,12 +122,15 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr64 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32 - ; CHECK: %w0 = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]] + ; CHECK: %w0 = COPY [[COPY2]] %0(p0) = COPY %x0 %1(s8) = G_PTRTOINT %0 - %w0 = COPY %1(s8) + %2:gpr(s32) = G_ANYEXT %1 + %w0 = COPY %2(s32) ... --- @@ -142,10 +148,13 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr64 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32 - ; CHECK: %w0 = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]] + ; CHECK: %w0 = COPY [[COPY2]] %0(p0) = COPY %x0 %1(s1) = G_PTRTOINT %0 - %w0 = COPY %1(s1) + %2:gpr(s32) = G_ANYEXT %1 + %w0 = COPY %2(s32) ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir index 801ba35..3c997e5 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir @@ -99,12 +99,15 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr64sp ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[LDRHHui:%[0-9]+]] = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) - ; CHECK: %w0 = COPY [[LDRHHui]] + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[LDRHHui]] + ; CHECK: %w0 = COPY [[COPY1]] %0(p0) = COPY %x0 %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr) - %w0 = COPY %1(s16) + %2:gpr(s32) = G_ANYEXT %1 + %w0 = COPY %2(s32) ... --- @@ -124,12 +127,15 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr64sp ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[LDRBBui:%[0-9]+]] = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr) - ; CHECK: %w0 = COPY [[LDRBBui]] + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[LDRBBui]] + ; CHECK: %w0 = COPY [[COPY1]] %0(p0) = COPY %x0 %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr) - %w0 = COPY %1(s8) + %2:gpr(s32) = G_ANYEXT %1 + %w0 = COPY %2(s32) ... --- @@ -242,14 +248,17 @@ body: | ; CHECK-NEXT: id: 1, class: gpr ; CHECK-NEXT: id: 2, class: gpr ; CHECK-NEXT: id: 3, class: gpr32 + ; CHECK-NEXT: id: 4, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[LDRHHui:%[0-9]+]] = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr) - ; CHECK: %w0 = COPY [[LDRHHui]] + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[LDRHHui]] + ; CHECK: %w0 = COPY [[COPY1]] %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 64 %2(p0) = G_GEP %0, %1 %3(s16) = G_LOAD %2 :: (load 2 from %ir.addr) - %w0 = COPY %3 + %4:gpr(s32) = G_ANYEXT %3 + %w0 = COPY %4 ... --- @@ -273,14 +282,17 @@ body: | ; CHECK-NEXT: id: 1, class: gpr ; CHECK-NEXT: id: 2, class: gpr ; CHECK-NEXT: id: 3, class: gpr32 + ; CHECK-NEXT: id: 4, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[LDRBBui:%[0-9]+]] = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr) - ; CHECK: %w0 = COPY [[LDRBBui]] + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[LDRBBui]] + ; CHECK: %w0 = COPY [[COPY1]] %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 1 %2(p0) = G_GEP %0, %1 %3(s8) = G_LOAD %2 :: (load 1 from %ir.addr) - %w0 = COPY %3 + %4:gpr(s32) = G_ANYEXT %3 + %w0 = COPY %4 ... --- diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir index cbdab49..ccc4fcb 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir @@ -106,7 +106,8 @@ body: | %0(p0) = COPY %x0 %1(p0) = COPY %x1 - %2(s1) = COPY %w2 + %6:gpr(s32) = COPY %w2 + %2(s1) = G_TRUNC %6 G_BRCOND %2(s1), %bb.1 G_BR %bb.2 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir index 4c44511..95f32c3 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir @@ -100,11 +100,14 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr64sp ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 - ; CHECK: STRHHui [[COPY1]], [[COPY]], 0 :: (store 2 into %ir.addr) + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]] + ; CHECK: STRHHui [[COPY2]], [[COPY]], 0 :: (store 2 into %ir.addr) %0(p0) = COPY %x0 - %1(s16) = COPY %w1 + %2:gpr(s32) = COPY %w1 + %1(s16) = G_TRUNC %2 G_STORE %1, %0 :: (store 2 into %ir.addr) ... @@ -126,11 +129,14 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr64sp ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 - ; CHECK: STRBBui [[COPY1]], [[COPY]], 0 :: (store 1 into %ir.addr) + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]] + ; CHECK: STRBBui [[COPY2]], [[COPY]], 0 :: (store 1 into %ir.addr) %0(p0) = COPY %x0 - %1(s8) = COPY %w1 + %2:gpr(s32) = COPY %w1 + %1(s8) = G_TRUNC %2 G_STORE %1, %0 :: (store 1 into %ir.addr) ... @@ -295,11 +301,14 @@ body: | ; CHECK-NEXT: id: 1, class: gpr32 ; CHECK-NEXT: id: 2, class: gpr ; CHECK-NEXT: id: 3, class: gpr + ; CHECK-NEXT: id: 4, class: gpr32 ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 - ; CHECK: STRHHui [[COPY1]], [[COPY]], 32 :: (store 2 into %ir.addr) + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]] + ; CHECK: STRHHui [[COPY2]], [[COPY]], 32 :: (store 2 into %ir.addr) %0(p0) = COPY %x0 - %1(s16) = COPY %w1 + %4:gpr(s32) = COPY %w1 + %1(s16) = G_TRUNC %4 %2(s64) = G_CONSTANT i64 64 %3(p0) = G_GEP %0, %2 G_STORE %1, %3 :: (store 2 into %ir.addr) @@ -326,11 +335,14 @@ body: | ; CHECK-NEXT: id: 1, class: gpr32 ; CHECK-NEXT: id: 2, class: gpr ; CHECK-NEXT: id: 3, class: gpr + ; CHECK-NEXT: id: 4, class: gpr32 ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 - ; CHECK: STRBBui [[COPY1]], [[COPY]], 1 :: (store 1 into %ir.addr) + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]] + ; CHECK: STRBBui [[COPY2]], [[COPY]], 1 :: (store 1 into %ir.addr) %0(p0) = COPY %x0 - %1(s8) = COPY %w1 + %4:gpr(s32) = COPY %w1 + %1(s8) = G_TRUNC %4 %2(s64) = G_CONSTANT i64 1 %3(p0) = G_GEP %0, %2 G_STORE %1, %3 :: (store 1 into %ir.addr) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir index 1d66644..1b51242 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir @@ -51,12 +51,15 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr64 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32 - ; CHECK: %w0 = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]] + ; CHECK: %w0 = COPY [[COPY2]] %0(s64) = COPY %x0 %1(s8) = G_TRUNC %0 - %w0 = COPY %1(s8) + %2:gpr(s32) = G_ANYEXT %1 + %w0 = COPY %2(s32) ... --- @@ -76,10 +79,13 @@ body: | ; CHECK: registers: ; CHECK-NEXT: id: 0, class: gpr32 ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32all ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] - ; CHECK: %w0 = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]] + ; CHECK: %w0 = COPY [[COPY2]] %0(s32) = COPY %w0 %1(s1) = G_TRUNC %0 - %w0 = COPY %1(s1) + %2:gpr(s32) = G_ANYEXT %1 + %w0 = COPY %2(s32) ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir index dfd8133..1c72c3e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir @@ -148,6 +148,9 @@ registers: - { id: 6, class: gpr } - { id: 7, class: gpr } - { id: 8, class: gpr } + - { id: 9, class: gpr } + - { id: 10, class: gpr } + - { id: 11, class: gpr } # CHECK: body: # CHECK: %wzr = SUBSWrr %0, %0, implicit-def %nzcv @@ -166,17 +169,20 @@ body: | %0(s32) = COPY %w0 %1(s32) = G_ICMP intpred(eq), %0, %0 %6(s1) = G_TRUNC %1(s32) - %w0 = COPY %6(s1) + %9(s32) = G_ANYEXT %6 + %w0 = COPY %9(s32) %2(s64) = COPY %x0 %3(s32) = G_ICMP intpred(uge), %2, %2 %7(s1) = G_TRUNC %3(s32) - %w0 = COPY %7(s1) + %10(s32) = G_ANYEXT %7 + %w0 = COPY %10(s32) %4(p0) = COPY %x0 %5(s32) = G_ICMP intpred(ne), %4, %4 %8(s1) = G_TRUNC %5(s32) - %w0 = COPY %8(s1) + %11(s32) = G_ANYEXT %8 + %w0 = COPY %11(s32) ... --- @@ -199,6 +205,8 @@ registers: - { id: 3, class: gpr } - { id: 4, class: gpr } - { id: 5, class: gpr } + - { id: 6, class: gpr } + - { id: 7, class: gpr } # CHECK: body: # CHECK: FCMPSrr %0, %0, implicit-def %nzcv @@ -216,12 +224,14 @@ body: | %0(s32) = COPY %s0 %1(s32) = G_FCMP floatpred(one), %0, %0 %4(s1) = G_TRUNC %1(s32) - %w0 = COPY %4(s1) + %6(s32) = G_ANYEXT %4 + %w0 = COPY %6(s32) %2(s64) = COPY %d0 %3(s32) = G_FCMP floatpred(uge), %2, %2 %5(s1) = G_TRUNC %3(s32) - %w0 = COPY %5(s1) + %7(s32) = G_ANYEXT %5 + %w0 = COPY %7(s32) ... @@ -250,7 +260,8 @@ body: | liveins: %s0, %w0 successors: %bb.1 %0(s32) = COPY %s0 - %1(s1) = COPY %w0 + %3:gpr(s32) = COPY %w0 + %1(s1) = G_TRUNC %3 bb.1: successors: %bb.1, %bb.2 @@ -302,7 +313,8 @@ registers: body: | bb.0: liveins: %w0, %w1, %w2 - %0(s1) = COPY %w0 + %10:gpr(s32) = COPY %w0 + %0(s1) = G_TRUNC %10 %1(s32) = COPY %w1 %2(s32) = COPY %w2 -- 2.7.4