From 4de324442b2cd4b30f73a7d1b277078549774783 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 2 Aug 2014 02:26:51 +0000 Subject: [PATCH] R600: Cleanup fneg tests llvm-svn: 214612 --- llvm/test/CodeGen/R600/fneg-fabs.ll | 94 ++++++++++++++++++--------------- llvm/test/CodeGen/R600/fneg.ll | 101 +++++++++++++++++------------------- 2 files changed, 101 insertions(+), 94 deletions(-) diff --git a/llvm/test/CodeGen/R600/fneg-fabs.ll b/llvm/test/CodeGen/R600/fneg-fabs.ll index d95e131..8f75459 100644 --- a/llvm/test/CodeGen/R600/fneg-fabs.ll +++ b/llvm/test/CodeGen/R600/fneg-fabs.ll @@ -1,55 +1,67 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s + ; DAGCombiner will transform: ; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF)) ; unless isFabsFree returns true -; R600-CHECK-LABEL: @fneg_fabs_free -; R600-CHECK-NOT: AND -; R600-CHECK: |PV.{{[XYZW]}}| -; R600-CHECK: -PV -; SI-CHECK-LABEL: @fneg_fabs_free -; SI-CHECK: V_OR_B32 - -define void @fneg_fabs_free(float addrspace(1)* %out, i32 %in) { -entry: - %0 = bitcast i32 %in to float - %1 = call float @fabs(float %0) - %2 = fsub float -0.000000e+00, %1 - store float %2, float addrspace(1)* %out +; FUNC-LABEL: @fneg_fabs_free_f32 +; R600-NOT: AND +; R600: |PV.{{[XYZW]}}| +; R600: -PV + +; SI: V_OR_B32 +define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) { + %bc = bitcast i32 %in to float + %fabs = call float @llvm.fabs.f32(float %bc) + %fsub = fsub float -0.000000e+00, %fabs + store float %fsub, float addrspace(1)* %out ret void } -; R600-CHECK-LABEL: @fneg_fabs_v2 -; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| -; R600-CHECK: -PV -; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| -; R600-CHECK: -PV -; SI-CHECK-LABEL: @fneg_fabs_v2 -; SI-CHECK: V_OR_B32 -; SI-CHECK: V_OR_B32 -define void @fneg_fabs_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) { -entry: - %0 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in) - %1 = fsub <2 x float> , %0 - store <2 x float> %1, <2 x float> addrspace(1)* %out +; FUNC-LABEL: @fneg_fabs_fn_free_f32 +; R600-NOT: AND +; R600: |PV.{{[XYZW]}}| +; R600: -PV + +; SI: V_OR_B32 +define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) { + %bc = bitcast i32 %in to float + %fabs = call float @fabs(float %bc) + %fsub = fsub float -0.000000e+00, %fabs + store float %fsub, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @fneg_fabs_v2f32 +; R600: |{{(PV|T[0-9])\.[XYZW]}}| +; R600: -PV +; R600: |{{(PV|T[0-9])\.[XYZW]}}| +; R600: -PV + +; SI: V_OR_B32 +; SI: V_OR_B32 +define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { + %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in) + %fsub = fsub <2 x float> , %fabs + store <2 x float> %fsub, <2 x float> addrspace(1)* %out ret void } -; SI-CHECK-LABEL: @fneg_fabs_v4 -; SI-CHECK: V_OR_B32 -; SI-CHECK: V_OR_B32 -; SI-CHECK: V_OR_B32 -; SI-CHECK: V_OR_B32 -define void @fneg_fabs_v4(<4 x float> addrspace(1)* %out, <4 x float> %in) { -entry: - %0 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in) - %1 = fsub <4 x float> , %0 - store <4 x float> %1, <4 x float> addrspace(1)* %out +; FUNC-LABEL: @fneg_fabs_v4f32 +; SI: V_OR_B32 +; SI: V_OR_B32 +; SI: V_OR_B32 +; SI: V_OR_B32 +define void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { + %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in) + %fsub = fsub <4 x float> , %fabs + store <4 x float> %fsub, <4 x float> addrspace(1)* %out ret void } -declare float @fabs(float ) readnone -declare <2 x float> @llvm.fabs.v2f32(<2 x float> ) readnone -declare <4 x float> @llvm.fabs.v4f32(<4 x float> ) readnone +declare float @fabs(float) readnone +declare float @llvm.fabs.f32(float) readnone +declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone +declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone diff --git a/llvm/test/CodeGen/R600/fneg.ll b/llvm/test/CodeGen/R600/fneg.ll index 5b47817..df61618 100644 --- a/llvm/test/CodeGen/R600/fneg.ll +++ b/llvm/test/CodeGen/R600/fneg.ll @@ -1,44 +1,41 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK -; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s -; R600-CHECK-LABEL: @fneg -; R600-CHECK: -PV -; SI-CHECK-LABEL: @fneg -; SI-CHECK: V_XOR_B32 -define void @fneg(float addrspace(1)* %out, float %in) { -entry: - %0 = fsub float -0.000000e+00, %in - store float %0, float addrspace(1)* %out +; FUNC-LABEL: @fneg_f32 +; R600: -PV + +; SI: V_XOR_B32 +define void @fneg_f32(float addrspace(1)* %out, float %in) { + %fneg = fsub float -0.000000e+00, %in + store float %fneg, float addrspace(1)* %out ret void } -; R600-CHECK-LABEL: @fneg_v2 -; R600-CHECK: -PV -; R600-CHECK: -PV -; SI-CHECK-LABEL: @fneg_v2 -; SI-CHECK: V_XOR_B32 -; SI-CHECK: V_XOR_B32 -define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) { -entry: - %0 = fsub <2 x float> , %in - store <2 x float> %0, <2 x float> addrspace(1)* %out +; FUNC-LABEL: @fneg_v2f32 +; R600: -PV +; R600: -PV + +; SI: V_XOR_B32 +; SI: V_XOR_B32 +define void @fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) { + %fneg = fsub <2 x float> , %in + store <2 x float> %fneg, <2 x float> addrspace(1)* %out ret void } -; R600-CHECK-LABEL: @fneg_v4 -; R600-CHECK: -PV -; R600-CHECK: -T -; R600-CHECK: -PV -; R600-CHECK: -PV -; SI-CHECK-LABEL: @fneg_v4 -; SI-CHECK: V_XOR_B32 -; SI-CHECK: V_XOR_B32 -; SI-CHECK: V_XOR_B32 -; SI-CHECK: V_XOR_B32 -define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) { -entry: - %0 = fsub <4 x float> , %in - store <4 x float> %0, <4 x float> addrspace(1)* %out +; FUNC-LABEL: @fneg_v4f32 +; R600: -PV +; R600: -T +; R600: -PV +; R600: -PV + +; SI: V_XOR_B32 +; SI: V_XOR_B32 +; SI: V_XOR_B32 +; SI: V_XOR_B32 +define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) { + %fneg = fsub <4 x float> , %in + store <4 x float> %fneg, <4 x float> addrspace(1)* %out ret void } @@ -46,28 +43,26 @@ entry: ; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000)) ; unless the target returns true for isNegFree() -; R600-CHECK-LABEL: @fneg_free -; R600-CHECK-NOT: XOR -; R600-CHECK: -KC0[2].Z -; SI-CHECK-LABEL: @fneg_free +; FUNC-LABEL: @fneg_free_f32 +; R600-NOT: XOR +; R600: -KC0[2].Z + ; XXX: We could use V_ADD_F32_e64 with the negate bit here instead. -; SI-CHECK: V_SUB_F32_e64 v{{[0-9]}}, 0.000000e+00, s{{[0-9]}}, 0, 0 -define void @fneg_free(float addrspace(1)* %out, i32 %in) { -entry: - %0 = bitcast i32 %in to float - %1 = fsub float 0.0, %0 - store float %1, float addrspace(1)* %out +; SI: V_SUB_F32_e64 v{{[0-9]}}, 0.000000e+00, s{{[0-9]}}, 0, 0 +define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) { + %bc = bitcast i32 %in to float + %fsub = fsub float 0.0, %bc + store float %fsub, float addrspace(1)* %out ret void } -; SI-CHECK-LABEL: @fneg_fold -; SI-CHECK: S_LOAD_DWORD [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb -; SI-CHECK-NOT: V_XOR_B32 -; SI-CHECK: V_MUL_F32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], v{{[0-9]+}} -define void @fneg_fold(float addrspace(1)* %out, float %in) { -entry: - %0 = fsub float -0.0, %in - %1 = fmul float %0, %in - store float %1, float addrspace(1)* %out +; FUNC-LABEL: @fneg_fold +; SI: S_LOAD_DWORD [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb +; SI-NOT: XOR +; SI: V_MUL_F32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], v{{[0-9]+}} +define void @fneg_fold_f32(float addrspace(1)* %out, float %in) { + %fsub = fsub float -0.0, %in + %fmul = fmul float %fsub, %in + store float %fmul, float addrspace(1)* %out ret void } -- 2.7.4