From 4d8fb4948472c976d0c6dcf3380f92332dd660c1 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 27 Jun 2019 14:52:42 +0200 Subject: [PATCH] clk: mvebu: armada-37xx-periph: add PCIe gated clock The PCIe clock is a gated clock which has the same source as GbE0 (both IPs share a set of registers). This source clock is called 'gbe_core' in the driver. Signed-off-by: Miquel Raynal Link: https://lkml.kernel.org/r/20190627125245.26788-2-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd --- drivers/clk/mvebu/armada-37xx-periph.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index 5fc6d48..d9d8429 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -303,6 +303,7 @@ PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1); PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6); PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12); PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18); +static PERIPH_GATE(pcie, 14); static struct clk_periph_data data_sb[] = { REF_CLK_MUX_DD(gbe_50), @@ -318,6 +319,7 @@ static struct clk_periph_data data_sb[] = { REF_CLK_FULL_DD(sdio), REF_CLK_FULL_DD(usb32_usb2_sys), REF_CLK_FULL_DD(usb32_ss_sys), + REF_CLK_GATE(pcie, "gbe_core"), { }, }; -- 2.7.4