From 4d242b18b2427b9ff28fe9faa1ee587b634ef1df Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Thu, 16 Nov 2017 12:29:28 +0000 Subject: [PATCH] [ARM GlobalISel] Add tests for REVSH patterns. NFC Add instruction selector tests for some of the REVSH patterns handled by TableGen. llvm-svn: 318393 --- .../GlobalISel/arm-instruction-select-combos.mir | 185 +++++++++++++++++++++ 1 file changed, 185 insertions(+) diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir index 939c851..d411893 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir @@ -7,6 +7,11 @@ define void @test_mls() #2 { ret void } define void @test_no_mls() { ret void } + define void @test_shifts_to_revsh() #0 { ret void } + define void @test_shifts_to_revsh_commutative() #0 { ret void } + define void @test_shifts_no_revsh_features() #1 { ret void } + define void @test_shifts_no_revsh_constants() #0 { ret void } + attributes #0 = { "target-features"="+v6" } attributes #1 = { "target-features"="-v6" } attributes #2 = { "target-features"="+v6t2" } @@ -182,3 +187,183 @@ body: | BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, _, implicit %r0 ... +--- +name: test_shifts_to_revsh +# CHECK-LABEL: name: test_shifts_to_revsh +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } + - { id: 4, class: gprb } + - { id: 5, class: gprb } + - { id: 6, class: gprb } + - { id: 7, class: gprb } + - { id: 8, class: gprb } + - { id: 9, class: gprb } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 + + %1(s32) = G_CONSTANT i32 24 + %2(s32) = G_SHL %0(s32), %1(s32) + + %3(s32) = G_CONSTANT i32 16 + %4(s32) = G_ASHR %2(s32), %3(s32) + + %5(s32) = G_CONSTANT i32 8 + %6(s32) = G_LSHR %0(s32), %5(s32) + + %7(s32) = G_CONSTANT 255 + %8(s32) = G_AND %6(s32), %7(s32) + + %9(s32) = G_OR %4(s32), %8(s32) + ; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]] + + %r0 = COPY %9(s32) + ; CHECK: %r0 = COPY [[VREGR]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_shifts_to_revsh_commutative +# CHECK-LABEL: name: test_shifts_to_revsh_commutative +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } + - { id: 4, class: gprb } + - { id: 5, class: gprb } + - { id: 6, class: gprb } + - { id: 7, class: gprb } + - { id: 8, class: gprb } + - { id: 9, class: gprb } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 + + %1(s32) = G_CONSTANT i32 24 + %2(s32) = G_SHL %0(s32), %1(s32) + + %3(s32) = G_CONSTANT i32 16 + %4(s32) = G_ASHR %2(s32), %3(s32) + + %5(s32) = G_CONSTANT i32 8 + %6(s32) = G_LSHR %0(s32), %5(s32) + + %7(s32) = G_CONSTANT 255 + %8(s32) = G_AND %6(s32), %7(s32) + + %9(s32) = G_OR %8(s32), %4(s32) + ; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]] + + %r0 = COPY %9(s32) + ; CHECK: %r0 = COPY [[VREGR]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_shifts_no_revsh_features +# CHECK-LABEL: name: test_shifts_no_revsh +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } + - { id: 4, class: gprb } + - { id: 5, class: gprb } + - { id: 6, class: gprb } + - { id: 7, class: gprb } + - { id: 8, class: gprb } + - { id: 9, class: gprb } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + + %1(s32) = G_CONSTANT i32 24 + %2(s32) = G_SHL %0(s32), %1(s32) + + %3(s32) = G_CONSTANT i32 16 + %4(s32) = G_ASHR %2(s32), %3(s32) + + %5(s32) = G_CONSTANT i32 8 + %6(s32) = G_LSHR %0(s32), %5(s32) + + %7(s32) = G_CONSTANT 255 + %8(s32) = G_AND %6(s32), %7(s32) + + %9(s32) = G_OR %4(s32), %8(s32) + ; We don't really care how this is folded as long as it's not into a REVSH. + ; CHECK-NOT: REVSH + + %r0 = COPY %9(s32) + + BX_RET 14, _, implicit %r0 +... +--- +name: test_shifts_no_revsh_constants +# CHECK-LABEL: name: test_shifts_no_revsh_constants +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } + - { id: 4, class: gprb } + - { id: 5, class: gprb } + - { id: 6, class: gprb } + - { id: 7, class: gprb } + - { id: 8, class: gprb } + - { id: 9, class: gprb } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + + %1(s32) = G_CONSTANT i32 16 ; REVSH needs 24 here + %2(s32) = G_SHL %0(s32), %1(s32) + + %3(s32) = G_CONSTANT i32 24 ; REVSH needs 16 here + %4(s32) = G_ASHR %2(s32), %3(s32) + + %5(s32) = G_CONSTANT i32 8 + %6(s32) = G_LSHR %0(s32), %5(s32) + + %7(s32) = G_CONSTANT 255 + %8(s32) = G_AND %6(s32), %7(s32) + + %9(s32) = G_OR %4(s32), %8(s32) + ; We don't really care how this is folded as long as it's not into a REVSH. + ; CHECK-NOT: REVSH + + %r0 = COPY %9(s32) + + BX_RET 14, _, implicit %r0 +... -- 2.7.4