From 4d1df2aa2380966e170b637bcc958e162f7c4fe0 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 13 Sep 2019 05:24:37 +0000 Subject: [PATCH] [TargetRegisterInfo] Remove SVT argument from getCommonSubClass. This was added to support fp128 on x86-64, but appears to be unneeded now. This may be because the FR128 register class added back then was merged with the VR128 register class later. llvm-svn: 371815 --- llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 6 +----- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 2 +- llvm/lib/CodeGen/TargetRegisterInfo.cpp | 18 +++++------------- 3 files changed, 7 insertions(+), 19 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index ea980eb..c42ca3a 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -680,13 +680,9 @@ public: /// Find the largest common subclass of A and B. /// Return NULL if there is no common subclass. - /// The common subclass should contain - /// simple value type SVT if it is not the Any type. const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, - const TargetRegisterClass *B, - const MVT::SimpleValueType SVT = - MVT::SimpleValueType::Any) const; + const TargetRegisterClass *B) const; /// Returns a TargetRegisterClass used for pointer values. /// If a target supports multiple different pointer register classes, diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 3ad9c41..5c6923f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -139,7 +139,7 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, UseRC = RC; else if (RC) { const TargetRegisterClass *ComRC = - TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy); + TRI->getCommonSubClass(UseRC, RC); // If multiple uses expect disjoint register classes, we emit // copies in AddRegisterOperand. if (ComRC) diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index 4e0f752..e5592c3 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -238,24 +238,16 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, static inline const TargetRegisterClass *firstCommonClass(const uint32_t *A, const uint32_t *B, - const TargetRegisterInfo *TRI, - const MVT::SimpleValueType SVT = - MVT::SimpleValueType::Any) { - const MVT VT(SVT); + const TargetRegisterInfo *TRI) { for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) - if (unsigned Common = *A++ & *B++) { - const TargetRegisterClass *RC = - TRI->getRegClass(I + countTrailingZeros(Common)); - if (SVT == MVT::SimpleValueType::Any || TRI->isTypeLegalForClass(*RC, VT)) - return RC; - } + if (unsigned Common = *A++ & *B++) + return TRI->getRegClass(I + countTrailingZeros(Common)); return nullptr; } const TargetRegisterClass * TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, - const TargetRegisterClass *B, - const MVT::SimpleValueType SVT) const { + const TargetRegisterClass *B) const { // First take care of the trivial cases. if (A == B) return A; @@ -264,7 +256,7 @@ TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, // Register classes are ordered topologically, so the largest common // sub-class it the common sub-class with the smallest ID. - return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this, SVT); + return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this); } const TargetRegisterClass * -- 2.7.4