From 4bc6434624222a846115f3bed826c75e5d0bb613 Mon Sep 17 00:00:00 2001
From: Amara Emerson <amara@apple.com>
Date: Sun, 26 Feb 2023 15:42:57 -0800
Subject: [PATCH] [GlobalISel] Fix an assertion failure in
 matchHoistLogicOpWithSameOpcodeHands().

We use this combine in the AArch64 postlegalizer combiner, which causes this
function to query the legalizer rules for the action for an invalid opcode/type
combination (G_AND and p0). Moving the legalizer query until after the validity
check in matchHoistLogicOpWithSameOpcodeHands() fixes this.
---
 llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp     |  5 ++--
 ...stlegalizer-combiner-sameopcode-hands-crash.mir | 28 ++++++++++++++++++++++
 2 files changed, 31 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sameopcode-hands-crash.mir

diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 65d923ae..2939983 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2764,8 +2764,6 @@ bool CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(
   LLT YTy = MRI.getType(Y);
   if (!XTy.isValid() || XTy != YTy)
     return false;
-  if (!isLegalOrBeforeLegalizer({LogicOpcode, {XTy, YTy}}))
-    return false;
 
   // Optional extra source register.
   Register ExtraHandOpSrcReg;
@@ -2791,6 +2789,9 @@ bool CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(
   }
   }
 
+  if (!isLegalOrBeforeLegalizer({LogicOpcode, {XTy, YTy}}))
+    return false;
+
   // Record the steps to build the new instructions.
   //
   // Steps to build (logic x, y)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sameopcode-hands-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sameopcode-hands-crash.mir
new file mode 100644
index 0000000..f8510a2
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sameopcode-hands-crash.mir
@@ -0,0 +1,28 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+---
+name:            crash_fn
+alignment:       4
+tracksRegLiveness: true
+legalized:         true
+body:             |
+  bb.1:
+    ; CHECK-LABEL: name: crash_fn
+    ; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[C]](p0) :: (load (s16), align 8)
+    ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[C]](p0) :: (load (s16))
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ZEXTLOAD1]], [[ZEXTLOAD]]
+    ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
+    %1:_(p0) = G_CONSTANT i64 0
+    %6:_(s32) = G_CONSTANT i32 0
+    %9:_(s1) = G_CONSTANT i1 false
+    %0:_(s16) = G_LOAD %1(p0) :: (load (s16), align 8)
+    %2:_(s32) = G_ZEXT %0(s16)
+    %3:_(s16) = G_LOAD %1(p0) :: (load (s16))
+    %4:_(s32) = G_ZEXT %3(s16)
+    %5:_(s32) = G_AND %4, %2
+    $w0 = COPY %5(s32)
+    RET_ReallyLR implicit $w0
+
+...
-- 
2.7.4