From 4bb19c91d38e36b81e92de3d9b4e61d9b8928b54 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 24 May 2020 22:37:55 +0100 Subject: [PATCH] ARM: dts: r8a7742: Add USB 2.0 host support Describe internal PCI bridge devices, USB phy device and link PCI USB devices to USB phy. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1590356277-19993-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 115 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index df914da..5be3da7 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -505,6 +505,28 @@ status = "disabled"; }; + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7742", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7742", "renesas,rcar-dmac"; @@ -754,6 +776,99 @@ status = "disabled"; }; + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7742", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0b0000 { + compatible = "renesas,pci-r8a7742", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0b0000 0 0xc00>, + <0 0xee0a0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci2: pci@ee0d0000 { + compatible = "renesas,pci-r8a7742", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 703>; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + status = "disabled"; + + bus-range = <2 2>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x20800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x21000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7742", "renesas,rcar-gen2-sdhi"; -- 2.7.4