From 4b77a6a55ec294132dc0fe24dffd47c727f6bbf4 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Wed, 15 May 2019 21:15:44 +0000 Subject: [PATCH] [NFC][InstCombine] Add some more tests for pulling binops through shifts The ashr variant may see relaxation in https://reviews.llvm.org/D61938 llvm-svn: 360814 --- .../InstCombine/pull-binop-through-shift.ll | 260 +++++++++++++++++ .../pull-conditional-binop-through-shift.ll | 308 +++++++++++++++++++++ 2 files changed, 568 insertions(+) create mode 100644 llvm/test/Transforms/InstCombine/pull-binop-through-shift.ll create mode 100644 llvm/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll diff --git a/llvm/test/Transforms/InstCombine/pull-binop-through-shift.ll b/llvm/test/Transforms/InstCombine/pull-binop-through-shift.ll new file mode 100644 index 0000000..5892134 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/pull-binop-through-shift.ll @@ -0,0 +1,260 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -S | FileCheck %s + +; shift left + +define i32 @and_signbit_shl(i32 %x) { +; CHECK-LABEL: @and_signbit_shl( +; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = and i32 [[T0]], -16777216 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 4294901760 ; 0xFFFF0000 + %r = shl i32 %t0, 8 + ret i32 %r +} +define i32 @and_nosignbit_shl(i32 %x) { +; CHECK-LABEL: @and_nosignbit_shl( +; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = and i32 [[T0]], -16777216 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 2147418112 ; 0x7FFF0000 + %r = shl i32 %t0, 8 + ret i32 %r +} + +define i32 @or_signbit_shl(i32 %x) { +; CHECK-LABEL: @or_signbit_shl( +; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = or i32 [[T0]], -16777216 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 4294901760 ; 0xFFFF0000 + %r = shl i32 %t0, 8 + ret i32 %r +} +define i32 @or_nosignbit_shl(i32 %x) { +; CHECK-LABEL: @or_nosignbit_shl( +; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = or i32 [[T0]], -16777216 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 2147418112 ; 0x7FFF0000 + %r = shl i32 %t0, 8 + ret i32 %r +} + +define i32 @xor_signbit_shl(i32 %x) { +; CHECK-LABEL: @xor_signbit_shl( +; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = xor i32 [[T0]], -16777216 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000 + %r = shl i32 %t0, 8 + ret i32 %r +} +define i32 @xor_nosignbit_shl(i32 %x) { +; CHECK-LABEL: @xor_nosignbit_shl( +; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = xor i32 [[T0]], -16777216 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000 + %r = shl i32 %t0, 8 + ret i32 %r +} + +define i32 @add_signbit_shl(i32 %x) { +; CHECK-LABEL: @add_signbit_shl( +; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = add i32 [[T0]], -16777216 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 4294901760 ; 0xFFFF0000 + %r = shl i32 %t0, 8 + ret i32 %r +} +define i32 @add_nosignbit_shl(i32 %x) { +; CHECK-LABEL: @add_nosignbit_shl( +; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = add i32 [[T0]], -16777216 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 2147418112 ; 0x7FFF0000 + %r = shl i32 %t0, 8 + ret i32 %r +} + +; logical shift right + +define i32 @and_signbit_lshr(i32 %x) { +; CHECK-LABEL: @and_signbit_lshr( +; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = and i32 [[T0]], 16776960 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 4294901760 ; 0xFFFF0000 + %r = lshr i32 %t0, 8 + ret i32 %r +} +define i32 @and_nosignbit_lshr(i32 %x) { +; CHECK-LABEL: @and_nosignbit_lshr( +; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = and i32 [[T0]], 8388352 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 2147418112 ; 0x7FFF0000 + %r = lshr i32 %t0, 8 + ret i32 %r +} + +define i32 @or_signbit_lshr(i32 %x) { +; CHECK-LABEL: @or_signbit_lshr( +; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = or i32 [[T0]], 16776960 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 4294901760 ; 0xFFFF0000 + %r = lshr i32 %t0, 8 + ret i32 %r +} +define i32 @or_nosignbit_lshr(i32 %x) { +; CHECK-LABEL: @or_nosignbit_lshr( +; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = or i32 [[T0]], 8388352 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 2147418112 ; 0x7FFF0000 + %r = lshr i32 %t0, 8 + ret i32 %r +} + +define i32 @xor_signbit_lshr(i32 %x) { +; CHECK-LABEL: @xor_signbit_lshr( +; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = xor i32 [[T0]], 16776960 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000 + %r = lshr i32 %t0, 8 + ret i32 %r +} +define i32 @xor_nosignbit_lshr(i32 %x) { +; CHECK-LABEL: @xor_nosignbit_lshr( +; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = xor i32 [[T0]], 8388352 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000 + %r = lshr i32 %t0, 8 + ret i32 %r +} + +define i32 @add_signbit_lshr(i32 %x) { +; CHECK-LABEL: @add_signbit_lshr( +; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], -65536 +; CHECK-NEXT: [[R:%.*]] = lshr i32 [[T0]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 4294901760 ; 0xFFFF0000 + %r = lshr i32 %t0, 8 + ret i32 %r +} +define i32 @add_nosignbit_lshr(i32 %x) { +; CHECK-LABEL: @add_nosignbit_lshr( +; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], 2147418112 +; CHECK-NEXT: [[R:%.*]] = lshr i32 [[T0]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 2147418112 ; 0x7FFF0000 + %r = lshr i32 %t0, 8 + ret i32 %r +} + +; arithmetic shift right + +define i32 @and_signbit_ashr(i32 %x) { +; CHECK-LABEL: @and_signbit_ashr( +; CHECK-NEXT: [[T0:%.*]] = ashr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = and i32 [[T0]], -256 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 4294901760 ; 0xFFFF0000 + %r = ashr i32 %t0, 8 + ret i32 %r +} +define i32 @and_nosignbit_ashr(i32 %x) { +; CHECK-LABEL: @and_nosignbit_ashr( +; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0]], 8388352 +; CHECK-NEXT: ret i32 [[TMP1]] +; + %t0 = and i32 %x, 2147418112 ; 0x7FFF0000 + %r = ashr i32 %t0, 8 + ret i32 %r +} + +define i32 @or_signbit_ashr(i32 %x) { +; CHECK-LABEL: @or_signbit_ashr( +; CHECK-NEXT: [[T0:%.*]] = or i32 [[X:%.*]], -65536 +; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T0]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 4294901760 ; 0xFFFF0000 + %r = ashr i32 %t0, 8 + ret i32 %r +} +define i32 @or_nosignbit_ashr(i32 %x) { +; CHECK-LABEL: @or_nosignbit_ashr( +; CHECK-NEXT: [[T0:%.*]] = ashr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = or i32 [[T0]], 8388352 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 2147418112 ; 0x7FFF0000 + %r = ashr i32 %t0, 8 + ret i32 %r +} + +define i32 @xor_signbit_ashr(i32 %x) { +; CHECK-LABEL: @xor_signbit_ashr( +; CHECK-NEXT: [[T0:%.*]] = xor i32 [[X:%.*]], -65536 +; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T0]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000 + %r = ashr i32 %t0, 8 + ret i32 %r +} +define i32 @xor_nosignbit_ashr(i32 %x) { +; CHECK-LABEL: @xor_nosignbit_ashr( +; CHECK-NEXT: [[T0:%.*]] = ashr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[R:%.*]] = xor i32 [[T0]], 8388352 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000 + %r = ashr i32 %t0, 8 + ret i32 %r +} + +define i32 @add_signbit_ashr(i32 %x) { +; CHECK-LABEL: @add_signbit_ashr( +; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], -65536 +; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T0]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 4294901760 ; 0xFFFF0000 + %r = ashr i32 %t0, 8 + ret i32 %r +} +define i32 @add_nosignbit_ashr(i32 %x) { +; CHECK-LABEL: @add_nosignbit_ashr( +; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], 2147418112 +; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T0]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 2147418112 ; 0x7FFF0000 + %r = ashr i32 %t0, 8 + ret i32 %r +} diff --git a/llvm/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll b/llvm/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll new file mode 100644 index 0000000..3bd7873 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll @@ -0,0 +1,308 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -S | FileCheck %s + +; shift left + +define i32 @and_signbit_select_shl(i32 %x, i1 %cond) { +; CHECK-LABEL: @and_signbit_select_shl( +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -16777216 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = shl i32 %t1, 8 + ret i32 %r +} +define i32 @and_nosignbit_select_shl(i32 %x, i1 %cond) { +; CHECK-LABEL: @and_nosignbit_select_shl( +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -16777216 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = shl i32 %t1, 8 + ret i32 %r +} + +define i32 @or_signbit_select_shl(i32 %x, i1 %cond) { +; CHECK-LABEL: @or_signbit_select_shl( +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], -16777216 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = shl i32 %t1, 8 + ret i32 %r +} +define i32 @or_nosignbit_select_shl(i32 %x, i1 %cond) { +; CHECK-LABEL: @or_nosignbit_select_shl( +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], -16777216 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = shl i32 %t1, 8 + ret i32 %r +} + +define i32 @xor_signbit_select_shl(i32 %x, i1 %cond) { +; CHECK-LABEL: @xor_signbit_select_shl( +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -16777216 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = shl i32 %t1, 8 + ret i32 %r +} +define i32 @xor_nosignbit_select_shl(i32 %x, i1 %cond) { +; CHECK-LABEL: @xor_nosignbit_select_shl( +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -16777216 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = shl i32 %t1, 8 + ret i32 %r +} + +define i32 @add_signbit_select_shl(i32 %x, i1 %cond) { +; CHECK-LABEL: @add_signbit_select_shl( +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -16777216 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = shl i32 %t1, 8 + ret i32 %r +} +define i32 @add_nosignbit_select_shl(i32 %x, i1 %cond) { +; CHECK-LABEL: @add_nosignbit_select_shl( +; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -16777216 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = shl i32 %t1, 8 + ret i32 %r +} + +; logical shift right + +define i32 @and_signbit_select_lshr(i32 %x, i1 %cond) { +; CHECK-LABEL: @and_signbit_select_lshr( +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 16776960 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = lshr i32 %t1, 8 + ret i32 %r +} +define i32 @and_nosignbit_select_lshr(i32 %x, i1 %cond) { +; CHECK-LABEL: @and_nosignbit_select_lshr( +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 8388352 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = lshr i32 %t1, 8 + ret i32 %r +} + +define i32 @or_signbit_select_lshr(i32 %x, i1 %cond) { +; CHECK-LABEL: @or_signbit_select_lshr( +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 16776960 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = lshr i32 %t1, 8 + ret i32 %r +} +define i32 @or_nosignbit_select_lshr(i32 %x, i1 %cond) { +; CHECK-LABEL: @or_nosignbit_select_lshr( +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 8388352 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = lshr i32 %t1, 8 + ret i32 %r +} + +define i32 @xor_signbit_select_lshr(i32 %x, i1 %cond) { +; CHECK-LABEL: @xor_signbit_select_lshr( +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 16776960 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = lshr i32 %t1, 8 + ret i32 %r +} +define i32 @xor_nosignbit_select_lshr(i32 %x, i1 %cond) { +; CHECK-LABEL: @xor_nosignbit_select_lshr( +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 8388352 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = lshr i32 %t1, 8 + ret i32 %r +} + +define i32 @add_signbit_select_lshr(i32 %x, i1 %cond) { +; CHECK-LABEL: @add_signbit_select_lshr( +; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], -65536 +; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]] +; CHECK-NEXT: [[R:%.*]] = lshr i32 [[T1]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = lshr i32 %t1, 8 + ret i32 %r +} +define i32 @add_nosignbit_select_lshr(i32 %x, i1 %cond) { +; CHECK-LABEL: @add_nosignbit_select_lshr( +; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], 2147418112 +; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]] +; CHECK-NEXT: [[R:%.*]] = lshr i32 [[T1]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = lshr i32 %t1, 8 + ret i32 %r +} + +; arithmetic shift right + +define i32 @and_signbit_select_ashr(i32 %x, i1 %cond) { +; CHECK-LABEL: @and_signbit_select_ashr( +; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -256 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = ashr i32 %t1, 8 + ret i32 %r +} +define i32 @and_nosignbit_select_ashr(i32 %x, i1 %cond) { +; CHECK-LABEL: @and_nosignbit_select_ashr( +; CHECK-NEXT: [[T0:%.*]] = and i32 [[X:%.*]], 2147418112 +; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]] +; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T1]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = and i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = ashr i32 %t1, 8 + ret i32 %r +} + +define i32 @or_signbit_select_ashr(i32 %x, i1 %cond) { +; CHECK-LABEL: @or_signbit_select_ashr( +; CHECK-NEXT: [[T0:%.*]] = or i32 [[X:%.*]], -65536 +; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]] +; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T1]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = ashr i32 %t1, 8 + ret i32 %r +} +define i32 @or_nosignbit_select_ashr(i32 %x, i1 %cond) { +; CHECK-LABEL: @or_nosignbit_select_ashr( +; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 8388352 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = or i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = ashr i32 %t1, 8 + ret i32 %r +} + +define i32 @xor_signbit_select_ashr(i32 %x, i1 %cond) { +; CHECK-LABEL: @xor_signbit_select_ashr( +; CHECK-NEXT: [[T0:%.*]] = xor i32 [[X:%.*]], -65536 +; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]] +; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T1]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = ashr i32 %t1, 8 + ret i32 %r +} +define i32 @xor_nosignbit_select_ashr(i32 %x, i1 %cond) { +; CHECK-LABEL: @xor_nosignbit_select_ashr( +; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 8388352 +; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = ashr i32 %t1, 8 + ret i32 %r +} + +define i32 @add_signbit_select_ashr(i32 %x, i1 %cond) { +; CHECK-LABEL: @add_signbit_select_ashr( +; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], -65536 +; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]] +; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T1]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 4294901760 ; 0xFFFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = ashr i32 %t1, 8 + ret i32 %r +} +define i32 @add_nosignbit_select_ashr(i32 %x, i1 %cond) { +; CHECK-LABEL: @add_nosignbit_select_ashr( +; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], 2147418112 +; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]] +; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T1]], 8 +; CHECK-NEXT: ret i32 [[R]] +; + %t0 = add i32 %x, 2147418112 ; 0x7FFF0000 + %t1 = select i1 %cond, i32 %t0, i32 %x + %r = ashr i32 %t1, 8 + ret i32 %r +} -- 2.7.4