From 4b62b3960ec405c6ed226a7763e0905c434cb2bb Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Fri, 6 Mar 2020 16:36:23 +0200 Subject: [PATCH] arc: Update tumaddsidi4 test. The test is using -O1 and, the macu instruction is generated by the combiner and not in the expand step. My previous "arc: Improve code gen for 64bit add/sub operations." is actually splitting the 64-bit add in the expand, leading to the impossibility to match the multiply and accumulate on 64 bit datum by the combiner, hence, the error. This patch is stepping up the optimization level which will generate the macu instruction at the expand time. xxxx-xx-xx Claudiu Zissulescu * gcc.target/arc/tumaddsidi4.c: Step-up optimization level. Signed-off-by: Claudiu Zissulescu --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/arc/tumaddsidi4.c | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 13da5a8..ea9bc42 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-06 Claudiu Zissulescu + + * gcc.target/arc/tumaddsidi4.c: Step-up optimization level. + 2020-03-06 Delia Burduv * gcc.target/arm/simd/bf16_vldn_1.c: New test. diff --git a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c index d5dc294..0298a24 100644 --- a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c +++ b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mcpu=archs -O1 -mmpy-option=plus_dmpy -w" } */ +/* { dg-options "-mcpu=archs -O2 -mmpy-option=plus_dmpy -w" } */ /* Check how we generate umaddsidi4 patterns. */ long a; @@ -11,4 +11,4 @@ void fn1(void) b = d * (long long)c + a; } -/* { dg-final { scan-assembler "macu 0,r" } } */ +/* { dg-final { scan-assembler "macu" } } */ -- 2.7.4