From 4b3518d50b30c4afb1f6e3500a4b26e0bb056a46 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Thu, 18 Nov 2021 22:15:09 -0800
Subject: [PATCH] [RISCV] Pre-commit test for D98932. NFC

---
 llvm/test/CodeGen/RISCV/sink-icmp.ll | 47 ++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/sink-icmp.ll

diff --git a/llvm/test/CodeGen/RISCV/sink-icmp.ll b/llvm/test/CodeGen/RISCV/sink-icmp.ll
new file mode 100644
index 0000000..409545c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/sink-icmp.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefixes=RV32 %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefixes=RV64 %s
+
+define signext i16 @func(i16* %a, i16* %b) {
+; RV32-LABEL: func:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    lh a0, 0(a0)
+; RV32-NEXT:    bltz a0, .LBB0_3
+; RV32-NEXT:  # %bb.1: # %.LBB0_1
+; RV32-NEXT:    seqz a1, a1
+; RV32-NEXT:    bnez a1, .LBB0_3
+; RV32-NEXT:  # %bb.2: # %.LBB0_2
+; RV32-NEXT:    ret
+; RV32-NEXT:  .LBB0_3: # %return
+; RV32-NEXT:    mv a0, zero
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: func:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    lh a0, 0(a0)
+; RV64-NEXT:    bltz a0, .LBB0_3
+; RV64-NEXT:  # %bb.1: # %.LBB0_1
+; RV64-NEXT:    seqz a1, a1
+; RV64-NEXT:    bnez a1, .LBB0_3
+; RV64-NEXT:  # %bb.2: # %.LBB0_2
+; RV64-NEXT:    ret
+; RV64-NEXT:  .LBB0_3: # %return
+; RV64-NEXT:    mv a0, zero
+; RV64-NEXT:    ret
+entry:
+  %0 = load i16, i16* %a
+  %cmp = icmp sgt i16 %0, -1
+  %tobool.not = icmp eq i16* %b, null
+  br i1 %cmp, label %.LBB0_1, label %return
+
+.LBB0_1:
+  br i1 %tobool.not, label %return, label %.LBB0_2
+
+.LBB0_2:
+  ret i16 %0
+
+return:
+  ret i16 0
+}
-- 
2.7.4