From 4b04d54206a5b7f549af9a2f0a9588ee8e933eb2 Mon Sep 17 00:00:00 2001 From: Alexander Pivovarov Date: Wed, 1 Sep 2021 16:26:51 -0500 Subject: [PATCH] [RISCV] Fix typo in RISCVSchedSiFive7.td Fix typo in "microarchitecure". Differential Revision: https://reviews.llvm.org/D109006 --- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index 75ca6ca..5b435fc 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -18,7 +18,7 @@ def SiFive7Model : SchedMachineModel { let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg]; } -// The SiFive7 microarchitecure has two pipelines: A and B. +// The SiFive7 microarchitecture has two pipelines: A and B. // Pipe A can handle memory, integer alu and vector operations. // Pipe B can handle integer alu, control flow, integer multiply and divide, // and floating point computation. -- 2.7.4