From 4a9dd7c39b197fc13eeb1d27ba97ecedc7c6602a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 5 Mar 2019 18:37:41 +0000 Subject: [PATCH] [X86] Enable 8-bit SHL to convert to LEA Differential Revision: https://reviews.llvm.org/D58870 llvm-svn: 355425 --- llvm/lib/Target/X86/X86InstrInfo.cpp | 4 ++++ llvm/lib/Target/X86/X86InstrShiftRotate.td | 2 +- llvm/test/CodeGen/X86/fast-isel-shift.ll | 4 ++-- llvm/test/CodeGen/X86/mul-constant-i8.ll | 12 ++++++------ 4 files changed, 13 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 01b1740..435e487 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -755,6 +755,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA( BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA); switch (MIOpc) { default: llvm_unreachable("Unreachable!"); + case X86::SHL8ri: case X86::SHL16ri: { unsigned ShAmt = MI.getOperand(2).getImm(); MIB.addReg(0).addImm(1ULL << ShAmt) @@ -918,6 +919,9 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, break; } + case X86::SHL8ri: + Is8BitOp = true; + LLVM_FALLTHROUGH; case X86::SHL16ri: { assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!"); unsigned ShAmt = getTruncatedShiftCount(MI, 2); diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td index 21a20c1..0853056 100644 --- a/llvm/lib/Target/X86/X86InstrShiftRotate.td +++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td @@ -30,11 +30,11 @@ def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), [(set GR64:$dst, (shl GR64:$src1, CL))]>; } // Uses = [CL], SchedRW +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), "shl{b}\t{$src2, $dst|$dst, $src2}", [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; -let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), "shl{w}\t{$src2, $dst|$dst, $src2}", [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, diff --git a/llvm/test/CodeGen/X86/fast-isel-shift.ll b/llvm/test/CodeGen/X86/fast-isel-shift.ll index 2aff7cf..243bb4ad 100644 --- a/llvm/test/CodeGen/X86/fast-isel-shift.ll +++ b/llvm/test/CodeGen/X86/fast-isel-shift.ll @@ -157,8 +157,8 @@ define i64 @ashr_i64(i64 %a, i64 %b) { define i8 @shl_imm1_i8(i8 %a) { ; CHECK-LABEL: shl_imm1_i8: ; CHECK: ## %bb.0: -; CHECK-NEXT: movl %edi, %eax -; CHECK-NEXT: shlb $1, %al +; CHECK-NEXT: ## kill: def $edi killed $edi def $rdi +; CHECK-NEXT: leal (,%rdi,2), %eax ; CHECK-NEXT: ## kill: def $al killed $al killed $eax ; CHECK-NEXT: retq %c = shl i8 %a, 1 diff --git a/llvm/test/CodeGen/X86/mul-constant-i8.ll b/llvm/test/CodeGen/X86/mul-constant-i8.ll index 43afd24..5a33888 100644 --- a/llvm/test/CodeGen/X86/mul-constant-i8.ll +++ b/llvm/test/CodeGen/X86/mul-constant-i8.ll @@ -36,8 +36,8 @@ define i8 @test_mul_by_3(i8 %x) { define i8 @test_mul_by_4(i8 %x) { ; X64-LABEL: test_mul_by_4: ; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: shlb $2, %al +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: leal (,%rdi,4), %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq %m = mul i8 %x, 4 @@ -82,8 +82,8 @@ define i8 @test_mul_by_7(i8 %x) { define i8 @test_mul_by_8(i8 %x) { ; X64-LABEL: test_mul_by_8: ; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: shlb $3, %al +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: leal (,%rdi,8), %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq %m = mul i8 %x, 8 @@ -449,8 +449,8 @@ define i8 @test_mul_by_73(i8 %x) { define i8 @test_mul_by_520(i8 %x) { ; X64-LABEL: test_mul_by_520: ; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: shlb $3, %al +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: leal (,%rdi,8), %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq %m = mul i8 %x, 520 -- 2.7.4