From 49abb980c5fafc75f10c2beb13c63a8b0f8bc44a Mon Sep 17 00:00:00 2001 From: Xiangliang Yu Date: Mon, 6 Mar 2017 15:27:51 +0800 Subject: [PATCH] drm/amdgpu/gfx8: move CE&DE meta data structure to vi_structs.h MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Because different HWs have different definition for CE & DE meta data, follow mqd design to move the structures to vi_structs.h. And change the prefix from amdgpu to vi as the structures is only for VI family. Signed-off-by: Xiangliang Yu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 16 ++--- drivers/gpu/drm/amd/amdgpu/vi.h | 112 ------------------------------- drivers/gpu/drm/amd/include/vi_structs.h | 106 +++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+), 120 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 248010b..5dcf8db 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -7284,15 +7284,15 @@ static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t c uint64_t ce_payload_addr; int cnt_ce; static union { - struct amdgpu_ce_ib_state regular; - struct amdgpu_ce_ib_state_chained_ib chained; + struct vi_ce_ib_state regular; + struct vi_ce_ib_state_chained_ib chained; } ce_payload = {}; if (ring->adev->virt.chained_ib_support) { - ce_payload_addr = csa_addr + offsetof(struct amdgpu_gfx_meta_data_chained_ib, ce_payload); + ce_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload); cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2; } else { - ce_payload_addr = csa_addr + offsetof(struct amdgpu_gfx_meta_data, ce_payload); + ce_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, ce_payload); cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2; } @@ -7311,20 +7311,20 @@ static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring, uint64_t c uint64_t de_payload_addr, gds_addr; int cnt_de; static union { - struct amdgpu_de_ib_state regular; - struct amdgpu_de_ib_state_chained_ib chained; + struct vi_de_ib_state regular; + struct vi_de_ib_state_chained_ib chained; } de_payload = {}; gds_addr = csa_addr + 4096; if (ring->adev->virt.chained_ib_support) { de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr); de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr); - de_payload_addr = csa_addr + offsetof(struct amdgpu_gfx_meta_data_chained_ib, de_payload); + de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload); cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2; } else { de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr); de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr); - de_payload_addr = csa_addr + offsetof(struct amdgpu_gfx_meta_data, de_payload); + de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload); cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2; } diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h index 719587b..575d7ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.h +++ b/drivers/gpu/drm/amd/amdgpu/vi.h @@ -28,116 +28,4 @@ void vi_srbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); int vi_set_ip_blocks(struct amdgpu_device *adev); -struct amdgpu_ce_ib_state -{ - uint32_t ce_ib_completion_status; - uint32_t ce_constegnine_count; - uint32_t ce_ibOffset_ib1; - uint32_t ce_ibOffset_ib2; -}; /* Total of 4 DWORD */ - -struct amdgpu_de_ib_state -{ - uint32_t ib_completion_status; - uint32_t de_constEngine_count; - uint32_t ib_offset_ib1; - uint32_t ib_offset_ib2; - uint32_t preamble_begin_ib1; - uint32_t preamble_begin_ib2; - uint32_t preamble_end_ib1; - uint32_t preamble_end_ib2; - uint32_t draw_indirect_baseLo; - uint32_t draw_indirect_baseHi; - uint32_t disp_indirect_baseLo; - uint32_t disp_indirect_baseHi; - uint32_t gds_backup_addrlo; - uint32_t gds_backup_addrhi; - uint32_t index_base_addrlo; - uint32_t index_base_addrhi; - uint32_t sample_cntl; -}; /* Total of 17 DWORD */ - -struct amdgpu_ce_ib_state_chained_ib -{ - /* section of non chained ib part */ - uint32_t ce_ib_completion_status; - uint32_t ce_constegnine_count; - uint32_t ce_ibOffset_ib1; - uint32_t ce_ibOffset_ib2; - - /* section of chained ib */ - uint32_t ce_chainib_addrlo_ib1; - uint32_t ce_chainib_addrlo_ib2; - uint32_t ce_chainib_addrhi_ib1; - uint32_t ce_chainib_addrhi_ib2; - uint32_t ce_chainib_size_ib1; - uint32_t ce_chainib_size_ib2; -}; /* total 10 DWORD */ - -struct amdgpu_de_ib_state_chained_ib -{ - /* section of non chained ib part */ - uint32_t ib_completion_status; - uint32_t de_constEngine_count; - uint32_t ib_offset_ib1; - uint32_t ib_offset_ib2; - - /* section of chained ib */ - uint32_t chain_ib_addrlo_ib1; - uint32_t chain_ib_addrlo_ib2; - uint32_t chain_ib_addrhi_ib1; - uint32_t chain_ib_addrhi_ib2; - uint32_t chain_ib_size_ib1; - uint32_t chain_ib_size_ib2; - - /* section of non chained ib part */ - uint32_t preamble_begin_ib1; - uint32_t preamble_begin_ib2; - uint32_t preamble_end_ib1; - uint32_t preamble_end_ib2; - - /* section of chained ib */ - uint32_t chain_ib_pream_addrlo_ib1; - uint32_t chain_ib_pream_addrlo_ib2; - uint32_t chain_ib_pream_addrhi_ib1; - uint32_t chain_ib_pream_addrhi_ib2; - - /* section of non chained ib part */ - uint32_t draw_indirect_baseLo; - uint32_t draw_indirect_baseHi; - uint32_t disp_indirect_baseLo; - uint32_t disp_indirect_baseHi; - uint32_t gds_backup_addrlo; - uint32_t gds_backup_addrhi; - uint32_t index_base_addrlo; - uint32_t index_base_addrhi; - uint32_t sample_cntl; -}; /* Total of 27 DWORD */ - -struct amdgpu_gfx_meta_data -{ - /* 4 DWORD, address must be 4KB aligned */ - struct amdgpu_ce_ib_state ce_payload; - uint32_t reserved1[60]; - /* 17 DWORD, address must be 64B aligned */ - struct amdgpu_de_ib_state de_payload; - /* PFP IB base address which get pre-empted */ - uint32_t DeIbBaseAddrLo; - uint32_t DeIbBaseAddrHi; - uint32_t reserved2[941]; -}; /* Total of 4K Bytes */ - -struct amdgpu_gfx_meta_data_chained_ib -{ - /* 10 DWORD, address must be 4KB aligned */ - struct amdgpu_ce_ib_state_chained_ib ce_payload; - uint32_t reserved1[54]; - /* 27 DWORD, address must be 64B aligned */ - struct amdgpu_de_ib_state_chained_ib de_payload; - /* PFP IB base address which get pre-empted */ - uint32_t DeIbBaseAddrLo; - uint32_t DeIbBaseAddrHi; - uint32_t reserved2[931]; -}; /* Total of 4K Bytes */ - #endif diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h index 65cfacd..b68f8ef 100644 --- a/drivers/gpu/drm/amd/include/vi_structs.h +++ b/drivers/gpu/drm/amd/include/vi_structs.h @@ -414,4 +414,110 @@ struct vi_mqd { uint32_t queue_doorbell_id15; }; +struct vi_ce_ib_state { + uint32_t ce_ib_completion_status; + uint32_t ce_constegnine_count; + uint32_t ce_ibOffset_ib1; + uint32_t ce_ibOffset_ib2; +}; /* Total of 4 DWORD */ + +struct vi_de_ib_state { + uint32_t ib_completion_status; + uint32_t de_constEngine_count; + uint32_t ib_offset_ib1; + uint32_t ib_offset_ib2; + uint32_t preamble_begin_ib1; + uint32_t preamble_begin_ib2; + uint32_t preamble_end_ib1; + uint32_t preamble_end_ib2; + uint32_t draw_indirect_baseLo; + uint32_t draw_indirect_baseHi; + uint32_t disp_indirect_baseLo; + uint32_t disp_indirect_baseHi; + uint32_t gds_backup_addrlo; + uint32_t gds_backup_addrhi; + uint32_t index_base_addrlo; + uint32_t index_base_addrhi; + uint32_t sample_cntl; +}; /* Total of 17 DWORD */ + +struct vi_ce_ib_state_chained_ib { + /* section of non chained ib part */ + uint32_t ce_ib_completion_status; + uint32_t ce_constegnine_count; + uint32_t ce_ibOffset_ib1; + uint32_t ce_ibOffset_ib2; + + /* section of chained ib */ + uint32_t ce_chainib_addrlo_ib1; + uint32_t ce_chainib_addrlo_ib2; + uint32_t ce_chainib_addrhi_ib1; + uint32_t ce_chainib_addrhi_ib2; + uint32_t ce_chainib_size_ib1; + uint32_t ce_chainib_size_ib2; +}; /* total 10 DWORD */ + +struct vi_de_ib_state_chained_ib { + /* section of non chained ib part */ + uint32_t ib_completion_status; + uint32_t de_constEngine_count; + uint32_t ib_offset_ib1; + uint32_t ib_offset_ib2; + + /* section of chained ib */ + uint32_t chain_ib_addrlo_ib1; + uint32_t chain_ib_addrlo_ib2; + uint32_t chain_ib_addrhi_ib1; + uint32_t chain_ib_addrhi_ib2; + uint32_t chain_ib_size_ib1; + uint32_t chain_ib_size_ib2; + + /* section of non chained ib part */ + uint32_t preamble_begin_ib1; + uint32_t preamble_begin_ib2; + uint32_t preamble_end_ib1; + uint32_t preamble_end_ib2; + + /* section of chained ib */ + uint32_t chain_ib_pream_addrlo_ib1; + uint32_t chain_ib_pream_addrlo_ib2; + uint32_t chain_ib_pream_addrhi_ib1; + uint32_t chain_ib_pream_addrhi_ib2; + + /* section of non chained ib part */ + uint32_t draw_indirect_baseLo; + uint32_t draw_indirect_baseHi; + uint32_t disp_indirect_baseLo; + uint32_t disp_indirect_baseHi; + uint32_t gds_backup_addrlo; + uint32_t gds_backup_addrhi; + uint32_t index_base_addrlo; + uint32_t index_base_addrhi; + uint32_t sample_cntl; +}; /* Total of 27 DWORD */ + +struct vi_gfx_meta_data { + /* 4 DWORD, address must be 4KB aligned */ + struct vi_ce_ib_state ce_payload; + uint32_t reserved1[60]; + /* 17 DWORD, address must be 64B aligned */ + struct vi_de_ib_state de_payload; + /* PFP IB base address which get pre-empted */ + uint32_t DeIbBaseAddrLo; + uint32_t DeIbBaseAddrHi; + uint32_t reserved2[941]; +}; /* Total of 4K Bytes */ + +struct vi_gfx_meta_data_chained_ib { + /* 10 DWORD, address must be 4KB aligned */ + struct vi_ce_ib_state_chained_ib ce_payload; + uint32_t reserved1[54]; + /* 27 DWORD, address must be 64B aligned */ + struct vi_de_ib_state_chained_ib de_payload; + /* PFP IB base address which get pre-empted */ + uint32_t DeIbBaseAddrLo; + uint32_t DeIbBaseAddrHi; + uint32_t reserved2[931]; +}; /* Total of 4K Bytes */ + #endif /* VI_STRUCTS_H_ */ -- 2.7.4