From 4978db6b9ed47538b5ab8094bb4017d47d46b5ac Mon Sep 17 00:00:00 2001 From: Mark Janes Date: Tue, 7 Feb 2023 14:16:33 -0800 Subject: [PATCH] intel: use generated workaround helpers for Wa_1409600907 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Wa_1409600907 was enabled for gen12+. It should not be applied for platforms after gen12.0. Use generated helpers to ensure application to all relevant platforms. Reviewed-by: Tapani Pälli Part-of: --- src/gallium/drivers/iris/iris_state.c | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 2 +- src/intel/vulkan/gfx8_cmd_buffer.c | 2 ++ src/intel/vulkan_hasvk/genX_cmd_buffer.c | 5 ----- 4 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index d98395b..31b5eb6 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -8424,7 +8424,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; } - if (GFX_VER >= 12 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) { + if (INTEL_NEEDS_WA_1409600907 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) { /* Wa_1409600907: * * "PIPE_CONTROL with Depth Stall Enable bit must be set diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index d28852d..875c32a 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1668,10 +1668,10 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, pipe.RenderTargetCacheFlushEnable = bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT; +#if INTEL_NEEDS_WA_1409600907 /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must * be set with any PIPE_CONTROL with Depth Flush Enable bit set. */ -#if GFX_VER >= 12 pipe.DepthStallEnable = pipe.DepthCacheFlushEnable || (bits & ANV_PIPE_DEPTH_STALL_BIT); #else diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c index a6fe630..baebfe8 100644 --- a/src/intel/vulkan/gfx8_cmd_buffer.c +++ b/src/intel/vulkan/gfx8_cmd_buffer.c @@ -55,7 +55,9 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) pc.RenderTargetCacheFlushEnable = true; #if GFX_VER >= 12 pc.TileCacheFlushEnable = true; +#endif +#if INTEL_NEEDS_WA_1409600907 /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must * be set with any PIPE_CONTROL with Depth Flush Enable bit set. */ diff --git a/src/intel/vulkan_hasvk/genX_cmd_buffer.c b/src/intel/vulkan_hasvk/genX_cmd_buffer.c index 37853f3..ac01183 100644 --- a/src/intel/vulkan_hasvk/genX_cmd_buffer.c +++ b/src/intel/vulkan_hasvk/genX_cmd_buffer.c @@ -1727,11 +1727,6 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, pipe.RenderTargetCacheFlushEnable = bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT; - /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must - * be set with any PIPE_CONTROL with Depth Flush Enable bit set. - */ - pipe.DepthStallEnable = bits & ANV_PIPE_DEPTH_STALL_BIT; - pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT; #if GFX_VER == 8 /* From Broadwell PRM, volume 2a: -- 2.7.4