From 495b653480238d692d814dde50469441b83adb4b Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Fri, 17 Feb 2023 16:25:01 -0800 Subject: [PATCH] [RISCV] Add missing plumbing and tests for zfa Experimental support for the zfa extension was recently added in https://reviews.llvm.org/D141984. A couple of the normal test changes and clang plumbing got missed in that change. This commit updates the usual suspects. Differential Revision: https://reviews.llvm.org/D144288 --- clang/test/Preprocessor/riscv-target-features.c | 8 ++++++++ llvm/lib/Support/RISCVISAInfo.cpp | 3 +++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++ llvm/test/MC/RISCV/attribute-arch.s | 3 +++ 4 files changed, 18 insertions(+) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index da87e6b..f965f1e 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -506,3 +506,11 @@ // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64izifencei2p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZIFENCEI-EXT %s // CHECK-ZIFENCEI-EXT: __riscv_zifencei 2000000{{$}} + +// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv32izfa0p1 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s +// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv64izfa0p1 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s +// CHECK-ZFA-EXT: __riscv_zfa 1000{{$}} diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index b3f67f4..0928ad5 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -126,6 +126,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zcb", RISCVExtensionVersion{1, 0}}, {"zcd", RISCVExtensionVersion{1, 0}}, {"zcf", RISCVExtensionVersion{1, 0}}, + {"zfa", RISCVExtensionVersion{0, 1}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"zawrs", RISCVExtensionVersion{1, 0}}, {"ztso", RISCVExtensionVersion{0, 1}}, @@ -836,6 +837,7 @@ static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"}; static const char *ImpliedExtsZvfh[] = {"zve32f"}; static const char *ImpliedExtsXTHeadVdot[] = {"v"}; static const char *ImpliedExtsZcb[] = {"zca"}; +static const char *ImpliedExtsZfa[] = {"f"}; struct ImpliedExtsEntry { StringLiteral Name; @@ -854,6 +856,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = { {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}}, {{"zcb"}, {ImpliedExtsZcb}}, {{"zdinx"}, {ImpliedExtsZdinx}}, + {{"zfa"}, {ImpliedExtsZfa}}, {{"zfh"}, {ImpliedExtsZfh}}, {{"zfhmin"}, {ImpliedExtsZfhmin}}, {{"zhinx"}, {ImpliedExtsZhinx}}, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 24c7409..23a8fd4 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -48,6 +48,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s ; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s ; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s @@ -103,6 +104,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s ; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s ; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s ; CHECK: .attribute 4, 16 @@ -153,6 +155,7 @@ ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0" ; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0" ; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0" +; RV32ZFA: .attribute 5, "rv32i2p0_f2p0_zfa0p1" ; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0" @@ -207,6 +210,7 @@ ; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0" ; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0" ; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0" +; RV64ZFA: .attribute 5, "rv64i2p0_f2p0_zfa0p1" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 3f8e261..7856dcf 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -199,3 +199,6 @@ .attribute arch, "rv32izifencei2p0" # CHECK: attribute 5, "rv32i2p0_zifencei2p0" + +.attribute arch, "rv32izfa0p1" +# CHECK: attribute 5, "rv32i2p0_f2p0_zfa0p1" -- 2.7.4