From 492d0eab894f488b42d595d3bdc0c199fa624459 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sun, 10 Apr 2022 08:37:44 -0400 Subject: [PATCH] AArch64/GlobalISel: Remove IR section from a test --- .../CodeGen/AArch64/GlobalISel/select-zextload.mir | 110 +++++++-------------- 1 file changed, 35 insertions(+), 75 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir index ea44159..4e746ed 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir @@ -1,77 +1,37 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @zextload_s32_from_s16(i16 *%addr) { ret void } - define void @zextload_s32_from_s16_not_combined(i16 *%addr) { ret void } - - define i64 @i32_to_i64(i32* %ptr) { - %ld = load i32, i32* %ptr, align 4 - %val = zext i32 %ld to i64 - ret i64 %val - } - - define i64 @i16_to_i64(i16* %ptr) { - %ld = load i16, i16* %ptr, align 2 - %val = zext i16 %ld to i64 - ret i64 %val - } - - define i64 @i8_to_i64(i8* %ptr) { - %ld = load i8, i8* %ptr, align 1 - %val = zext i8 %ld to i64 - ret i64 %val - } - - define i32 @i8_to_i32(i8* %ptr) { - %ld = load i8, i8* %ptr, align 1 - %val = zext i8 %ld to i32 - ret i32 %val - } - - define i32 @i16_to_i32(i16* %ptr) { - %ld = load i16, i16* %ptr, align 2 - %val = zext i16 %ld to i32 - ret i32 %val - } - -... - --- name: zextload_s32_from_s16 legalized: true regBankSelected: true - body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: zextload_s32_from_s16 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr) - ; CHECK: $w0 = COPY [[LDRHHui]] + ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $w0 = COPY [[LDRHHui]] %0:gpr(p0) = COPY $x0 - %1:gpr(s32) = G_ZEXTLOAD %0 :: (load (s16) from %ir.addr) + %1:gpr(s32) = G_ZEXTLOAD %0 :: (load (s16)) $w0 = COPY %1(s32) ... --- name: zextload_s32_from_s16_not_combined legalized: true regBankSelected: true - body: | bb.0: liveins: $x0 ; CHECK-LABEL: name: zextload_s32_from_s16_not_combined ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr) - ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]] - ; CHECK: $w0 = COPY [[COPY1]] + ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]] + ; CHECK-NEXT: $w0 = COPY [[COPY1]] %0:gpr(p0) = COPY $x0 - %1:gpr(s16) = G_LOAD %0 :: (load (s16) from %ir.addr) + %1:gpr(s16) = G_LOAD %0 :: (load (s16)) %2:gpr(s32) = G_ZEXT %1 $w0 = COPY %2(s32) ... @@ -80,17 +40,17 @@ name: i32_to_i64 legalized: true regBankSelected: true body: | - bb.1 (%ir-block.0): + bb.0: liveins: $x0 ; CHECK-LABEL: name: i32_to_i64 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32) from %ir.ptr) - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_32 - ; CHECK: $x0 = COPY [[SUBREG_TO_REG]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32)) + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_32 + ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(p0) = COPY $x0 - %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s32) from %ir.ptr) + %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s32)) $x0 = COPY %2(s64) RET_ReallyLR implicit $x0 @@ -100,17 +60,17 @@ name: i16_to_i64 legalized: true regBankSelected: true body: | - bb.1 (%ir-block.0): + bb.0: liveins: $x0 ; CHECK-LABEL: name: i16_to_i64 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.ptr) - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRHHui]], %subreg.sub_32 - ; CHECK: $x0 = COPY [[SUBREG_TO_REG]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRHHui]], %subreg.sub_32 + ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(p0) = COPY $x0 - %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.ptr) + %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s16)) $x0 = COPY %2(s64) RET_ReallyLR implicit $x0 @@ -120,17 +80,17 @@ name: i8_to_i64 legalized: true regBankSelected: true body: | - bb.1 (%ir-block.0): + bb.0: liveins: $x0 ; CHECK-LABEL: name: i8_to_i64 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.ptr) - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32 - ; CHECK: $x0 = COPY [[SUBREG_TO_REG]] - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32 + ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(p0) = COPY $x0 - %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.ptr) + %2:gpr(s64) = G_ZEXTLOAD %0(p0) :: (load (s8)) $x0 = COPY %2(s64) RET_ReallyLR implicit $x0 @@ -140,16 +100,16 @@ name: i8_to_i32 legalized: true regBankSelected: true body: | - bb.1 (%ir-block.0): + bb.0: liveins: $x0 ; CHECK-LABEL: name: i8_to_i32 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.ptr) - ; CHECK: $w0 = COPY [[LDRBBui]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8)) + ; CHECK-NEXT: $w0 = COPY [[LDRBBui]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(p0) = COPY $x0 - %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.ptr) + %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s8)) $w0 = COPY %2(s32) RET_ReallyLR implicit $w0 @@ -159,16 +119,16 @@ name: i16_to_i32 legalized: true regBankSelected: true body: | - bb.1 (%ir-block.0): + bb.0: liveins: $x0 ; CHECK-LABEL: name: i16_to_i32 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 - ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.ptr) - ; CHECK: $w0 = COPY [[LDRHHui]] - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16)) + ; CHECK-NEXT: $w0 = COPY [[LDRHHui]] + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %0:gpr(p0) = COPY $x0 - %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.ptr) + %2:gpr(s32) = G_ZEXTLOAD %0(p0) :: (load (s16)) $w0 = COPY %2(s32) RET_ReallyLR implicit $w0 -- 2.7.4