From 491d11baf3333bec5a92ae02828e86cd8f72c55c Mon Sep 17 00:00:00 2001 From: alalaw01 Date: Wed, 12 Nov 2014 18:51:53 +0000 Subject: [PATCH] Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips endianness gcc/: * config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices. * config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_index. (aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to... (aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these. (aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New. (aarch64_types_getlane_qualifiers): Rename to... (aarch64_types_binop_imm_qualifiers): ...this. (TYPES_SHIFTIMM): Follow renaming. (TYPES_GETLANE): Rename to... (TYPE_GETREG): ...this. (aarch64_types_setlane_qualifiers): Rename to... (aarch64_type_ternop_imm_qualifiers): ...this. (TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming. (TYPES_SETLANE): Follow renaming above, and rename self to... (TYPE_SETREG): ...this. (enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX. (aarch64_simd_expand_args): Add range check and endianness-flip. (aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index. * config/aarch64/aarch64-simd.md (aarch64_sqdmulh_lane_internal *2): Rename to... (aarch64_sqdmulh_lane): ...this, and remove lane bounds check. (aarch64_sqdmulh_lane *2, aarch64_sqrdmulh_lane *2): Delete. (aarch64_sqdmulh_laneq_internal): Rename to... (aarch64_sqdmulh_lane): ...this. (aarch64_sqdmll_lane_internal *2): Rename to... (aarch64_sqdmll_lane): ...this. (aarch64_sqdmll_laneq_internal *2): Rename to... (aarch64_sqdmll_laneq): ...this. (aarch64_sqdmull_lane_internal *2): Rename to... (aarch64_sqdmull_lane): ...this. (aarch64_sqdmull_laneq_internal *2): Rename to... (aarch64_sqdmull_laneq): ...this. (aarch64_sqdmulh_laneq, aarch64_sqrdmulh_laneq, (aarch64_sqdmlal_lane, aarch64_sqdmlal_laneq, aarch64_sqdmlsl_lane, aarch64_sqdmlsl_laneq, aarch64_sqdmull_lane, aarch64_sqdmull_laneq): Delete. (aarch64_sqdmlal2_lane, aarch64_sqdmlal2_laneq, aarch64_sqdmlsl2_lane, aarch64_sqdmlsl2_laneq, aarch64_sqdmull2_lane, aarch64_sqdmull2_laneq): Remove bounds check and lane flip. * config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane, get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi, set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG. (sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq, sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow renaming of TERNOP_LANE to QUADOP_LANE. (sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq, sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set qualifiers to TERNOP_LANE. gcc/testsuite/: * gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test. * gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise. * gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217440 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 69 ++++++ gcc/config/aarch64/aarch64-builtins.c | 46 ++-- gcc/config/aarch64/aarch64-simd-builtins.def | 66 +++--- gcc/config/aarch64/aarch64-simd.md | 231 ++------------------- gcc/config/aarch64/aarch64.c | 2 +- gcc/testsuite/ChangeLog | 53 +++++ .../aarch64/simd/vqdmlal_high_lane_s16_indices_1.c | 21 ++ .../aarch64/simd/vqdmlal_high_lane_s32_indices_1.c | 21 ++ .../simd/vqdmlal_high_laneq_s16_indices_1.c | 22 ++ .../simd/vqdmlal_high_laneq_s32_indices_1.c | 22 ++ .../aarch64/simd/vqdmlal_lane_s16_indices_1.c | 20 ++ .../aarch64/simd/vqdmlal_lane_s32_indices_1.c | 20 ++ .../aarch64/simd/vqdmlal_laneq_s16_indices_1.c | 21 ++ .../aarch64/simd/vqdmlal_laneq_s32_indices_1.c | 21 ++ .../aarch64/simd/vqdmlalh_lane_s16_indices_1.c | 17 ++ .../aarch64/simd/vqdmlals_lane_s32_indices_1.c | 17 ++ .../aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c | 21 ++ .../aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c | 21 ++ .../simd/vqdmlsl_high_laneq_s16_indices_1.c | 22 ++ .../simd/vqdmlsl_high_laneq_s32_indices_1.c | 22 ++ .../aarch64/simd/vqdmlsl_lane_s16_indices_1.c | 20 ++ .../aarch64/simd/vqdmlsl_lane_s32_indices_1.c | 20 ++ .../aarch64/simd/vqdmlsl_laneq_s16_indices_1.c | 21 ++ .../aarch64/simd/vqdmlsl_laneq_s32_indices_1.c | 21 ++ .../aarch64/simd/vqdmlslh_lane_s16_indices_1.c | 17 ++ .../aarch64/simd/vqdmlsls_lane_s32_indices_1.c | 18 ++ .../aarch64/simd/vqdmulh_lane_s16_indices_1.c | 17 ++ .../aarch64/simd/vqdmulh_lane_s32_indices_1.c | 17 ++ .../aarch64/simd/vqdmulh_laneq_s16_indices_1.c | 19 ++ .../aarch64/simd/vqdmulh_laneq_s32_indices_1.c | 19 ++ .../aarch64/simd/vqdmulhh_lane_s16_indices_1.c | 16 ++ .../aarch64/simd/vqdmulhq_lane_s16_indices_1.c | 18 ++ .../aarch64/simd/vqdmulhq_lane_s32_indices_1.c | 18 ++ .../aarch64/simd/vqdmulhq_laneq_s16_indices_1.c | 20 ++ .../aarch64/simd/vqdmulhq_laneq_s32_indices_1.c | 20 ++ .../aarch64/simd/vqdmulhs_lane_s32_indices_1.c | 16 ++ .../aarch64/simd/vqdmull_high_lane_s16_indices_1.c | 18 ++ .../aarch64/simd/vqdmull_high_lane_s32_indices_1.c | 18 ++ .../simd/vqdmull_high_laneq_s16_indices_1.c | 20 ++ .../simd/vqdmull_high_laneq_s32_indices_1.c | 20 ++ .../aarch64/simd/vqdmull_lane_s16_indices_1.c | 17 ++ .../aarch64/simd/vqdmull_lane_s32_indices_1.c | 17 ++ .../aarch64/simd/vqdmull_laneq_s16_indices_1.c | 19 ++ .../aarch64/simd/vqdmull_laneq_s32_indices_1.c | 19 ++ .../aarch64/simd/vqdmullh_lane_s16_indices_1.c | 16 ++ .../aarch64/simd/vqdmulls_lane_s32_indices_1.c | 16 ++ .../aarch64/simd/vqrdmulh_lane_s16_indices_1.c | 17 ++ .../aarch64/simd/vqrdmulh_lane_s32_indices_1.c | 17 ++ .../aarch64/simd/vqrdmulh_laneq_s16_indices_1.c | 19 ++ .../aarch64/simd/vqrdmulh_laneq_s32_indices_1.c | 19 ++ .../aarch64/simd/vqrdmulhh_lane_s16_indices_1.c | 16 ++ .../aarch64/simd/vqrdmulhq_lane_s16_indices_1.c | 18 ++ .../aarch64/simd/vqrdmulhq_lane_s32_indices_1.c | 18 ++ .../aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c | 20 ++ .../aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c | 20 ++ .../aarch64/simd/vqrdmulhs_lane_s32_indices_1.c | 16 ++ 56 files changed, 1148 insertions(+), 264 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 320c94d..2eb6f35 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,72 @@ +2014-11-12 Alan Lawrence + + * config/aarch64/aarch64.c (aarch64_simd_lane_bounds): Display indices. + + * config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add + qualifier_lane_index. + (aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): Rename to... + (aarch64_types_quadop_lane_qualifiers, TYPES_QUADOP_LANE): ...these. + (aarch64_types_ternop_lane_qualifiers, TYPES_TERNOP_LANE): New. + + (aarch64_types_getlane_qualifiers): Rename to... + (aarch64_types_binop_imm_qualifiers): ...this. + (TYPES_SHIFTIMM): Follow renaming. + (TYPES_GETLANE): Rename to... + (TYPE_GETREG): ...this. + + (aarch64_types_setlane_qualifiers): Rename to... + (aarch64_type_ternop_imm_qualifiers): ...this. + (TYPES_SHIFTINSERT, TYPES_SHIFTACC): Follow renaming. + (TYPES_SETLANE): Follow renaming above, and rename self to... + (TYPE_SETREG): ...this. + + (enum builtin_simd_arg): Add SIMD_ARG_LANE_INDEX. + (aarch64_simd_expand_args): Add range check and endianness-flip. + + (aarch64_simd_expand_builtin): Add mapping for qualifier_lane_index. + + * config/aarch64/aarch64-simd.md + (aarch64_sqdmulh_lane_internal *2): Rename to... + (aarch64_sqdmulh_lane): ...this, and remove lane bounds check. + (aarch64_sqdmulh_lane *2, aarch64_sqrdmulh_lane *2): Delete. + + (aarch64_sqdmulh_laneq_internal): Rename to... + (aarch64_sqdmulh_lane): ...this. + + (aarch64_sqdmll_lane_internal *2): Rename to... + (aarch64_sqdmll_lane): ...this. + + (aarch64_sqdmll_laneq_internal *2): Rename to... + (aarch64_sqdmll_laneq): ...this. + + (aarch64_sqdmull_lane_internal *2): Rename to... + (aarch64_sqdmull_lane): ...this. + + (aarch64_sqdmull_laneq_internal *2): Rename to... + (aarch64_sqdmull_laneq): ...this. + + (aarch64_sqdmulh_laneq, aarch64_sqrdmulh_laneq, + (aarch64_sqdmlal_lane, aarch64_sqdmlal_laneq, + aarch64_sqdmlsl_lane, aarch64_sqdmlsl_laneq, + aarch64_sqdmull_lane, aarch64_sqdmull_laneq): Delete. + + (aarch64_sqdmlal2_lane, aarch64_sqdmlal2_laneq, + aarch64_sqdmlsl2_lane, aarch64_sqdmlsl2_laneq, + aarch64_sqdmull2_lane, aarch64_sqdmull2_laneq): Remove + bounds check and lane flip. + + * config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane, + get_dregoi, get_dregci, getdregxi, get_qregoi,get_qregci, get_qregxi, + set_qregoi, set_qregci, set_qregxi): Change qualifiers to GETREG. + + (sqdmlal_lane, sqdmlsl_lane, sqdmlal_laneq, sqdmlsl_laneq, + sqdmlal2_lane, sqdmlsl2_lane, sqdmlal2_laneq, sqdmlsl2_laneq): Follow + renaming of TERNOP_LANE to QUADOP_LANE. + + (sqdmull_lane, sqdmull_laneq, sqdmull2_lane, sqdmull2_laneq, + sqdmulh_lane, sqdmulh_laneq, sqrdmulh_lane, sqrdmulh_laneq): Set + qualifiers to TERNOP_LANE. + 2014-11-12 Tobias Burnus * Makefile.in (CLOOGLIBS, CLOOGINC): Remove. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 239c68e..87962f1 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -114,7 +114,9 @@ enum aarch64_type_qualifiers /* qualifier_const | qualifier_pointer | qualifier_map_mode */ qualifier_const_pointer_map_mode = 0x86, /* Polynomial types. */ - qualifier_poly = 0x100 + qualifier_poly = 0x100, + /* Lane indices - must be in range, and flipped for bigendian. */ + qualifier_lane_index = 0x200 }; typedef struct @@ -167,22 +169,26 @@ aarch64_types_ternop_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_none, qualifier_none }; #define TYPES_TERNOP (aarch64_types_ternop_qualifiers) static enum aarch64_type_qualifiers +aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_lane_index }; +#define TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers) +static enum aarch64_type_qualifiers aarch64_types_ternopu_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, qualifier_unsigned }; #define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers) static enum aarch64_type_qualifiers -aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] +aarch64_types_quadop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_none, - qualifier_none, qualifier_immediate }; -#define TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers) + qualifier_none, qualifier_lane_index }; +#define TYPES_QUADOP_LANE (aarch64_types_quadop_lane_qualifiers) static enum aarch64_type_qualifiers -aarch64_types_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS] +aarch64_types_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_immediate }; -#define TYPES_GETLANE (aarch64_types_getlane_qualifiers) -#define TYPES_SHIFTIMM (aarch64_types_getlane_qualifiers) +#define TYPES_GETREG (aarch64_types_binop_imm_qualifiers) +#define TYPES_SHIFTIMM (aarch64_types_binop_imm_qualifiers) static enum aarch64_type_qualifiers aarch64_types_shift_to_unsigned_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_none, qualifier_immediate }; @@ -193,11 +199,11 @@ aarch64_types_unsigned_shift_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define TYPES_USHIFTIMM (aarch64_types_unsigned_shift_qualifiers) static enum aarch64_type_qualifiers -aarch64_types_setlane_qualifiers[SIMD_MAX_BUILTIN_ARGS] +aarch64_types_ternop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate }; -#define TYPES_SETLANE (aarch64_types_setlane_qualifiers) -#define TYPES_SHIFTINSERT (aarch64_types_setlane_qualifiers) -#define TYPES_SHIFTACC (aarch64_types_setlane_qualifiers) +#define TYPES_SETREG (aarch64_types_ternop_imm_qualifiers) +#define TYPES_SHIFTINSERT (aarch64_types_ternop_imm_qualifiers) +#define TYPES_SHIFTACC (aarch64_types_ternop_imm_qualifiers) static enum aarch64_type_qualifiers aarch64_types_unsigned_shiftacc_qualifiers[SIMD_MAX_BUILTIN_ARGS] @@ -853,6 +859,7 @@ typedef enum { SIMD_ARG_COPY_TO_REG, SIMD_ARG_CONSTANT, + SIMD_ARG_LANE_INDEX, SIMD_ARG_STOP } builtin_simd_arg; @@ -896,6 +903,19 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval, op[argc] = copy_to_mode_reg (mode[argc], op[argc]); break; + case SIMD_ARG_LANE_INDEX: + /* Must be a previous operand into which this is an index. */ + gcc_assert (argc > 0); + if (CONST_INT_P (op[argc])) + { + enum machine_mode vmode = mode[argc - 1]; + aarch64_simd_lane_bounds (op[argc], + 0, GET_MODE_NUNITS (vmode)); + /* Keep to GCC-vector-extension lane indices in the RTL. */ + op[argc] = GEN_INT (ENDIAN_LANE_N (vmode, INTVAL (op[argc]))); + } + /* Fall through - if the lane index isn't a constant then + the next case will error. */ case SIMD_ARG_CONSTANT: if (!(*insn_data[icode].operand[argc + have_retval].predicate) (op[argc], mode[argc])) @@ -1004,7 +1024,9 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target) int operands_k = k - is_void; int expr_args_k = k - 1; - if (d->qualifiers[qualifiers_k] & qualifier_immediate) + if (d->qualifiers[qualifiers_k] & qualifier_lane_index) + args[k] = SIMD_ARG_LANE_INDEX; + else if (d->qualifiers[qualifiers_k] & qualifier_immediate) args[k] = SIMD_ARG_CONSTANT; else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate) { diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 62b7f33..10bf67e 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -47,7 +47,8 @@ VAR1 (UNOP, addp, 0, di) BUILTIN_VDQ_BHSI (UNOP, clz, 2) - BUILTIN_VALL (GETLANE, be_checked_get_lane, 0) + /* be_checked_get_lane does its own lane swapping, so not a lane index. */ + BUILTIN_VALL (GETREG, be_checked_get_lane, 0) /* Implemented by aarch64_qshl. */ BUILTIN_VSDQ_I (BINOP, sqshl, 0) @@ -64,17 +65,17 @@ BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0) /* Implemented by aarch64_get_dreg. */ - BUILTIN_VDC (GETLANE, get_dregoi, 0) - BUILTIN_VDC (GETLANE, get_dregci, 0) - BUILTIN_VDC (GETLANE, get_dregxi, 0) + BUILTIN_VDC (GETREG, get_dregoi, 0) + BUILTIN_VDC (GETREG, get_dregci, 0) + BUILTIN_VDC (GETREG, get_dregxi, 0) /* Implemented by aarch64_get_qreg. */ - BUILTIN_VQ (GETLANE, get_qregoi, 0) - BUILTIN_VQ (GETLANE, get_qregci, 0) - BUILTIN_VQ (GETLANE, get_qregxi, 0) + BUILTIN_VQ (GETREG, get_qregoi, 0) + BUILTIN_VQ (GETREG, get_qregci, 0) + BUILTIN_VQ (GETREG, get_qregxi, 0) /* Implemented by aarch64_set_qreg. */ - BUILTIN_VQ (SETLANE, set_qregoi, 0) - BUILTIN_VQ (SETLANE, set_qregci, 0) - BUILTIN_VQ (SETLANE, set_qregxi, 0) + BUILTIN_VQ (SETREG, set_qregoi, 0) + BUILTIN_VQ (SETREG, set_qregci, 0) + BUILTIN_VQ (SETREG, set_qregxi, 0) /* Implemented by aarch64_ld. */ BUILTIN_VDC (LOADSTRUCT, ld2, 0) BUILTIN_VDC (LOADSTRUCT, ld3, 0) @@ -142,43 +143,44 @@ BUILTIN_VSDQ_I (UNOP, sqabs, 0) BUILTIN_VSDQ_I (UNOP, sqneg, 0) - BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_lane, 0) - BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_lane, 0) - BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_laneq, 0) - BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_laneq, 0) - BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0) - BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0) - BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_lane, 0) - BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_lane, 0) - BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_laneq, 0) - BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_laneq, 0) - BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0) - BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0) /* Implemented by aarch64_sqdmll. */ BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0) BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0) + /* Implemented by aarch64_sqdmll_lane. */ + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0) + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0) + /* Implemented by aarch64_sqdmll_laneq. */ + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0) + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0) /* Implemented by aarch64_sqdmll_n. */ BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0) BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0) + BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0) + BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0) + BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0) + BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0) + BUILTIN_VSD_HSI (BINOP, sqdmull, 0) - BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0) - BUILTIN_VSD_HSI (TERNOP, sqdmull_laneq, 0) + BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0) + BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0) BUILTIN_VD_HSI (BINOP, sqdmull_n, 0) BUILTIN_VQ_HSI (BINOP, sqdmull2, 0) - BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0) - BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0) + BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0) + BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0) BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0) /* Implemented by aarch64_sqdmulh. */ BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0) BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0) /* Implemented by aarch64_sqdmulh_lane. */ - BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0) - BUILTIN_VSDQ_HSI (TERNOP, sqdmulh_laneq, 0) - BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0) - BUILTIN_VSDQ_HSI (TERNOP, sqrdmulh_laneq, 0) - BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0) - BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0) BUILTIN_VSDQ_I_DI (BINOP, ashl, 3) /* Implemented by aarch64_shl. */ diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f7012ec..1a9e0de 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2771,41 +2771,7 @@ ;; sqdmulh_lane -(define_expand "aarch64_sqdmulh_lane" - [(match_operand:VDQHS 0 "register_operand" "") - (match_operand:VDQHS 1 "register_operand" "") - (match_operand: 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_SIMD" - { - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); - operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); - emit_insn (gen_aarch64_sqdmulh_lane_internal (operands[0], - operands[1], - operands[2], - operands[3])); - DONE; - } -) - -(define_expand "aarch64_sqrdmulh_lane" - [(match_operand:VDQHS 0 "register_operand" "") - (match_operand:VDQHS 1 "register_operand" "") - (match_operand: 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_SIMD" - { - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); - operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); - emit_insn (gen_aarch64_sqrdmulh_lane_internal (operands[0], - operands[1], - operands[2], - operands[3])); - DONE; - } -) - -(define_insn "aarch64_sqdmulh_lane_internal" +(define_insn "aarch64_sqdmulh_lane" [(set (match_operand:VDQHS 0 "register_operand" "=w") (unspec:VDQHS [(match_operand:VDQHS 1 "register_operand" "w") @@ -2815,47 +2781,12 @@ VQDMULH))] "TARGET_SIMD" "* - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); return \"sqdmulh\\t%0., %1., %2.[%3]\";" [(set_attr "type" "neon_sat_mul__scalar")] ) -(define_expand "aarch64_sqdmulh_laneq" - [(match_operand:VSDQ_HSI 0 "register_operand" "") - (match_operand:VSDQ_HSI 1 "register_operand" "") - (match_operand: 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_SIMD" - { - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); - operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); - emit_insn (gen_aarch64_sqdmulh_laneq_internal (operands[0], - operands[1], - operands[2], - operands[3])); - DONE; - } -) - -(define_expand "aarch64_sqrdmulh_laneq" - [(match_operand:VSDQ_HSI 0 "register_operand" "") - (match_operand:VSDQ_HSI 1 "register_operand" "") - (match_operand: 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_SIMD" - { - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); - operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); - emit_insn (gen_aarch64_sqrdmulh_laneq_internal (operands[0], - operands[1], - operands[2], - operands[3])); - DONE; - } -) - -(define_insn "aarch64_sqdmulh_laneq_internal" +(define_insn "aarch64_sqdmulh_laneq" [(set (match_operand:VDQHS 0 "register_operand" "=w") (unspec:VDQHS [(match_operand:VDQHS 1 "register_operand" "w") @@ -2870,41 +2801,7 @@ [(set_attr "type" "neon_sat_mul__scalar")] ) -(define_expand "aarch64_sqdmulh_lane" - [(match_operand:SD_HSI 0 "register_operand" "") - (match_operand:SD_HSI 1 "register_operand" "") - (match_operand: 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_SIMD" - { - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); - operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); - emit_insn (gen_aarch64_sqdmulh_lane_internal (operands[0], - operands[1], - operands[2], - operands[3])); - DONE; - } -) - -(define_expand "aarch64_sqrdmulh_lane" - [(match_operand:SD_HSI 0 "register_operand" "") - (match_operand:SD_HSI 1 "register_operand" "") - (match_operand: 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" "")] - "TARGET_SIMD" - { - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); - operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); - emit_insn (gen_aarch64_sqrdmulh_lane_internal (operands[0], - operands[1], - operands[2], - operands[3])); - DONE; - } -) - -(define_insn "aarch64_sqdmulh_lane_internal" +(define_insn "aarch64_sqdmulh_lane" [(set (match_operand:SD_HSI 0 "register_operand" "=w") (unspec:SD_HSI [(match_operand:SD_HSI 1 "register_operand" "w") @@ -2919,7 +2816,7 @@ [(set_attr "type" "neon_sat_mul__scalar")] ) -(define_insn "aarch64_sqdmulh_laneq_internal" +(define_insn "aarch64_sqdmulh_laneq" [(set (match_operand:SD_HSI 0 "register_operand" "=w") (unspec:SD_HSI [(match_operand:SD_HSI 1 "register_operand" "w") @@ -2954,7 +2851,7 @@ ;; vqdml[sa]l_lane -(define_insn "aarch64_sqdmll_lane_internal" +(define_insn "aarch64_sqdmll_lane" [(set (match_operand: 0 "register_operand" "=w") (SBINQOPS: (match_operand: 1 "register_operand" "0") @@ -2978,7 +2875,7 @@ [(set_attr "type" "neon_sat_mla__scalar_long")] ) -(define_insn "aarch64_sqdmll_laneq_internal" +(define_insn "aarch64_sqdmll_laneq" [(set (match_operand: 0 "register_operand" "=w") (SBINQOPS: (match_operand: 1 "register_operand" "0") @@ -3002,7 +2899,7 @@ [(set_attr "type" "neon_sat_mla__scalar_long")] ) -(define_insn "aarch64_sqdmll_lane_internal" +(define_insn "aarch64_sqdmll_lane" [(set (match_operand: 0 "register_operand" "=w") (SBINQOPS: (match_operand: 1 "register_operand" "0") @@ -3025,7 +2922,7 @@ [(set_attr "type" "neon_sat_mla__scalar_long")] ) -(define_insn "aarch64_sqdmll_laneq_internal" +(define_insn "aarch64_sqdmll_laneq" [(set (match_operand: 0 "register_operand" "=w") (SBINQOPS: (match_operand: 1 "register_operand" "0") @@ -3048,70 +2945,6 @@ [(set_attr "type" "neon_sat_mla__scalar_long")] ) -(define_expand "aarch64_sqdmlal_lane" - [(match_operand: 0 "register_operand" "=w") - (match_operand: 1 "register_operand" "0") - (match_operand:VSD_HSI 2 "register_operand" "w") - (match_operand: 3 "register_operand" "") - (match_operand:SI 4 "immediate_operand" "i")] - "TARGET_SIMD" -{ - aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); - operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); - emit_insn (gen_aarch64_sqdmlal_lane_internal (operands[0], operands[1], - operands[2], operands[3], - operands[4])); - DONE; -}) - -(define_expand "aarch64_sqdmlal_laneq" - [(match_operand: 0 "register_operand" "=w") - (match_operand: 1 "register_operand" "0") - (match_operand:VSD_HSI 2 "register_operand" "w") - (match_operand: 3 "register_operand" "") - (match_operand:SI 4 "immediate_operand" "i")] - "TARGET_SIMD" -{ - aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); - operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); - emit_insn (gen_aarch64_sqdmlal_laneq_internal (operands[0], operands[1], - operands[2], operands[3], - operands[4])); - DONE; -}) - -(define_expand "aarch64_sqdmlsl_lane" - [(match_operand: 0 "register_operand" "=w") - (match_operand: 1 "register_operand" "0") - (match_operand:VSD_HSI 2 "register_operand" "w") - (match_operand: 3 "register_operand" "") - (match_operand:SI 4 "immediate_operand" "i")] - "TARGET_SIMD" -{ - aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); - operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); - emit_insn (gen_aarch64_sqdmlsl_lane_internal (operands[0], operands[1], - operands[2], operands[3], - operands[4])); - DONE; -}) - -(define_expand "aarch64_sqdmlsl_laneq" - [(match_operand: 0 "register_operand" "=w") - (match_operand: 1 "register_operand" "0") - (match_operand:VSD_HSI 2 "register_operand" "w") - (match_operand: 3 "register_operand" "") - (match_operand:SI 4 "immediate_operand" "i")] - "TARGET_SIMD" -{ - aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); - operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); - emit_insn (gen_aarch64_sqdmlsl_laneq_internal (operands[0], operands[1], - operands[2], operands[3], - operands[4])); - DONE; -}) - ;; vqdml[sa]l_n (define_insn "aarch64_sqdmll_n" @@ -3242,8 +3075,6 @@ "TARGET_SIMD" { rtx p = aarch64_simd_vect_par_cnst_half (mode, true); - aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); - operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); emit_insn (gen_aarch64_sqdmlal2_lane_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3259,8 +3090,6 @@ "TARGET_SIMD" { rtx p = aarch64_simd_vect_par_cnst_half (mode, true); - aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); - operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); emit_insn (gen_aarch64_sqdmlal2_laneq_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3276,8 +3105,6 @@ "TARGET_SIMD" { rtx p = aarch64_simd_vect_par_cnst_half (mode, true); - aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); - operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); emit_insn (gen_aarch64_sqdmlsl2_lane_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3293,8 +3120,6 @@ "TARGET_SIMD" { rtx p = aarch64_simd_vect_par_cnst_half (mode, true); - aarch64_simd_lane_bounds (operands[4], 0, GET_MODE_NUNITS (mode)); - operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); emit_insn (gen_aarch64_sqdmlsl2_laneq_internal (operands[0], operands[1], operands[2], operands[3], operands[4], p)); @@ -3366,7 +3191,7 @@ ;; vqdmull_lane -(define_insn "aarch64_sqdmull_lane_internal" +(define_insn "aarch64_sqdmull_lane" [(set (match_operand: 0 "register_operand" "=w") (ss_ashift: (mult: @@ -3387,7 +3212,7 @@ [(set_attr "type" "neon_sat_mul__scalar_long")] ) -(define_insn "aarch64_sqdmull_laneq_internal" +(define_insn "aarch64_sqdmull_laneq" [(set (match_operand: 0 "register_operand" "=w") (ss_ashift: (mult: @@ -3408,7 +3233,7 @@ [(set_attr "type" "neon_sat_mul__scalar_long")] ) -(define_insn "aarch64_sqdmull_lane_internal" +(define_insn "aarch64_sqdmull_lane" [(set (match_operand: 0 "register_operand" "=w") (ss_ashift: (mult: @@ -3428,7 +3253,7 @@ [(set_attr "type" "neon_sat_mul__scalar_long")] ) -(define_insn "aarch64_sqdmull_laneq_internal" +(define_insn "aarch64_sqdmull_laneq" [(set (match_operand: 0 "register_operand" "=w") (ss_ashift: (mult: @@ -3448,34 +3273,6 @@ [(set_attr "type" "neon_sat_mul__scalar_long")] ) -(define_expand "aarch64_sqdmull_lane" - [(match_operand: 0 "register_operand" "=w") - (match_operand:VSD_HSI 1 "register_operand" "w") - (match_operand: 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" "i")] - "TARGET_SIMD" -{ - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); - operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); - emit_insn (gen_aarch64_sqdmull_lane_internal (operands[0], operands[1], - operands[2], operands[3])); - DONE; -}) - -(define_expand "aarch64_sqdmull_laneq" - [(match_operand: 0 "register_operand" "=w") - (match_operand:VSD_HSI 1 "register_operand" "w") - (match_operand: 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" "i")] - "TARGET_SIMD" -{ - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); - operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); - emit_insn (gen_aarch64_sqdmull_laneq_internal - (operands[0], operands[1], operands[2], operands[3])); - DONE; -}) - ;; vqdmull_n (define_insn "aarch64_sqdmull_n" @@ -3585,8 +3382,6 @@ "TARGET_SIMD" { rtx p = aarch64_simd_vect_par_cnst_half (mode, true); - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); - operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); emit_insn (gen_aarch64_sqdmull2_lane_internal (operands[0], operands[1], operands[2], operands[3], p)); @@ -3601,8 +3396,6 @@ "TARGET_SIMD" { rtx p = aarch64_simd_vect_par_cnst_half (mode, true); - aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); - operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); emit_insn (gen_aarch64_sqdmull2_laneq_internal (operands[0], operands[1], operands[2], operands[3], p)); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d4a8a2f..07f75e1 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -8163,7 +8163,7 @@ aarch64_simd_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) lane = INTVAL (operand); if (lane < low || lane >= high) - error ("lane out of range"); + error ("lane %ld out of range %ld - %ld", lane, low, high - 1); } /* Emit code to place a AdvSIMD pair result in memory locations (with equal diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7b570dc..5478e50 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,56 @@ +2014-11-12 Alan Lawrence + + * gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c: New test. + * gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c: Likewise. + * gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c: Likewise. + 2014-11-12 Uros Bizjak * gcc.target/i386/387-1.c (dg-skip-if): Use *-*-* target selector. diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c new file mode 100644 index 0000000..dd52b3e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s16_indices_1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c); + int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlal_high_lane_s16 (int32x4_a, int16x8_b, int16x4_c, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlal_high_lane_s16 (int32x4_a, int16x8_b, int16x4_c, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c new file mode 100644 index 0000000..279e592 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_lane_s32_indices_1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c); + int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b); + int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlal_high_lane_s32 (int64x2_a, int32x4_b, int32x2_c, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlal_high_lane_s32 (int64x2_a, int32x4_b, int32x2_c, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c new file mode 100644 index 0000000..6a6e877 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s16_indices_1.c @@ -0,0 +1,22 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_c = vcombine_u64 (base_c, base_a); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b); + int16x8_t int16x8_c = vreinterpretq_s16_u64 (baseq_c); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmlal_high_laneq_s16 (int32x4_a, int16x8_b, int16x8_c, -1); + /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmlal_high_laneq_s16 (int32x4_a, int16x8_b, int16x8_c, 8); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c new file mode 100644 index 0000000..e3353a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_high_laneq_s32_indices_1.c @@ -0,0 +1,22 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_c = vcombine_u64 (base_c, base_a); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b); + int32x4_t int32x4_c = vreinterpretq_s32_u64 (baseq_c); + int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlal_high_laneq_s32 (int64x2_a, int32x4_b, int32x4_c, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlal_high_laneq_s32 (int64x2_a, int32x4_b, int32x4_c, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c new file mode 100644 index 0000000..69bd5f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s16_indices_1.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlal_lane_s16 (int32x4_a, int16x4_b, int16x4_c, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlal_lane_s16 (int32x4_a, int16x4_b, int16x4_c, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c new file mode 100644 index 0000000..e8886c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_lane_s32_indices_1.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c); + int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlal_lane_s32 (int64x2_a, int32x2_b, int32x2_c, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlal_lane_s32 (int64x2_a, int32x2_b, int32x2_c, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c new file mode 100644 index 0000000..f800d36 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s16_indices_1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_c = vcombine_u64 (base_c, base_a); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + int16x8_t int16x8_c = vreinterpretq_s16_u64 (baseq_c); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmlal_laneq_s16 (int32x4_a, int16x4_b, int16x8_c, -1); + /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmlal_laneq_s16 (int32x4_a, int16x4_b, int16x8_c, 8); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c new file mode 100644 index 0000000..f72f92a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlal_laneq_s32_indices_1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_c = vcombine_u64 (base_c, base_a); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + int32x4_t int32x4_c = vreinterpretq_s32_u64 (baseq_c); + int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlal_laneq_s32 (int64x2_a, int32x2_b, int32x4_c, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlal_laneq_s32 (int64x2_a, int32x2_b, int32x4_c, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c new file mode 100644 index 0000000..34b01f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlalh_lane_s16_indices_1.c @@ -0,0 +1,17 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + int16_t int16_b = 0x5678; + int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c); + int32_t int32_a = 0xdeadbeef; + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlalh_lane_s16 (int32_a, int16_b, int16x4_c, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlalh_lane_s16 (int32_a, int16_b, int16x4_c, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c new file mode 100644 index 0000000..43e656a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32_indices_1.c @@ -0,0 +1,17 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + int64_t int64_a = 0x1111222233334444LL; + int32_t int32_b = 0xcafebabe; + int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlals_lane_s32 (int64_a, int32_b, int32x2_c, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlals_lane_s32 (int64_a, int32_b, int32x2_c, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c new file mode 100644 index 0000000..c4c009f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s16_indices_1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c); + int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlsl_high_lane_s16 (int32x4_a, int16x8_b, int16x4_c, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlsl_high_lane_s16 (int32x4_a, int16x8_b, int16x4_c, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c new file mode 100644 index 0000000..1d9d242 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_lane_s32_indices_1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c); + int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b); + int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlsl_high_lane_s32 (int64x2_a, int32x4_b, int32x2_c, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlsl_high_lane_s32 (int64x2_a, int32x4_b, int32x2_c, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c new file mode 100644 index 0000000..d0675f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16_indices_1.c @@ -0,0 +1,22 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_c = vcombine_u64 (base_c, base_a); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b); + int16x8_t int16x8_c = vreinterpretq_s16_u64 (baseq_c); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmlsl_high_laneq_s16 (int32x4_a, int16x8_b, int16x8_c, -1); + /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmlsl_high_laneq_s16 (int32x4_a, int16x8_b, int16x8_c, 8); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c new file mode 100644 index 0000000..56383ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32_indices_1.c @@ -0,0 +1,22 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_c = vcombine_u64 (base_c, base_a); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b); + int32x4_t int32x4_c = vreinterpretq_s32_u64 (baseq_c); + int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlsl_high_laneq_s32 (int64x2_a, int32x4_b, int32x4_c, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlsl_high_laneq_s32 (int64x2_a, int32x4_b, int32x4_c, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c new file mode 100644 index 0000000..9999680 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s16_indices_1.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlsl_lane_s16 (int32x4_a, int16x4_b, int16x4_c, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlsl_lane_s16 (int32x4_a, int16x4_b, int16x4_c, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c new file mode 100644 index 0000000..a4f35ca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_lane_s32_indices_1.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c); + int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlsl_lane_s32 (int64x2_a, int32x2_b, int32x2_c, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlsl_lane_s32 (int64x2_a, int32x2_b, int32x2_c, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c new file mode 100644 index 0000000..65e9c00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s16_indices_1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_c = vcombine_u64 (base_c, base_a); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + int16x8_t int16x8_c = vreinterpretq_s16_u64 (baseq_c); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmlsl_laneq_s16 (int32x4_a, int16x4_b, int16x8_c, -1); + /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmlsl_laneq_s16 (int32x4_a, int16x4_b, int16x8_c, 8); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c new file mode 100644 index 0000000..4dc3360 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsl_laneq_s32_indices_1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_c = vcombine_u64 (base_c, base_a); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + int32x4_t int32x4_c = vreinterpretq_s32_u64 (baseq_c); + int64x2_t int64x2_a = vreinterpretq_s64_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlsl_laneq_s32 (int64x2_a, int32x2_b, int32x4_c, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlsl_laneq_s32 (int64x2_a, int32x2_b, int32x4_c, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c new file mode 100644 index 0000000..f46e5bb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlslh_lane_s16_indices_1.c @@ -0,0 +1,17 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + int16_t int16_b = 0x5678; + int16x4_t int16x4_c = vreinterpret_s16_u64 (base_c); + int32_t int32_a = 0xdeadbeef; + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlslh_lane_s16 (int32_a, int16_b, int16x4_c, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmlslh_lane_s16 (int32_a, int16_b, int16x4_c, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c new file mode 100644 index 0000000..c8271f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32_indices_1.c @@ -0,0 +1,18 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + int64_t int64_a = 0x1111222233334444LL; + int32_t int32_b = 0xcafebabe; + int32x2_t int32x2_c = vreinterpret_s32_u64 (base_c); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlsls_lane_s32 (int64_a, int32_b, int32x2_c, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmlsls_lane_s32 (int64_a, int32_b, int32x2_c, 2); +} + diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c new file mode 100644 index 0000000..9bde011 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s16_indices_1.c @@ -0,0 +1,17 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a); + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmulh_lane_s16 (int16x4_a, int16x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmulh_lane_s16 (int16x4_a, int16x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c new file mode 100644 index 0000000..bd93566 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_lane_s32_indices_1.c @@ -0,0 +1,17 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a); + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmulh_lane_s32 (int32x2_a, int32x2_b, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmulh_lane_s32 (int32x2_a, int32x2_b, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c new file mode 100644 index 0000000..ece91e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s16_indices_1.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a); + int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmulh_laneq_s16 (int16x4_a, int16x8_b, -1); + /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmulh_laneq_s16 (int16x4_a, int16x8_b, 8); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c new file mode 100644 index 0000000..dd5afb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulh_laneq_s32_indices_1.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a); + int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmulh_laneq_s32 (int32x2_a, int32x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmulh_laneq_s32 (int32x2_a, int32x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c new file mode 100644 index 0000000..8804e84 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhh_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int16_t int16_a = 0x1234; + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmulhh_lane_s16 (int16_a, int16x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmulhh_lane_s16 (int16_a, int16x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c new file mode 100644 index 0000000..0b19ea9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s16_indices_1.c @@ -0,0 +1,18 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmulhq_lane_s16 (int16x8_a, int16x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmulhq_lane_s16 (int16x8_a, int16x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c new file mode 100644 index 0000000..f2d3228 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_lane_s32_indices_1.c @@ -0,0 +1,18 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmulhq_lane_s32 (int32x4_a, int32x2_b, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmulhq_lane_s32 (int32x4_a, int32x2_b, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c new file mode 100644 index 0000000..20f5284 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s16_indices_1.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a); + int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmulhq_laneq_s16 (int16x8_a, int16x8_b, -1); + /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmulhq_laneq_s16 (int16x8_a, int16x8_b, 8); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c new file mode 100644 index 0000000..916efbb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhq_laneq_s32_indices_1.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmulhq_laneq_s32 (int32x4_a, int32x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmulhq_laneq_s32 (int32x4_a, int32x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c new file mode 100644 index 0000000..8bcfb33 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulhs_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int32_t int32_a = 0xdeadbeef; + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmulhs_lane_s32 (int32_a, int32x2_b, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmulhs_lane_s32 (int32_a, int32x2_b, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c new file mode 100644 index 0000000..e21ca9c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s16_indices_1.c @@ -0,0 +1,18 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmull_high_lane_s16 (int16x8_a, int16x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmull_high_lane_s16 (int16x8_a, int16x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c new file mode 100644 index 0000000..1df33b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_lane_s32_indices_1.c @@ -0,0 +1,18 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmull_high_lane_s32 (int32x4_a, int32x2_b, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmull_high_lane_s32 (int32x4_a, int32x2_b, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c new file mode 100644 index 0000000..df81cb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s16_indices_1.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a); + int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmull_high_laneq_s16 (int16x8_a, int16x8_b, -1); + /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmull_high_laneq_s16 (int16x8_a, int16x8_b, 8); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c new file mode 100644 index 0000000..a67da62 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_high_laneq_s32_indices_1.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmull_high_laneq_s32 (int32x4_a, int32x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmull_high_laneq_s32 (int32x4_a, int32x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c new file mode 100644 index 0000000..938279c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s16_indices_1.c @@ -0,0 +1,17 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a); + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmull_lane_s16 (int16x4_a, int16x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmull_lane_s16 (int16x4_a, int16x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c new file mode 100644 index 0000000..b922c65 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_lane_s32_indices_1.c @@ -0,0 +1,17 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a); + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmull_lane_s32 (int32x2_a, int32x2_b, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmull_lane_s32 (int32x2_a, int32x2_b, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c new file mode 100644 index 0000000..e38cbc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s16_indices_1.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a); + int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmull_laneq_s16 (int16x4_a, int16x8_b, -1); + /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqdmull_laneq_s16 (int16x4_a, int16x8_b, 8); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c new file mode 100644 index 0000000..f90fbe6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmull_laneq_s32_indices_1.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a); + int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmull_laneq_s32 (int32x2_a, int32x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmull_laneq_s32 (int32x2_a, int32x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c new file mode 100644 index 0000000..fc53284 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmullh_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int16_t int16_a = 0x1234; + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmullh_lane_s16 (int16_a, int16x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqdmullh_lane_s16 (int16_a, int16x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c new file mode 100644 index 0000000..edc66b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmulls_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int32_t int32_a = 0xdeadbeef; + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmulls_lane_s32 (int32_a, int32x2_b, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqdmulls_lane_s32 (int32_a, int32x2_b, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c new file mode 100644 index 0000000..1ce5c4b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s16_indices_1.c @@ -0,0 +1,17 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a); + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqrdmulh_lane_s16 (int16x4_a, int16x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqrdmulh_lane_s16 (int16x4_a, int16x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c new file mode 100644 index 0000000..b16f1b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_lane_s32_indices_1.c @@ -0,0 +1,17 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a); + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqrdmulh_lane_s32 (int32x2_a, int32x2_b, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqrdmulh_lane_s32 (int32x2_a, int32x2_b, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c new file mode 100644 index 0000000..19cad84 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s16_indices_1.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int16x4_t int16x4_a = vreinterpret_s16_u64 (base_a); + int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqrdmulh_laneq_s16 (int16x4_a, int16x8_b, -1); + /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqrdmulh_laneq_s16 (int16x4_a, int16x8_b, 8); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c new file mode 100644 index 0000000..af20661 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulh_laneq_s32_indices_1.c @@ -0,0 +1,19 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int32x2_t int32x2_a = vreinterpret_s32_u64 (base_a); + int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqrdmulh_laneq_s32 (int32x2_a, int32x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqrdmulh_laneq_s32 (int32x2_a, int32x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c new file mode 100644 index 0000000..a15d39e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhh_lane_s16_indices_1.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int16_t int16_a = 0x1234; + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqrdmulhh_lane_s16 (int16_a, int16x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqrdmulhh_lane_s16 (int16_a, int16x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c new file mode 100644 index 0000000..3b0c41e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s16_indices_1.c @@ -0,0 +1,18 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int16x4_t int16x4_b = vreinterpret_s16_u64 (base_b); + int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqrdmulhq_lane_s16 (int16x8_a, int16x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqrdmulhq_lane_s16 (int16x8_a, int16x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c new file mode 100644 index 0000000..9a91c37 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_lane_s32_indices_1.c @@ -0,0 +1,18 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqrdmulhq_lane_s32 (int32x4_a, int32x2_b, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqrdmulhq_lane_s32 (int32x4_a, int32x2_b, 2); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c new file mode 100644 index 0000000..038d796 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s16_indices_1.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int16x8_t int16x8_a = vreinterpretq_s16_u64 (baseq_a); + int16x8_t int16x8_b = vreinterpretq_s16_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqrdmulhq_laneq_s16 (int16x8_a, int16x8_b, -1); + /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */ + vqrdmulhq_laneq_s16 (int16x8_a, int16x8_b, 8); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c new file mode 100644 index 0000000..b46b92a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhq_laneq_s32_indices_1.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_a = vcreate_u64 (0x1111222233334444ULL); + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + uint64x2_t baseq_a = vcombine_u64 (base_a, base_b); + uint64x1_t base_c = vcreate_u64 (0x9999aaaabbbbccccULL); + uint64x2_t baseq_b = vcombine_u64 (base_b, base_c); + int32x4_t int32x4_a = vreinterpretq_s32_u64 (baseq_a); + int32x4_t int32x4_b = vreinterpretq_s32_u64 (baseq_b); + + /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqrdmulhq_laneq_s32 (int32x4_a, int32x4_b, -1); + /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */ + vqrdmulhq_laneq_s32 (int32x4_a, int32x4_b, 4); +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c new file mode 100644 index 0000000..48223cb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqrdmulhs_lane_s32_indices_1.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-std=c99" } */ +#include + +int +main (int argc, char **argv) +{ + uint64x1_t base_b = vcreate_u64 (0x5555666677778888ULL); + int32_t int32_a = 0xdeadbeef; + int32x2_t int32x2_b = vreinterpret_s32_u64 (base_b); + + /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqrdmulhs_lane_s32 (int32_a, int32x2_b, -1); + /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */ + vqrdmulhs_lane_s32 (int32_a, int32x2_b, 2); +} -- 2.7.4