From 490d1b4a834897e927d58d1a8fba93c2a33172df Mon Sep 17 00:00:00 2001
From: Kugan Vivekanandarajah <kuganv@linaro.org>
Date: Mon, 14 Oct 2019 23:33:17 +0000
Subject: [PATCH] vfp.md (fma<SDF:mode>4): Enable DF only when
 TARGET_VFP_DOUBLE.

gcc/ChangeLog:

2019-10-15  Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

	* config/arm/vfp.md (fma<SDF:mode>4): Enable DF only when
	TARGET_VFP_DOUBLE.
	(*fmsub<SDF:mode>4): Likewise.
	*fnmsub<SDF:mode>4): Likewise.
	(*fnmadd<SDF:mode>4): Likewise.

From-SVN: r276977
---
 gcc/ChangeLog         | 8 ++++++++
 gcc/config/arm/vfp.md | 8 ++++----
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b58f60c..9957d2c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-10-15  Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>
+
+	* config/arm/vfp.md (fma<SDF:mode>4): Enable DF only when
+	TARGET_VFP_DOUBLE.
+	(*fmsub<SDF:mode>4): Likewise.
+	*fnmsub<SDF:mode>4): Likewise.
+	(*fnmadd<SDF:mode>4): Likewise.
+
 2019-10-14 Joel Hutton  <Joel.Hutton@arm.com>
 
 	* doc/tree-ssa.texi: Update renamed macro name.
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 661919e..1979aa6 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1321,7 +1321,7 @@
         (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
 		 (match_operand:SDF 2 "register_operand" "<F_constraint>")
 		 (match_operand:SDF 3 "register_operand" "0")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
   "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "predicable" "yes")
    (set_attr "type" "ffma<vfp_type>")]
@@ -1357,7 +1357,7 @@
 					     "<F_constraint>"))
 		 (match_operand:SDF 2 "register_operand" "<F_constraint>")
 		 (match_operand:SDF 3 "register_operand" "0")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
   "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "predicable" "yes")
    (set_attr "type" "ffma<vfp_type>")]
@@ -1379,7 +1379,7 @@
 	(fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
 		 (match_operand:SDF 2 "register_operand" "<F_constraint>")
 		 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
   "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "predicable" "yes")
    (set_attr "type" "ffma<vfp_type>")]
@@ -1402,7 +1402,7 @@
 					       "<F_constraint>"))
 		 (match_operand:SDF 2 "register_operand" "<F_constraint>")
 		 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
   "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "predicable" "yes")
    (set_attr "type" "ffma<vfp_type>")]
-- 
2.7.4