From 48f5d77eeed4d7453d199c4b4ac16c1bbfbdbddf Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Wed, 11 Jan 2023 16:34:43 +0000 Subject: [PATCH] [NFC] Use TypeSize::getKnownMinValue() instead of TypeSize::getKnownMinSize() This change is one of a series to implement the discussion from https://reviews.llvm.org/D141134. --- llvm/include/llvm/CodeGen/ValueTypes.h | 2 +- llvm/include/llvm/IR/DataLayout.h | 2 +- llvm/include/llvm/IR/PatternMatch.h | 2 +- llvm/include/llvm/Support/LowLevelTypeImpl.h | 2 +- llvm/include/llvm/Support/MachineValueType.h | 2 +- llvm/lib/Analysis/InlineCost.cpp | 6 ++-- llvm/lib/Analysis/MemoryBuiltins.cpp | 2 +- llvm/lib/Analysis/ValueTracking.cpp | 2 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 +-- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 2 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 30 +++++++++---------- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 11 +++---- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 11 +++---- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 11 +++---- llvm/lib/CodeGen/TargetLoweringBase.cpp | 2 +- llvm/lib/IR/DataLayout.cpp | 4 +-- llvm/lib/IR/Instructions.cpp | 2 +- llvm/lib/IR/Value.cpp | 4 +-- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 6 ++-- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 20 ++++++------- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 8 ++--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 ++--- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 2 +- llvm/lib/Transforms/IPO/Attributor.cpp | 5 ++-- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 2 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 9 +++--- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 4 +-- .../InstCombine/InstructionCombining.cpp | 2 +- llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp | 2 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 4 +-- llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp | 24 +++++++-------- llvm/unittests/IR/VectorTypesTest.cpp | 34 +++++++++++----------- llvm/unittests/Support/TypeSizeTest.cpp | 4 +-- 35 files changed, 122 insertions(+), 117 deletions(-) diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h index 48d2654..6917fa9 100644 --- a/llvm/include/llvm/CodeGen/ValueTypes.h +++ b/llvm/include/llvm/CodeGen/ValueTypes.h @@ -361,7 +361,7 @@ namespace llvm { /// base size. TypeSize getStoreSize() const { TypeSize BaseSize = getSizeInBits(); - return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()}; + return {(BaseSize.getKnownMinValue() + 7) / 8, BaseSize.isScalable()}; } // Return the number of bytes overwritten by a store of this value type or diff --git a/llvm/include/llvm/IR/DataLayout.h b/llvm/include/llvm/IR/DataLayout.h index e63a305..3ac9c74 100644 --- a/llvm/include/llvm/IR/DataLayout.h +++ b/llvm/include/llvm/IR/DataLayout.h @@ -473,7 +473,7 @@ public: /// For example, returns 5 for i36 and 10 for x86_fp80. TypeSize getTypeStoreSize(Type *Ty) const { TypeSize BaseSize = getTypeSizeInBits(Ty); - return {divideCeil(BaseSize.getKnownMinSize(), 8), BaseSize.isScalable()}; + return {divideCeil(BaseSize.getKnownMinValue(), 8), BaseSize.isScalable()}; } /// Returns the maximum number of bits that may be overwritten by diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h index 1027160..38a916c 100644 --- a/llvm/include/llvm/IR/PatternMatch.h +++ b/llvm/include/llvm/IR/PatternMatch.h @@ -2490,7 +2490,7 @@ struct VScaleVal_match { if (GEP->getNumIndices() == 1 && isa(DerefTy) && m_Zero().match(GEP->getPointerOperand()) && m_SpecificInt(1).match(GEP->idx_begin()->get()) && - DL.getTypeAllocSizeInBits(DerefTy).getKnownMinSize() == 8) + DL.getTypeAllocSizeInBits(DerefTy).getKnownMinValue() == 8) return true; } } diff --git a/llvm/include/llvm/Support/LowLevelTypeImpl.h b/llvm/include/llvm/Support/LowLevelTypeImpl.h index f283bb6..aeedec0 100644 --- a/llvm/include/llvm/Support/LowLevelTypeImpl.h +++ b/llvm/include/llvm/Support/LowLevelTypeImpl.h @@ -166,7 +166,7 @@ public: /// needed to represent the size in bits. Must only be called on sized types. constexpr TypeSize getSizeInBytes() const { TypeSize BaseSize = getSizeInBits(); - return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()}; + return {(BaseSize.getKnownMinValue() + 7) / 8, BaseSize.isScalable()}; } constexpr LLT getScalarType() const { diff --git a/llvm/include/llvm/Support/MachineValueType.h b/llvm/include/llvm/Support/MachineValueType.h index c506f6d..aa4a9a3 100644 --- a/llvm/include/llvm/Support/MachineValueType.h +++ b/llvm/include/llvm/Support/MachineValueType.h @@ -1147,7 +1147,7 @@ namespace llvm { /// base size. TypeSize getStoreSize() const { TypeSize BaseSize = getSizeInBits(); - return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()}; + return {(BaseSize.getKnownMinValue() + 7) / 8, BaseSize.isScalable()}; } // Return the number of bytes overwritten by a store of this value type or diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp index 309da99..bce71b2 100644 --- a/llvm/lib/Analysis/InlineCost.cpp +++ b/llvm/lib/Analysis/InlineCost.cpp @@ -1394,7 +1394,7 @@ bool CallAnalyzer::visitAlloca(AllocaInst &I) { Type *Ty = I.getAllocatedType(); AllocatedSize = SaturatingMultiplyAdd( AllocSize->getLimitedValue(), - DL.getTypeAllocSize(Ty).getKnownMinSize(), AllocatedSize); + DL.getTypeAllocSize(Ty).getKnownMinValue(), AllocatedSize); if (AllocatedSize > InlineConstants::MaxSimplifiedDynamicAllocaToInline) HasDynamicAlloca = true; return false; @@ -1404,8 +1404,8 @@ bool CallAnalyzer::visitAlloca(AllocaInst &I) { // Accumulate the allocated size. if (I.isStaticAlloca()) { Type *Ty = I.getAllocatedType(); - AllocatedSize = - SaturatingAdd(DL.getTypeAllocSize(Ty).getKnownMinSize(), AllocatedSize); + AllocatedSize = SaturatingAdd(DL.getTypeAllocSize(Ty).getKnownMinValue(), + AllocatedSize); } // FIXME: This is overly conservative. Dynamic allocas are inefficient for diff --git a/llvm/lib/Analysis/MemoryBuiltins.cpp b/llvm/lib/Analysis/MemoryBuiltins.cpp index aa74867..0edad05 100644 --- a/llvm/lib/Analysis/MemoryBuiltins.cpp +++ b/llvm/lib/Analysis/MemoryBuiltins.cpp @@ -750,7 +750,7 @@ SizeOffsetType ObjectSizeOffsetVisitor::visitAllocaInst(AllocaInst &I) { TypeSize ElemSize = DL.getTypeAllocSize(I.getAllocatedType()); if (ElemSize.isScalable() && Options.EvalMode != ObjectSizeOpts::Mode::Min) return unknown(); - APInt Size(IntTyBits, ElemSize.getKnownMinSize()); + APInt Size(IntTyBits, ElemSize.getKnownMinValue()); if (!I.isArrayAllocation()) return std::make_pair(align(Size, I.getAlign()), Zero); diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index e49183d..ac8ec77 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -1375,7 +1375,7 @@ static void computeKnownBitsFromOperator(const Operator *I, KnownBits IndexBits(IndexBitWidth); computeKnownBits(Index, IndexBits, Depth + 1, Q); TypeSize IndexTypeSize = Q.DL.getTypeAllocSize(IndexedTy); - uint64_t TypeSizeInBytes = IndexTypeSize.getKnownMinSize(); + uint64_t TypeSizeInBytes = IndexTypeSize.getKnownMinValue(); KnownBits ScalingFactor(IndexBitWidth); // Multiply by current sizeof type. // &A[i] == A + i * sizeof(*A[i]). diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index cdfe98f..31caa65 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -2355,7 +2355,7 @@ bool CodeGenPrepare::optimizeCallInst(CallInst *CI, ModifyDT &ModifiedDT) { // to benefit from cheap constant propagation. Type *ScalableVectorTy = VectorType::get(Type::getInt8Ty(II->getContext()), 1, true); - if (DL->getTypeAllocSize(ScalableVectorTy).getKnownMinSize() == 8) { + if (DL->getTypeAllocSize(ScalableVectorTy).getKnownMinValue() == 8) { auto *Null = Constant::getNullValue(ScalableVectorTy->getPointerTo()); auto *One = ConstantInt::getSigned(II->getType(), 1); auto *CGep = diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 90f437e..ca3cd95 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -251,8 +251,8 @@ namespace { for (MVT VT : MVT::all_valuetypes()) if (EVT(VT).isSimple() && VT != MVT::Other && TLI.isTypeLegal(EVT(VT)) && - VT.getSizeInBits().getKnownMinSize() >= MaximumLegalStoreInBits) - MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinSize(); + VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits) + MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue(); } void ConsiderForPruning(SDNode *N) { diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index 3e59d0d..847a029 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -150,7 +150,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, (TFI->isStackRealignable() || (Alignment <= StackAlign))) { const ConstantInt *CUI = cast(AI->getArraySize()); uint64_t TySize = - MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinSize(); + MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinValue(); TySize *= CUI->getZExtValue(); // Get total allocated size. if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects. diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 534b3f5..edc6a43 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -769,7 +769,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) { Value = Result; Chain = Ch; - } else if (!isPowerOf2_64(SrcWidth.getKnownMinSize())) { + } else if (!isPowerOf2_64(SrcWidth.getKnownMinValue())) { // If not loading a power-of-2 number of bits, expand as two loads. assert(!SrcVT.isVector() && "Unsupported extload!"); unsigned SrcWidthBits = SrcWidth.getFixedSize(); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 34b0715..f76c14f1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1166,7 +1166,7 @@ void DAGTypeLegalizer::IncrementPointer(MemSDNode *N, EVT MemVT, MachinePointerInfo &MPI, SDValue &Ptr, uint64_t *ScaledOffset) { SDLoc DL(N); - unsigned IncrementSize = MemVT.getSizeInBits().getKnownMinSize() / 8; + unsigned IncrementSize = MemVT.getSizeInBits().getKnownMinValue() / 8; if (MemVT.isScalableVector()) { SDNodeFlags Flags; @@ -2006,7 +2006,7 @@ void DAGTypeLegalizer::SplitVecRes_VP_STRIDED_LOAD(VPStridedLoadSDNode *SLD, Align Alignment = SLD->getOriginalAlign(); if (LoMemVT.isScalableVector()) Alignment = commonAlignment( - Alignment, LoMemVT.getSizeInBits().getKnownMinSize() / 8); + Alignment, LoMemVT.getSizeInBits().getKnownMinValue() / 8); MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( MachinePointerInfo(SLD->getPointerInfo().getAddrSpace()), @@ -3310,7 +3310,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_VP_STORE(VPStoreSDNode *N, unsigned OpNo) { MachinePointerInfo MPI; if (LoMemVT.isScalableVector()) { Alignment = commonAlignment(Alignment, - LoMemVT.getSizeInBits().getKnownMinSize() / 8); + LoMemVT.getSizeInBits().getKnownMinValue() / 8); MPI = MachinePointerInfo(N->getPointerInfo().getAddrSpace()); } else MPI = N->getPointerInfo().getWithOffset( @@ -3386,7 +3386,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_VP_STRIDED_STORE(VPStridedStoreSDNode *N, Align Alignment = N->getOriginalAlign(); if (LoMemVT.isScalableVector()) Alignment = commonAlignment(Alignment, - LoMemVT.getSizeInBits().getKnownMinSize() / 8); + LoMemVT.getSizeInBits().getKnownMinValue() / 8); MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( MachinePointerInfo(N->getPointerInfo().getAddrSpace()), @@ -3460,7 +3460,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N, MachinePointerInfo MPI; if (LoMemVT.isScalableVector()) { Alignment = commonAlignment( - Alignment, LoMemVT.getSizeInBits().getKnownMinSize() / 8); + Alignment, LoMemVT.getSizeInBits().getKnownMinValue() / 8); MPI = MachinePointerInfo(N->getPointerInfo().getAddrSpace()); } else MPI = N->getPointerInfo().getWithOffset( @@ -6611,7 +6611,7 @@ static std::optional findMemType(SelectionDAG &DAG, unsigned WidenEx = 0) { EVT WidenEltVT = WidenVT.getVectorElementType(); const bool Scalable = WidenVT.isScalableVector(); - unsigned WidenWidth = WidenVT.getSizeInBits().getKnownMinSize(); + unsigned WidenWidth = WidenVT.getSizeInBits().getKnownMinValue(); unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); unsigned AlignInBits = Align*8; @@ -6649,7 +6649,7 @@ static std::optional findMemType(SelectionDAG &DAG, // Skip vector MVTs which don't match the scalable property of WidenVT. if (Scalable != MemVT.isScalableVector()) continue; - unsigned MemVTWidth = MemVT.getSizeInBits().getKnownMinSize(); + unsigned MemVTWidth = MemVT.getSizeInBits().getKnownMinValue(); auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT); if ((Action == TargetLowering::TypeLegal || Action == TargetLowering::TypePromoteInteger) && @@ -6732,8 +6732,8 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl &LdChain, // Find the vector type that can load from. std::optional FirstVT = - findMemType(DAG, TLI, LdWidth.getKnownMinSize(), WidenVT, LdAlign, - WidthDiff.getKnownMinSize()); + findMemType(DAG, TLI, LdWidth.getKnownMinValue(), WidenVT, LdAlign, + WidthDiff.getKnownMinValue()); if (!FirstVT) return SDValue(); @@ -6751,8 +6751,8 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl &LdChain, RemainingWidth -= NewVTWidth; if (TypeSize::isKnownLT(RemainingWidth, NewVTWidth)) { // The current type we are using is too large. Find a better size. - NewVT = findMemType(DAG, TLI, RemainingWidth.getKnownMinSize(), WidenVT, - LdAlign, WidthDiff.getKnownMinSize()); + NewVT = findMemType(DAG, TLI, RemainingWidth.getKnownMinValue(), + WidenVT, LdAlign, WidthDiff.getKnownMinValue()); if (!NewVT) return SDValue(); NewVTWidth = NewVT->getSizeInBits(); @@ -6844,9 +6844,9 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl &LdChain, TypeSize LdTySize = LdTy.getSizeInBits(); TypeSize NewLdTySize = NewLdTy.getSizeInBits(); assert(NewLdTySize.isScalable() == LdTySize.isScalable() && - NewLdTySize.isKnownMultipleOf(LdTySize.getKnownMinSize())); + NewLdTySize.isKnownMultipleOf(LdTySize.getKnownMinValue())); unsigned NumOps = - NewLdTySize.getKnownMinSize() / LdTySize.getKnownMinSize(); + NewLdTySize.getKnownMinValue() / LdTySize.getKnownMinValue(); SmallVector WidenOps(NumOps); unsigned j = 0; for (; j != End-Idx; ++j) @@ -6868,7 +6868,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl &LdChain, // We need to fill the rest with undefs to build the vector. unsigned NumOps = - WidenWidth.getKnownMinSize() / LdTy.getSizeInBits().getKnownMinSize(); + WidenWidth.getKnownMinValue() / LdTy.getSizeInBits().getKnownMinValue(); SmallVector WidenOps(NumOps); SDValue UndefVal = DAG.getUNDEF(LdTy); { @@ -6968,7 +6968,7 @@ bool DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl &StChain, while (StWidth.isNonZero()) { // Find the largest vector type we can store with. std::optional NewVT = - findMemType(DAG, TLI, StWidth.getKnownMinSize(), ValVT); + findMemType(DAG, TLI, StWidth.getKnownMinValue(), ValVT); if (!NewVT) return false; MemVTs.push_back({*NewVT, 0}); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 3805f70..12c76ba 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2348,7 +2348,7 @@ SDValue SelectionDAG::CreateStackTemporary(TypeSize Bytes, Align Alignment) { StackID = TFI->getStackIDForScalableVectors(); // The stack id gives an indication of whether the object is scalable or // not, so it's safe to pass in the minimum size here. - int FrameIdx = MFI.CreateStackObject(Bytes.getKnownMinSize(), Alignment, + int FrameIdx = MFI.CreateStackObject(Bytes.getKnownMinValue(), Alignment, false, nullptr, StackID); return getFrameIndex(FrameIdx, TLI->getFrameIndexTy(getDataLayout())); } @@ -2366,8 +2366,9 @@ SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) { assert(VT1Size.isScalable() == VT2Size.isScalable() && "Don't know how to choose the maximum size when creating a stack " "temporary"); - TypeSize Bytes = - VT1Size.getKnownMinSize() > VT2Size.getKnownMinSize() ? VT1Size : VT2Size; + TypeSize Bytes = VT1Size.getKnownMinValue() > VT2Size.getKnownMinValue() + ? VT1Size + : VT2Size; Type *Ty1 = VT1.getTypeForEVT(*getContext()); Type *Ty2 = VT2.getTypeForEVT(*getContext()); @@ -6894,7 +6895,7 @@ SDValue SelectionDAG::getMemBasePlusOffset(SDValue Base, TypeSize Offset, if (Offset.isScalable()) Index = getVScale(DL, Base.getValueType(), APInt(Base.getValueSizeInBits().getFixedSize(), - Offset.getKnownMinSize())); + Offset.getKnownMinValue())); else Index = getConstant(Offset.getFixedSize(), DL, VT); @@ -11099,7 +11100,7 @@ MemSDNode::MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, // the MMO. This is because the MMO might indicate only a possible address // range instead of specifying the affected memory addresses precisely. // TODO: Make MachineMemOperands aware of scalable vectors. - assert(memvt.getStoreSize().getKnownMinSize() <= MMO->getSize() && + assert(memvt.getStoreSize().getKnownMinValue() <= MMO->getSize() && "Size mismatch!"); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 1fb7ab1..e261b65 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -3948,7 +3948,7 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) { DAG.getDataLayout().getTypeAllocSize(GTI.getIndexedType()); // We intentionally mask away the high bits here; ElementSize may not // fit in IdxTy. - APInt ElementMul(IdxSize, ElementSize.getKnownMinSize()); + APInt ElementMul(IdxSize, ElementSize.getKnownMinValue()); bool ElementScalable = ElementSize.isScalable(); // If this is a scalar constant or a splat vector of constants, @@ -10145,7 +10145,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { ISD::OutputArg MyFlags( Flags, Parts[j].getValueType().getSimpleVT(), VT, i < CLI.NumFixedArgs, i, - j * Parts[j].getValueType().getStoreSize().getKnownMinSize()); + j * Parts[j].getValueType().getStoreSize().getKnownMinValue()); if (NumParts > 1 && j == 0) MyFlags.Flags.setSplit(); else if (j != 0) { @@ -10672,8 +10672,9 @@ void SelectionDAGISel::LowerArguments(const Function &F) { // For scalable vectors, use the minimum size; individual targets // are responsible for handling scalable vector arguments and // return values. - ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed, - ArgNo, PartBase+i*RegisterVT.getStoreSize().getKnownMinSize()); + ISD::InputArg MyFlags( + Flags, RegisterVT, VT, isArgValueUsed, ArgNo, + PartBase + i * RegisterVT.getStoreSize().getKnownMinValue()); if (NumRegs > 1 && i == 0) MyFlags.Flags.setSplit(); // if it isn't first piece, alignment must be 1 @@ -10686,7 +10687,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) { } if (NeedsRegBlock && Value == NumValues - 1) Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast(); - PartBase += VT.getStoreSize().getKnownMinSize(); + PartBase += VT.getStoreSize().getKnownMinValue(); } } diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index fe5a0f3..0c9caa7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -9343,7 +9343,7 @@ TargetLowering::IncrementMemoryAddress(SDValue Addr, SDValue Mask, } else if (DataVT.isScalableVector()) { Increment = DAG.getVScale(DL, AddrVT, APInt(AddrVT.getFixedSizeInBits(), - DataVT.getStoreSize().getKnownMinSize())); + DataVT.getStoreSize().getKnownMinValue())); } else Increment = DAG.getConstant(DataVT.getStoreSize(), DL, AddrVT); @@ -10341,7 +10341,7 @@ SDValue TargetLowering::expandVectorSplice(SDNode *Node, // Store the hi part of CONCAT_VECTORS(V1, V2) SDValue OffsetToV2 = DAG.getVScale( DL, PtrVT, - APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinSize())); + APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinValue())); SDValue StackPtr2 = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, OffsetToV2); SDValue StoreV2 = DAG.getStore(StoreV1, DL, V2, StackPtr2, PtrInfo); @@ -10362,9 +10362,10 @@ SDValue TargetLowering::expandVectorSplice(SDNode *Node, DAG.getConstant(TrailingElts * EltByteSize, DL, PtrVT); if (TrailingElts > VT.getVectorMinNumElements()) { - SDValue VLBytes = DAG.getVScale( - DL, PtrVT, - APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinSize())); + SDValue VLBytes = + DAG.getVScale(DL, PtrVT, + APInt(PtrVT.getFixedSizeInBits(), + VT.getStoreSize().getKnownMinValue())); TrailingBytes = DAG.getNode(ISD::UMIN, DL, PtrVT, TrailingBytes, VLBytes); } diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 40302d2..c7b1546 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -1627,7 +1627,7 @@ unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. TypeSize NewVTSize = NewVT.getSizeInBits(); // Convert sizes such as i33 to i64. - if (!isPowerOf2_32(NewVTSize.getKnownMinSize())) + if (!isPowerOf2_32(NewVTSize.getKnownMinValue())) NewVTSize = NewVTSize.coefficientNextPowerOf2(); return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); } diff --git a/llvm/lib/IR/DataLayout.cpp b/llvm/lib/IR/DataLayout.cpp index fb331ee..20359f6 100644 --- a/llvm/lib/IR/DataLayout.cpp +++ b/llvm/lib/IR/DataLayout.cpp @@ -800,7 +800,7 @@ Align DataLayout::getAlignment(Type *Ty, bool abi_or_pref) const { case Type::X86_MMXTyID: case Type::FixedVectorTyID: case Type::ScalableVectorTyID: { - unsigned BitWidth = getTypeSizeInBits(Ty).getKnownMinSize(); + unsigned BitWidth = getTypeSizeInBits(Ty).getKnownMinValue(); auto I = findAlignmentLowerBound(VECTOR_ALIGN, BitWidth); if (I != Alignments.end() && I->AlignType == VECTOR_ALIGN && I->TypeBitWidth == BitWidth) @@ -812,7 +812,7 @@ Align DataLayout::getAlignment(Type *Ty, bool abi_or_pref) const { // We're only calculating a natural alignment, so it doesn't have to be // based on the full size for scalable vectors. Using the minimum element // count should be enough here. - return Align(PowerOf2Ceil(getTypeStoreSize(Ty).getKnownMinSize())); + return Align(PowerOf2Ceil(getTypeStoreSize(Ty).getKnownMinValue())); } case Type::X86_AMXTyID: return Align(64); diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp index b557526..53e7477 100644 --- a/llvm/lib/IR/Instructions.cpp +++ b/llvm/lib/IR/Instructions.cpp @@ -3594,7 +3594,7 @@ bool CastInst::isBitCastable(Type *SrcTy, Type *DestTy) { // Could still have vectors of pointers if the number of elements doesn't // match - if (SrcBits.getKnownMinSize() == 0 || DestBits.getKnownMinSize() == 0) + if (SrcBits.getKnownMinValue() == 0 || DestBits.getKnownMinValue() == 0) return false; if (SrcBits != DestBits) diff --git a/llvm/lib/IR/Value.cpp b/llvm/lib/IR/Value.cpp index 6dc7af9..568b145 100644 --- a/llvm/lib/IR/Value.cpp +++ b/llvm/lib/IR/Value.cpp @@ -855,7 +855,7 @@ uint64_t Value::getPointerDereferenceableBytes(const DataLayout &DL, if (Type *ArgMemTy = A->getPointeeInMemoryValueType()) { if (ArgMemTy->isSized()) { // FIXME: Why isn't this the type alloc size? - DerefBytes = DL.getTypeStoreSize(ArgMemTy).getKnownMinSize(); + DerefBytes = DL.getTypeStoreSize(ArgMemTy).getKnownMinValue(); } } } @@ -899,7 +899,7 @@ uint64_t Value::getPointerDereferenceableBytes(const DataLayout &DL, } else if (auto *AI = dyn_cast(this)) { if (!AI->isArrayAllocation()) { DerefBytes = - DL.getTypeStoreSize(AI->getAllocatedType()).getKnownMinSize(); + DL.getTypeStoreSize(AI->getAllocatedType()).getKnownMinValue(); CanBeNull = false; CanBeFreed = false; } diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index a0d900c..2ee78b9 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -3945,7 +3945,7 @@ void AArch64DAGToDAGISel::SelectTagP(SDNode *N) { // vector types larger than NEON don't have a matching SubRegIndex. static SDNode *extractSubReg(SelectionDAG *DAG, EVT VT, SDValue V) { assert(V.getValueType().isScalableVector() && - V.getValueType().getSizeInBits().getKnownMinSize() == + V.getValueType().getSizeInBits().getKnownMinValue() == AArch64::SVEBitsPerBlock && "Expected to extract from a packed scalable vector!"); assert(VT.isFixedLengthVector() && @@ -3972,7 +3972,7 @@ static SDNode *extractSubReg(SelectionDAG *DAG, EVT VT, SDValue V) { // vector types larger than NEON don't have a matching SubRegIndex. static SDNode *insertSubReg(SelectionDAG *DAG, EVT VT, SDValue V) { assert(VT.isScalableVector() && - VT.getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock && + VT.getSizeInBits().getKnownMinValue() == AArch64::SVEBitsPerBlock && "Expected to insert into a packed scalable vector!"); assert(V.getValueType().isFixedLengthVector() && "Expected to insert a fixed length vector!"); @@ -5697,7 +5697,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N, return false; TypeSize TS = MemVT.getSizeInBits(); - int64_t MemWidthBytes = static_cast(TS.getKnownMinSize()) / 8; + int64_t MemWidthBytes = static_cast(TS.getKnownMinValue()) / 8; int64_t MulImm = cast(VScale.getOperand(0))->getSExtValue(); if ((MulImm % MemWidthBytes) != 0) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index d90b810..594397f 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -205,7 +205,7 @@ static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { assert(VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) && "Expected legal vector type!"); return VT.isFixedLengthVector() || - VT.getSizeInBits().getKnownMinSize() == AArch64::SVEBitsPerBlock; + VT.getSizeInBits().getKnownMinValue() == AArch64::SVEBitsPerBlock; } // Returns true for ####_MERGE_PASSTHRU opcodes, whose operands have a leading @@ -6573,7 +6573,7 @@ SDValue AArch64TargetLowering::LowerFormalArguments( (VA.getValVT().isScalableVector() || Subtarget->isWindowsArm64EC()) && "Indirect arguments should be scalable on most subtargets"); - uint64_t PartSize = VA.getValVT().getStoreSize().getKnownMinSize(); + uint64_t PartSize = VA.getValVT().getStoreSize().getKnownMinValue(); unsigned NumParts = 1; if (Ins[i].Flags.isInConsecutiveRegs()) { assert(!Ins[i].Flags.isInConsecutiveRegsLast()); @@ -7430,7 +7430,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, assert((isScalable || Subtarget->isWindowsArm64EC()) && "Indirect arguments should be scalable on most subtargets"); - uint64_t StoreSize = VA.getValVT().getStoreSize().getKnownMinSize(); + uint64_t StoreSize = VA.getValVT().getStoreSize().getKnownMinValue(); uint64_t PartSize = StoreSize; unsigned NumParts = 1; if (Outs[i].Flags.isInConsecutiveRegs()) { @@ -11743,7 +11743,7 @@ SDValue AArch64TargetLowering::LowerDUPQLane(SDValue Op, return SDValue(); // Current lowering only supports the SVE-ACLE types. - if (VT.getSizeInBits().getKnownMinSize() != AArch64::SVEBitsPerBlock) + if (VT.getSizeInBits().getKnownMinValue() != AArch64::SVEBitsPerBlock) return SDValue(); // The DUPQ operation is indepedent of element type so normalise to i64s. @@ -17841,11 +17841,11 @@ static SDValue LowerSVEIntrinsicEXT(SDNode *N, SelectionDAG &DAG) { assert(VT.isScalableVector() && "Expected a scalable vector."); // Current lowering only supports the SVE-ACLE types. - if (VT.getSizeInBits().getKnownMinSize() != AArch64::SVEBitsPerBlock) + if (VT.getSizeInBits().getKnownMinValue() != AArch64::SVEBitsPerBlock) return SDValue(); unsigned ElemSize = VT.getVectorElementType().getSizeInBits() / 8; - unsigned ByteSize = VT.getSizeInBits().getKnownMinSize() / 8; + unsigned ByteSize = VT.getSizeInBits().getKnownMinValue() / 8; EVT ByteVT = EVT::getVectorVT(Ctx, MVT::i8, ElementCount::getScalable(ByteSize)); @@ -18482,7 +18482,7 @@ static SDValue performLD1Combine(SDNode *N, SelectionDAG &DAG, unsigned Opc) { SDLoc DL(N); EVT VT = N->getValueType(0); - if (VT.getSizeInBits().getKnownMinSize() > AArch64::SVEBitsPerBlock) + if (VT.getSizeInBits().getKnownMinValue() > AArch64::SVEBitsPerBlock) return SDValue(); EVT ContainerVT = VT; @@ -20768,7 +20768,7 @@ static SDValue performScatterStoreCombine(SDNode *N, SelectionDAG &DAG, MVT SrcElVT = SrcVT.getVectorElementType().getSimpleVT(); // Make sure that source data will fit into an SVE register - if (SrcVT.getSizeInBits().getKnownMinSize() > AArch64::SVEBitsPerBlock) + if (SrcVT.getSizeInBits().getKnownMinValue() > AArch64::SVEBitsPerBlock) return SDValue(); // For FPs, ACLE only supports _packed_ single and double precision types. @@ -20870,7 +20870,7 @@ static SDValue performGatherLoadCombine(SDNode *N, SelectionDAG &DAG, SDLoc DL(N); // Make sure that the loaded data will fit into an SVE register - if (RetVT.getSizeInBits().getKnownMinSize() > AArch64::SVEBitsPerBlock) + if (RetVT.getSizeInBits().getKnownMinValue() > AArch64::SVEBitsPerBlock) return SDValue(); // Depending on the addressing mode, this is either a pointer or a vector of @@ -22418,7 +22418,7 @@ bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters( const DataLayout &DL) const { if (!Ty->isArrayTy()) { const TypeSize &TySize = Ty->getPrimitiveSizeInBits(); - return TySize.isScalable() && TySize.getKnownMinSize() > 128; + return TySize.isScalable() && TySize.getKnownMinValue() > 128; } // All non aggregate members of the type must have the same type diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index a10d8bc..d7e4220 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -2647,11 +2647,11 @@ bool AArch64InstrInfo::getMemOperandWithOffsetWidth( // set to 1. if (LdSt.getNumExplicitOperands() == 3) { BaseOp = &LdSt.getOperand(1); - Offset = LdSt.getOperand(2).getImm() * Scale.getKnownMinSize(); + Offset = LdSt.getOperand(2).getImm() * Scale.getKnownMinValue(); } else { assert(LdSt.getNumExplicitOperands() == 4 && "invalid number of operands"); BaseOp = &LdSt.getOperand(2); - Offset = LdSt.getOperand(3).getImm() * Scale.getKnownMinSize(); + Offset = LdSt.getOperand(3).getImm() * Scale.getKnownMinValue(); } OffsetIsScalable = Scale.isScalable(); @@ -4694,7 +4694,7 @@ int llvm::isAArch64FrameOffsetLegal(const MachineInstr &MI, // Construct the complete offset. bool IsMulVL = ScaleValue.isScalable(); - unsigned Scale = ScaleValue.getKnownMinSize(); + unsigned Scale = ScaleValue.getKnownMinValue(); int64_t Offset = IsMulVL ? SOffset.getScalable() : SOffset.getFixed(); const MachineOperand &ImmOpnd = @@ -4712,7 +4712,7 @@ int llvm::isAArch64FrameOffsetLegal(const MachineInstr &MI, MaxOff)) llvm_unreachable("unhandled opcode in isAArch64FrameOffsetLegal"); - Scale = ScaleValue.getKnownMinSize(); + Scale = ScaleValue.getKnownMinValue(); assert(IsMulVL == ScaleValue.isScalable() && "Unscaled opcode has different value for scalable"); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 8c1c8b55..860f202 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -13844,8 +13844,8 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts( LLVMContext &Context = *DAG.getContext(); EVT ValueEltVT = ValueVT.getVectorElementType(); EVT PartEltVT = PartVT.getVectorElementType(); - unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinSize(); - unsigned PartVTBitSize = PartVT.getSizeInBits().getKnownMinSize(); + unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinValue(); + unsigned PartVTBitSize = PartVT.getSizeInBits().getKnownMinValue(); if (PartVTBitSize % ValueVTBitSize == 0) { assert(PartVTBitSize >= ValueVTBitSize); // If the element types are different, bitcast to the same element type of @@ -13896,8 +13896,8 @@ SDValue RISCVTargetLowering::joinRegisterPartsIntoValue( SDValue Val = Parts[0]; EVT ValueEltVT = ValueVT.getVectorElementType(); EVT PartEltVT = PartVT.getVectorElementType(); - unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinSize(); - unsigned PartVTBitSize = PartVT.getSizeInBits().getKnownMinSize(); + unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinValue(); + unsigned PartVTBitSize = PartVT.getSizeInBits().getKnownMinValue(); if (PartVTBitSize % ValueVTBitSize == 0) { assert(PartVTBitSize >= ValueVTBitSize); EVT SameEltTypeVT = ValueVT; diff --git a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp index 7dace08..dd1a3b7 100644 --- a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp +++ b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp @@ -204,7 +204,7 @@ doPromotion(Function *F, FunctionAnalysisManager &FAM, for (auto *I : Params) if (auto *VT = dyn_cast(I)) LargestVectorWidth = std::max( - LargestVectorWidth, VT->getPrimitiveSizeInBits().getKnownMinSize()); + LargestVectorWidth, VT->getPrimitiveSizeInBits().getKnownMinValue()); // Recompute the parameter attributes list based on the new arguments for // the function. diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index 16e1293..2c4fb12 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -2704,8 +2704,9 @@ ChangeStatus Attributor::rewriteFunctionSignatures( uint64_t LargestVectorWidth = 0; for (auto *I : NewArgumentTypes) if (auto *VT = dyn_cast(I)) - LargestVectorWidth = std::max( - LargestVectorWidth, VT->getPrimitiveSizeInBits().getKnownMinSize()); + LargestVectorWidth = + std::max(LargestVectorWidth, + VT->getPrimitiveSizeInBits().getKnownMinValue()); FunctionType *OldFnTy = OldFn->getFunctionType(); Type *RetTy = OldFnTy->getReturnType(); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 014ad4e..11a658f 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -2703,7 +2703,7 @@ Value *InstCombinerImpl::matchSelectFromAndOr(Value *A, Value *C, Value *B, unsigned Elts = VecTy->getElementCount().getKnownMinValue(); // For a fixed or scalable vector, get the size in bits of N x iM; for a // scalar this is just M. - unsigned SelEltSize = SelTy->getPrimitiveSizeInBits().getKnownMinSize(); + unsigned SelEltSize = SelTy->getPrimitiveSizeInBits().getKnownMinValue(); Type *EltTy = Builder.getIntNTy(SelEltSize / Elts); SelTy = VectorType::get(EltTy, VecTy->getElementCount()); } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp index 75ccb10..23de923 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp @@ -121,14 +121,15 @@ Instruction *InstCombinerImpl::PromoteCastOfAllocation(BitCastInst &CI, if (!AI.hasOneUse() && CastElTyAlign == AllocElTyAlign) return nullptr; // The alloc and cast types should be either both fixed or both scalable. - uint64_t AllocElTySize = DL.getTypeAllocSize(AllocElTy).getKnownMinSize(); - uint64_t CastElTySize = DL.getTypeAllocSize(CastElTy).getKnownMinSize(); + uint64_t AllocElTySize = DL.getTypeAllocSize(AllocElTy).getKnownMinValue(); + uint64_t CastElTySize = DL.getTypeAllocSize(CastElTy).getKnownMinValue(); if (CastElTySize == 0 || AllocElTySize == 0) return nullptr; // If the allocation has multiple uses, only promote it if we're not // shrinking the amount of memory being allocated. - uint64_t AllocElTyStoreSize = DL.getTypeStoreSize(AllocElTy).getKnownMinSize(); - uint64_t CastElTyStoreSize = DL.getTypeStoreSize(CastElTy).getKnownMinSize(); + uint64_t AllocElTyStoreSize = + DL.getTypeStoreSize(AllocElTy).getKnownMinValue(); + uint64_t CastElTyStoreSize = DL.getTypeStoreSize(CastElTy).getKnownMinValue(); if (!AI.hasOneUse() && CastElTyStoreSize < AllocElTyStoreSize) return nullptr; // See if we can satisfy the modulus by pulling a scale out of the array diff --git a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp index 640ba90..1b427f3 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp @@ -384,7 +384,7 @@ Instruction *InstCombinerImpl::visitAllocaInst(AllocaInst &AI) { // Move all alloca's of zero byte objects to the entry block and merge them // together. Note that we only do this for alloca's, because malloc should // allocate and return a unique pointer, even for a zero byte allocation. - if (DL.getTypeAllocSize(AI.getAllocatedType()).getKnownMinSize() == 0) { + if (DL.getTypeAllocSize(AI.getAllocatedType()).getKnownMinValue() == 0) { // For a zero sized alloca there is no point in doing an array allocation. // This is helpful if the array size is a complicated expression not used // elsewhere. @@ -402,7 +402,7 @@ Instruction *InstCombinerImpl::visitAllocaInst(AllocaInst &AI) { AllocaInst *EntryAI = dyn_cast(FirstInst); if (!EntryAI || !EntryAI->getAllocatedType()->isSized() || DL.getTypeAllocSize(EntryAI->getAllocatedType()) - .getKnownMinSize() != 0) { + .getKnownMinValue() != 0) { AI.moveBefore(FirstInst); return &AI; } diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index 48f00fa..d29d5ba 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -2694,7 +2694,7 @@ Instruction *InstCombinerImpl::visitGetElementPtrInst(GetElementPtrInst &GEP) { BasePtrOffset.isNonNegative()) { APInt AllocSize( IdxWidth, - DL.getTypeAllocSize(AI->getAllocatedType()).getKnownMinSize()); + DL.getTypeAllocSize(AI->getAllocatedType()).getKnownMinValue()); if (BasePtrOffset.ule(AllocSize)) { return GetElementPtrInst::CreateInBounds( GEP.getSourceElementType(), PtrOp, Indices, GEP.getName()); diff --git a/llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp b/llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp index 02ea178..d17c399 100644 --- a/llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp +++ b/llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp @@ -254,7 +254,7 @@ struct AssumeBuilderState { unsigned DerefSize = MemInst->getModule() ->getDataLayout() .getTypeStoreSize(AccType) - .getKnownMinSize(); + .getKnownMinValue(); if (DerefSize != 0) { addKnowledge({Attribute::Dereferenceable, DerefSize, Pointer}); if (!NullPointerIsDefined(MemInst->getFunction(), diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index ecfdae6..5aab3d1 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -5187,7 +5187,7 @@ ElementCount LoopVectorizationCostModel::getMaximizedVFForTarget( // Ensure MaxVF is a power of 2; the dependence distance bound may not be. // Note that both WidestRegister and WidestType may not be a powers of 2. auto MaxVectorElementCount = ElementCount::get( - PowerOf2Floor(WidestRegister.getKnownMinSize() / WidestType), + PowerOf2Floor(WidestRegister.getKnownMinValue() / WidestType), ComputeScalableMaxVF); MaxVectorElementCount = MinVF(MaxVectorElementCount, MaxSafeVF); LLVM_DEBUG(dbgs() << "LV: The Widest register safe to use is: " @@ -5228,7 +5228,7 @@ ElementCount LoopVectorizationCostModel::getMaximizedVFForTarget( if (MaximizeBandwidth || (MaximizeBandwidth.getNumOccurrences() == 0 && TTI.shouldMaximizeVectorBandwidth(RegKind))) { auto MaxVectorElementCountMaxBW = ElementCount::get( - PowerOf2Floor(WidestRegister.getKnownMinSize() / SmallestType), + PowerOf2Floor(WidestRegister.getKnownMinValue() / SmallestType), ComputeScalableMaxVF); MaxVectorElementCountMaxBW = MinVF(MaxVectorElementCountMaxBW, MaxSafeVF); diff --git a/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp b/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp index 1f6d238..05bf91a 100644 --- a/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp +++ b/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp @@ -139,14 +139,14 @@ TEST(ScalableVectorMVTsTest, SizeQueries) { EXPECT_EQ(nxv4i32.getSizeInBits(), nxv2i64.getSizeInBits()); EXPECT_EQ(nxv2f64.getSizeInBits(), nxv2i64.getSizeInBits()); EXPECT_NE(nxv2i32.getSizeInBits(), nxv4i32.getSizeInBits()); - EXPECT_LT(nxv2i32.getSizeInBits().getKnownMinSize(), - nxv2i64.getSizeInBits().getKnownMinSize()); - EXPECT_LE(nxv4i32.getSizeInBits().getKnownMinSize(), - nxv2i64.getSizeInBits().getKnownMinSize()); - EXPECT_GT(nxv4i32.getSizeInBits().getKnownMinSize(), - nxv2i32.getSizeInBits().getKnownMinSize()); - EXPECT_GE(nxv2i64.getSizeInBits().getKnownMinSize(), - nxv4i32.getSizeInBits().getKnownMinSize()); + EXPECT_LT(nxv2i32.getSizeInBits().getKnownMinValue(), + nxv2i64.getSizeInBits().getKnownMinValue()); + EXPECT_LE(nxv4i32.getSizeInBits().getKnownMinValue(), + nxv2i64.getSizeInBits().getKnownMinValue()); + EXPECT_GT(nxv4i32.getSizeInBits().getKnownMinValue(), + nxv2i32.getSizeInBits().getKnownMinValue()); + EXPECT_GE(nxv2i64.getSizeInBits().getKnownMinValue(), + nxv4i32.getSizeInBits().getKnownMinValue()); // Check equivalence and ordering on fixed types. EXPECT_EQ(v4i32.getSizeInBits(), v2i64.getSizeInBits()); @@ -168,10 +168,10 @@ TEST(ScalableVectorMVTsTest, SizeQueries) { // Check that we can query the known minimum size for both scalable and // fixed length types. - EXPECT_EQ(nxv2i32.getSizeInBits().getKnownMinSize(), 64U); - EXPECT_EQ(nxv2f64.getSizeInBits().getKnownMinSize(), 128U); - EXPECT_EQ(v2i32.getSizeInBits().getKnownMinSize(), - nxv2i32.getSizeInBits().getKnownMinSize()); + EXPECT_EQ(nxv2i32.getSizeInBits().getKnownMinValue(), 64U); + EXPECT_EQ(nxv2f64.getSizeInBits().getKnownMinValue(), 128U); + EXPECT_EQ(v2i32.getSizeInBits().getKnownMinValue(), + nxv2i32.getSizeInBits().getKnownMinValue()); // Check scalable property. ASSERT_FALSE(v4i32.getSizeInBits().isScalable()); diff --git a/llvm/unittests/IR/VectorTypesTest.cpp b/llvm/unittests/IR/VectorTypesTest.cpp index af0f29f..d58bab5 100644 --- a/llvm/unittests/IR/VectorTypesTest.cpp +++ b/llvm/unittests/IR/VectorTypesTest.cpp @@ -287,7 +287,7 @@ TEST(VectorTypesTest, FixedLenComparisons) { auto *V2Int64Ty = FixedVectorType::get(Int64Ty, 2); TypeSize V2I32Len = V2Int32Ty->getPrimitiveSizeInBits(); - EXPECT_EQ(V2I32Len.getKnownMinSize(), 64U); + EXPECT_EQ(V2I32Len.getKnownMinValue(), 64U); EXPECT_FALSE(V2I32Len.isScalable()); EXPECT_LT(V2Int32Ty->getPrimitiveSizeInBits().getFixedSize(), @@ -333,32 +333,32 @@ TEST(VectorTypesTest, ScalableComparisons) { auto *ScV2Int64Ty = ScalableVectorType::get(Int64Ty, 2); TypeSize ScV2I32Len = ScV2Int32Ty->getPrimitiveSizeInBits(); - EXPECT_EQ(ScV2I32Len.getKnownMinSize(), 64U); + EXPECT_EQ(ScV2I32Len.getKnownMinValue(), 64U); EXPECT_TRUE(ScV2I32Len.isScalable()); - EXPECT_LT(ScV2Int32Ty->getPrimitiveSizeInBits().getKnownMinSize(), - ScV4Int32Ty->getPrimitiveSizeInBits().getKnownMinSize()); - EXPECT_GT(ScV2Int64Ty->getPrimitiveSizeInBits().getKnownMinSize(), - ScV2Int32Ty->getPrimitiveSizeInBits().getKnownMinSize()); - EXPECT_EQ(ScV4Int32Ty->getPrimitiveSizeInBits().getKnownMinSize(), - ScV2Int64Ty->getPrimitiveSizeInBits().getKnownMinSize()); - EXPECT_NE(ScV2Int32Ty->getPrimitiveSizeInBits().getKnownMinSize(), - ScV2Int64Ty->getPrimitiveSizeInBits().getKnownMinSize()); + EXPECT_LT(ScV2Int32Ty->getPrimitiveSizeInBits().getKnownMinValue(), + ScV4Int32Ty->getPrimitiveSizeInBits().getKnownMinValue()); + EXPECT_GT(ScV2Int64Ty->getPrimitiveSizeInBits().getKnownMinValue(), + ScV2Int32Ty->getPrimitiveSizeInBits().getKnownMinValue()); + EXPECT_EQ(ScV4Int32Ty->getPrimitiveSizeInBits().getKnownMinValue(), + ScV2Int64Ty->getPrimitiveSizeInBits().getKnownMinValue()); + EXPECT_NE(ScV2Int32Ty->getPrimitiveSizeInBits().getKnownMinValue(), + ScV2Int64Ty->getPrimitiveSizeInBits().getKnownMinValue()); // Check the DataLayout interfaces. EXPECT_EQ(DL.getTypeSizeInBits(ScV2Int64Ty), DL.getTypeSizeInBits(ScV4Int32Ty)); - EXPECT_EQ(DL.getTypeSizeInBits(ScV2Int32Ty).getKnownMinSize(), 64U); + EXPECT_EQ(DL.getTypeSizeInBits(ScV2Int32Ty).getKnownMinValue(), 64U); EXPECT_EQ(DL.getTypeStoreSize(ScV2Int64Ty), DL.getTypeStoreSize(ScV4Int32Ty)); EXPECT_NE(DL.getTypeStoreSizeInBits(ScV2Int32Ty), DL.getTypeStoreSizeInBits(ScV2Int64Ty)); - EXPECT_EQ(DL.getTypeStoreSizeInBits(ScV2Int32Ty).getKnownMinSize(), 64U); - EXPECT_EQ(DL.getTypeStoreSize(ScV2Int64Ty).getKnownMinSize(), 16U); + EXPECT_EQ(DL.getTypeStoreSizeInBits(ScV2Int32Ty).getKnownMinValue(), 64U); + EXPECT_EQ(DL.getTypeStoreSize(ScV2Int64Ty).getKnownMinValue(), 16U); EXPECT_EQ(DL.getTypeAllocSize(ScV4Int32Ty), DL.getTypeAllocSize(ScV2Int64Ty)); EXPECT_NE(DL.getTypeAllocSizeInBits(ScV2Int32Ty), DL.getTypeAllocSizeInBits(ScV2Int64Ty)); - EXPECT_EQ(DL.getTypeAllocSizeInBits(ScV4Int32Ty).getKnownMinSize(), 128U); - EXPECT_EQ(DL.getTypeAllocSize(ScV2Int32Ty).getKnownMinSize(), 8U); + EXPECT_EQ(DL.getTypeAllocSizeInBits(ScV4Int32Ty).getKnownMinValue(), 128U); + EXPECT_EQ(DL.getTypeAllocSize(ScV2Int32Ty).getKnownMinValue(), 8U); ASSERT_TRUE(DL.typeSizeEqualsStoreSize(ScV4Int32Ty)); } @@ -375,8 +375,8 @@ TEST(VectorTypesTest, CrossComparisons) { EXPECT_NE(V4Int32Ty->getPrimitiveSizeInBits(), ScV4Int32Ty->getPrimitiveSizeInBits()); // If we are only checking the minimum, then they are the same size. - EXPECT_EQ(V4Int32Ty->getPrimitiveSizeInBits().getKnownMinSize(), - ScV4Int32Ty->getPrimitiveSizeInBits().getKnownMinSize()); + EXPECT_EQ(V4Int32Ty->getPrimitiveSizeInBits().getKnownMinValue(), + ScV4Int32Ty->getPrimitiveSizeInBits().getKnownMinValue()); // We can't use ordering comparisons (<,<=,>,>=) between scalable and // non-scalable vector sizes. diff --git a/llvm/unittests/Support/TypeSizeTest.cpp b/llvm/unittests/Support/TypeSizeTest.cpp index 6e566be..c64134b 100644 --- a/llvm/unittests/Support/TypeSizeTest.cpp +++ b/llvm/unittests/Support/TypeSizeTest.cpp @@ -66,9 +66,9 @@ constexpr TypeSize TSFixed32 = TypeSize::Fixed(32); static_assert(TSFixed0.getFixedSize() == 0); static_assert(TSFixed1.getFixedSize() == 1); static_assert(TSFixed32.getFixedSize() == 32); -static_assert(TSFixed32.getKnownMinSize() == 32); +static_assert(TSFixed32.getKnownMinValue() == 32); -static_assert(TypeSize::Scalable(32).getKnownMinSize() == 32); +static_assert(TypeSize::Scalable(32).getKnownMinValue() == 32); static_assert(TSFixed32 * 2 == TypeSize::Fixed(64)); static_assert(TSFixed32 * 2u == TypeSize::Fixed(64)); -- 2.7.4