From 48e4851f492fce44ba24572ec36f0eee51c46555 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Fri, 17 Nov 2017 14:57:11 +0800 Subject: [PATCH] ARM: at91: add sama5d2 smc header Add a header for SAMA5D2 SMC since it's not compatible with SAMA5D3 one. Signed-off-by: Ludovic Desroches [wenyou: fix the wrong base address of the SMC register] Signed-off-by: Wenyou Yang --- arch/arm/mach-at91/include/mach/sama5d2_smc.h | 76 +++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 arch/arm/mach-at91/include/mach/sama5d2_smc.h diff --git a/arch/arm/mach-at91/include/mach/sama5d2_smc.h b/arch/arm/mach-at91/include/mach/sama5d2_smc.h new file mode 100644 index 0000000..7ddb728 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d2_smc.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2017 Microchip Corporation. + * + * Static Memory Controllers (SMC) - System peripherals registers. + * Based on SAMA5D2 datasheet. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SAMA5D2_SMC_H +#define SAMA5D2_SMC_H + +#ifdef __ASSEMBLY__ +#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x700) +#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x704) +#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x708) +#define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x70c) +#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x710) +#else +struct at91_cs { + u32 setup; /* 0x600 SMC Setup Register */ + u32 pulse; /* 0x604 SMC Pulse Register */ + u32 cycle; /* 0x608 SMC Cycle Register */ + u32 timings; /* 0x60C SMC Cycle Register */ + u32 mode; /* 0x610 SMC Mode Register */ +}; + +struct at91_smc { + struct at91_cs cs[4]; +}; +#endif /* __ASSEMBLY__ */ + +#define AT91_SMC_SETUP_NWE(x) (x & 0x3f) +#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) +#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) +#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) + +#define AT91_SMC_PULSE_NWE(x) (x & 0x7f) +#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) +#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) +#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) + +#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) +#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) + +#define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) +#define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) +#define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8) +#define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12) +#define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16) +#define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24) +#define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28) +#define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31) + +#define AT91_SMC_MODE_RM_NCS 0x00000000 +#define AT91_SMC_MODE_RM_NRD 0x00000001 +#define AT91_SMC_MODE_WM_NCS 0x00000000 +#define AT91_SMC_MODE_WM_NWE 0x00000002 + +#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 +#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 +#define AT91_SMC_MODE_EXNW_READY 0x00000030 + +#define AT91_SMC_MODE_BAT 0x00000100 +#define AT91_SMC_MODE_DBW_8 0x00000000 +#define AT91_SMC_MODE_DBW_16 0x00001000 +#define AT91_SMC_MODE_DBW_32 0x00002000 +#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) +#define AT91_SMC_MODE_TDF 0x00100000 +#define AT91_SMC_MODE_PMEN 0x01000000 +#define AT91_SMC_MODE_PS_4 0x00000000 +#define AT91_SMC_MODE_PS_8 0x10000000 +#define AT91_SMC_MODE_PS_16 0x20000000 +#define AT91_SMC_MODE_PS_32 0x30000000 + +#endif -- 2.7.4