From 48d4b677a9bd28af33987580badcbe98ddbaa001 Mon Sep 17 00:00:00 2001 From: "Sidorov, Dmitry" Date: Mon, 17 Oct 2022 07:09:36 -0700 Subject: [PATCH] Add SPV_INTEL_fpga_dsp_control Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_fpga_dsp_control.asciidoc Signed-off-by: Sidorov, Dmitry --- include/spirv/unified1/spirv.bf | 2 ++ include/spirv/unified1/spirv.core.grammar.json | 16 ++++++++++++++++ include/spirv/unified1/spirv.cs | 2 ++ include/spirv/unified1/spirv.h | 2 ++ include/spirv/unified1/spirv.hpp | 2 ++ include/spirv/unified1/spirv.hpp11 | 2 ++ include/spirv/unified1/spirv.json | 2 ++ include/spirv/unified1/spirv.lua | 2 ++ include/spirv/unified1/spirv.py | 2 ++ include/spirv/unified1/spv.d | 2 ++ 10 files changed, 34 insertions(+) diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf index 563b61e..3b53ebe 100644 --- a/include/spirv/unified1/spirv.bf +++ b/include/spirv/unified1/spirv.bf @@ -559,6 +559,7 @@ namespace Spv PrefetchINTEL = 5902, StallEnableINTEL = 5905, FuseLoopsInFunctionINTEL = 5907, + MathOpDSPModeINTEL = 5909, AliasScopeINTEL = 5914, NoAliasINTEL = 5915, InitiationIntervalINTEL = 5917, @@ -1104,6 +1105,7 @@ namespace Spv FPGAMemoryAccessesINTEL = 5898, FPGAClusterAttributesINTEL = 5904, LoopFuseINTEL = 5906, + FPGADSPControlINTEL = 5908, MemoryAccessAliasingINTEL = 5910, FPGAInvocationPipeliningAttributesINTEL = 5916, FPGABufferLocationINTEL = 5920, diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json index f51deb1..d17c9c0 100644 --- a/include/spirv/unified1/spirv.core.grammar.json +++ b/include/spirv/unified1/spirv.core.grammar.json @@ -11947,6 +11947,16 @@ "version" : "None" }, { + "enumerant" : "MathOpDSPModeINTEL", + "value" : 5909, + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'Mode'" }, + { "kind" : "LiteralInteger", "name" : "'Propagate'" } + ], + "capabilities" : [ "FPGADSPControlINTEL" ], + "version" : "None" + }, + { "enumerant" : "AliasScopeINTEL", "value" : 5914, "parameters" : [ @@ -14169,6 +14179,12 @@ "version" : "None" }, { + "enumerant" : "FPGADSPControlINTEL", + "value" : 5908, + "extensions" : [ "SPV_INTEL_fpga_dsp_control" ], + "version" : "None" + }, + { "enumerant" : "MemoryAccessAliasingINTEL", "value" : 5910, "extensions" : [ "SPV_INTEL_memory_access_aliasing" ], diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs index 2c1fd1d..864ca2d 100644 --- a/include/spirv/unified1/spirv.cs +++ b/include/spirv/unified1/spirv.cs @@ -558,6 +558,7 @@ namespace Spv PrefetchINTEL = 5902, StallEnableINTEL = 5905, FuseLoopsInFunctionINTEL = 5907, + MathOpDSPModeINTEL = 5909, AliasScopeINTEL = 5914, NoAliasINTEL = 5915, InitiationIntervalINTEL = 5917, @@ -1103,6 +1104,7 @@ namespace Spv FPGAMemoryAccessesINTEL = 5898, FPGAClusterAttributesINTEL = 5904, LoopFuseINTEL = 5906, + FPGADSPControlINTEL = 5908, MemoryAccessAliasingINTEL = 5910, FPGAInvocationPipeliningAttributesINTEL = 5916, FPGABufferLocationINTEL = 5920, diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h index 51e4dca..120553e 100644 --- a/include/spirv/unified1/spirv.h +++ b/include/spirv/unified1/spirv.h @@ -564,6 +564,7 @@ typedef enum SpvDecoration_ { SpvDecorationPrefetchINTEL = 5902, SpvDecorationStallEnableINTEL = 5905, SpvDecorationFuseLoopsInFunctionINTEL = 5907, + SpvDecorationMathOpDSPModeINTEL = 5909, SpvDecorationAliasScopeINTEL = 5914, SpvDecorationNoAliasINTEL = 5915, SpvDecorationInitiationIntervalINTEL = 5917, @@ -1103,6 +1104,7 @@ typedef enum SpvCapability_ { SpvCapabilityFPGAMemoryAccessesINTEL = 5898, SpvCapabilityFPGAClusterAttributesINTEL = 5904, SpvCapabilityLoopFuseINTEL = 5906, + SpvCapabilityFPGADSPControlINTEL = 5908, SpvCapabilityMemoryAccessAliasingINTEL = 5910, SpvCapabilityFPGAInvocationPipeliningAttributesINTEL = 5916, SpvCapabilityFPGABufferLocationINTEL = 5920, diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp index d199bb1..77da34d 100644 --- a/include/spirv/unified1/spirv.hpp +++ b/include/spirv/unified1/spirv.hpp @@ -560,6 +560,7 @@ enum Decoration { DecorationPrefetchINTEL = 5902, DecorationStallEnableINTEL = 5905, DecorationFuseLoopsInFunctionINTEL = 5907, + DecorationMathOpDSPModeINTEL = 5909, DecorationAliasScopeINTEL = 5914, DecorationNoAliasINTEL = 5915, DecorationInitiationIntervalINTEL = 5917, @@ -1099,6 +1100,7 @@ enum Capability { CapabilityFPGAMemoryAccessesINTEL = 5898, CapabilityFPGAClusterAttributesINTEL = 5904, CapabilityLoopFuseINTEL = 5906, + CapabilityFPGADSPControlINTEL = 5908, CapabilityMemoryAccessAliasingINTEL = 5910, CapabilityFPGAInvocationPipeliningAttributesINTEL = 5916, CapabilityFPGABufferLocationINTEL = 5920, diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 index 8bf4a9e..a9881a5 100644 --- a/include/spirv/unified1/spirv.hpp11 +++ b/include/spirv/unified1/spirv.hpp11 @@ -560,6 +560,7 @@ enum class Decoration : unsigned { PrefetchINTEL = 5902, StallEnableINTEL = 5905, FuseLoopsInFunctionINTEL = 5907, + MathOpDSPModeINTEL = 5909, AliasScopeINTEL = 5914, NoAliasINTEL = 5915, InitiationIntervalINTEL = 5917, @@ -1099,6 +1100,7 @@ enum class Capability : unsigned { FPGAMemoryAccessesINTEL = 5898, FPGAClusterAttributesINTEL = 5904, LoopFuseINTEL = 5906, + FPGADSPControlINTEL = 5908, MemoryAccessAliasingINTEL = 5910, FPGAInvocationPipeliningAttributesINTEL = 5916, FPGABufferLocationINTEL = 5920, diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json index 281219c..a62f017 100644 --- a/include/spirv/unified1/spirv.json +++ b/include/spirv/unified1/spirv.json @@ -586,6 +586,7 @@ "PrefetchINTEL": 5902, "StallEnableINTEL": 5905, "FuseLoopsInFunctionINTEL": 5907, + "MathOpDSPModeINTEL": 5909, "AliasScopeINTEL": 5914, "NoAliasINTEL": 5915, "InitiationIntervalINTEL": 5917, @@ -1079,6 +1080,7 @@ "FPGAMemoryAccessesINTEL": 5898, "FPGAClusterAttributesINTEL": 5904, "LoopFuseINTEL": 5906, + "FPGADSPControlINTEL": 5908, "MemoryAccessAliasingINTEL": 5910, "FPGAInvocationPipeliningAttributesINTEL": 5916, "FPGABufferLocationINTEL": 5920, diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua index 2eca531..c744b54 100644 --- a/include/spirv/unified1/spirv.lua +++ b/include/spirv/unified1/spirv.lua @@ -533,6 +533,7 @@ spv = { PrefetchINTEL = 5902, StallEnableINTEL = 5905, FuseLoopsInFunctionINTEL = 5907, + MathOpDSPModeINTEL = 5909, AliasScopeINTEL = 5914, NoAliasINTEL = 5915, InitiationIntervalINTEL = 5917, @@ -1061,6 +1062,7 @@ spv = { FPGAMemoryAccessesINTEL = 5898, FPGAClusterAttributesINTEL = 5904, LoopFuseINTEL = 5906, + FPGADSPControlINTEL = 5908, MemoryAccessAliasingINTEL = 5910, FPGAInvocationPipeliningAttributesINTEL = 5916, FPGABufferLocationINTEL = 5920, diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py index 5c56ec3..81e411c 100644 --- a/include/spirv/unified1/spirv.py +++ b/include/spirv/unified1/spirv.py @@ -533,6 +533,7 @@ spv = { 'PrefetchINTEL' : 5902, 'StallEnableINTEL' : 5905, 'FuseLoopsInFunctionINTEL' : 5907, + 'MathOpDSPModeINTEL' : 5909, 'AliasScopeINTEL' : 5914, 'NoAliasINTEL' : 5915, 'InitiationIntervalINTEL' : 5917, @@ -1061,6 +1062,7 @@ spv = { 'FPGAMemoryAccessesINTEL' : 5898, 'FPGAClusterAttributesINTEL' : 5904, 'LoopFuseINTEL' : 5906, + 'FPGADSPControlINTEL' : 5908, 'MemoryAccessAliasingINTEL' : 5910, 'FPGAInvocationPipeliningAttributesINTEL' : 5916, 'FPGABufferLocationINTEL' : 5920, diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d index a8c52b4..b4dd8b2 100644 --- a/include/spirv/unified1/spv.d +++ b/include/spirv/unified1/spv.d @@ -561,6 +561,7 @@ enum Decoration : uint PrefetchINTEL = 5902, StallEnableINTEL = 5905, FuseLoopsInFunctionINTEL = 5907, + MathOpDSPModeINTEL = 5909, AliasScopeINTEL = 5914, NoAliasINTEL = 5915, InitiationIntervalINTEL = 5917, @@ -1106,6 +1107,7 @@ enum Capability : uint FPGAMemoryAccessesINTEL = 5898, FPGAClusterAttributesINTEL = 5904, LoopFuseINTEL = 5906, + FPGADSPControlINTEL = 5908, MemoryAccessAliasingINTEL = 5910, FPGAInvocationPipeliningAttributesINTEL = 5916, FPGABufferLocationINTEL = 5920, -- 2.7.4