From 48ca0550ddccc3a9c46ab11600cf77688cbdb62c Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Tue, 10 Jul 2018 16:38:35 +0000 Subject: [PATCH] [GlobalISel][X86_64] Support for G_SITOFP The instruction selection is automatically handled by tablegen llvm-svn: 336703 --- llvm/lib/Target/X86/X86LegalizerInfo.cpp | 7 + llvm/lib/Target/X86/X86RegisterBankInfo.cpp | 11 + .../X86/GlobalISel/regbankselect-X86_64.mir | 161 +++++++++++ .../X86/GlobalISel/x86_64-legalize-sitofp.mir | 306 +++++++++++++++++++++ .../X86/GlobalISel/x86_64-select-sitofp.mir | 158 +++++++++++ 5 files changed, 643 insertions(+) create mode 100644 llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir create mode 100644 llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp index b8c31dd..d372cad 100644 --- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp +++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp @@ -212,6 +212,13 @@ void X86LegalizerInfo::setLegalizerInfo64bit() { setAction({extOp, s64}, Legal); } + getActionDefinitionsBuilder(G_SITOFP) + .legalForCartesianProduct({s32, s64}) + .clampScalar(1, s32, s64) + .widenScalarToNextPow2(1) + .clampScalar(0, s32, s64) + .widenScalarToNextPow2(0); + // Comparison setAction({G_ICMP, 1, s64}, Legal); diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp index 85d230e..246d6d5 100644 --- a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp @@ -198,6 +198,17 @@ X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // Instruction having only floating-point operands (all scalars in VECRReg) getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx); break; + case TargetOpcode::G_SITOFP: { + // Some of the floating-point instructions have mixed GPR and FP operands: + // fine-tune the computed mapping. + auto &Op0 = MI.getOperand(0); + auto &Op1 = MI.getOperand(1); + const LLT Ty0 = MRI.getType(Op0.getReg()); + const LLT Ty1 = MRI.getType(Op1.getReg()); + OpRegBankIdx[0] = getPartialMappingIdx(Ty0, /* isFP */ true); + OpRegBankIdx[1] = getPartialMappingIdx(Ty1, /* isFP */ false); + break; + } case TargetOpcode::G_TRUNC: case TargetOpcode::G_ANYEXT: { auto &Op0 = MI.getOperand(0); diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir index ea585ba..debf7e5 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir @@ -242,6 +242,30 @@ ret void } + define float @int32_to_float(i32 %a) { + entry: + %conv = sitofp i32 %a to float + ret float %conv + } + + define float @int64_to_float(i64 %a) { + entry: + %conv = sitofp i64 %a to float + ret float %conv + } + + define double @int32_to_double(i32 %a) { + entry: + %conv = sitofp i32 %a to double + ret double %conv + } + + define double @int64_to_double(i64 %a) { + entry: + %conv = sitofp i64 %a to double + ret double %conv + } + ... --- name: test_add_i8 @@ -1817,4 +1841,141 @@ body: | ; GREEDY: [[C1:%[0-9]+]]:vecr(s64) = G_FCONSTANT double 2.000000e+00 %0(s32) = G_FCONSTANT float 1.0 %1(s64) = G_FCONSTANT double 2.0 + +... +--- +name: int32_to_float +alignment: 4 +legalized: true +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1.entry: + liveins: $edi + + ; FAST-LABEL: name: int32_to_float + ; FAST: liveins: $edi + ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi + ; FAST: [[SITOFP:%[0-9]+]]:vecr(s32) = G_SITOFP [[COPY]](s32) + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s32) + ; FAST: $xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit $xmm0 + ; GREEDY-LABEL: name: int32_to_float + ; GREEDY: liveins: $edi + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi + ; GREEDY: [[SITOFP:%[0-9]+]]:vecr(s32) = G_SITOFP [[COPY]](s32) + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s32) + ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit $xmm0 + %0:_(s32) = COPY $edi + %1:_(s32) = G_SITOFP %0(s32) + %2:_(s128) = G_ANYEXT %1(s32) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... +--- +name: int64_to_float +alignment: 4 +legalized: true +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1.entry: + liveins: $rdi + + ; FAST-LABEL: name: int64_to_float + ; FAST: liveins: $rdi + ; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi + ; FAST: [[SITOFP:%[0-9]+]]:vecr(s32) = G_SITOFP [[COPY]](s64) + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s32) + ; FAST: $xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit $xmm0 + ; GREEDY-LABEL: name: int64_to_float + ; GREEDY: liveins: $rdi + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi + ; GREEDY: [[SITOFP:%[0-9]+]]:vecr(s32) = G_SITOFP [[COPY]](s64) + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s32) + ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit $xmm0 + %0:_(s64) = COPY $rdi + %1:_(s32) = G_SITOFP %0(s64) + %2:_(s128) = G_ANYEXT %1(s32) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... +--- +name: int32_to_double +alignment: 4 +legalized: true +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1.entry: + liveins: $edi + + ; FAST-LABEL: name: int32_to_double + ; FAST: liveins: $edi + ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi + ; FAST: [[SITOFP:%[0-9]+]]:vecr(s64) = G_SITOFP [[COPY]](s32) + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s64) + ; FAST: $xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit $xmm0 + ; GREEDY-LABEL: name: int32_to_double + ; GREEDY: liveins: $edi + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi + ; GREEDY: [[SITOFP:%[0-9]+]]:vecr(s64) = G_SITOFP [[COPY]](s32) + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s64) + ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit $xmm0 + %0:_(s32) = COPY $edi + %1:_(s64) = G_SITOFP %0(s32) + %2:_(s128) = G_ANYEXT %1(s64) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... +--- +name: int64_to_double +alignment: 4 +legalized: true +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1.entry: + liveins: $rdi + + ; FAST-LABEL: name: int64_to_double + ; FAST: liveins: $rdi + ; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi + ; FAST: [[SITOFP:%[0-9]+]]:vecr(s64) = G_SITOFP [[COPY]](s64) + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s64) + ; FAST: $xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit $xmm0 + ; GREEDY-LABEL: name: int64_to_double + ; GREEDY: liveins: $rdi + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi + ; GREEDY: [[SITOFP:%[0-9]+]]:vecr(s64) = G_SITOFP [[COPY]](s64) + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[SITOFP]](s64) + ; GREEDY: $xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit $xmm0 + %0:_(s64) = COPY $rdi + %1:_(s64) = G_SITOFP %0(s64) + %2:_(s128) = G_ANYEXT %1(s64) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + ... diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir new file mode 100644 index 0000000..a8be320 --- /dev/null +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir @@ -0,0 +1,306 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s + +--- | + ; ModuleID = 'sitofp.ll' + source_filename = "sitofp.c" + target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + target triple = "x86_64-unknown-linux-gnu" + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local float @int8_to_float(i8 signext %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i8 %a to float + ret float %conv + } + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local float @int16_to_float(i16 signext %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i16 %a to float + ret float %conv + } + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local float @int32_to_float(i32 %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i32 %a to float + ret float %conv + } + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local float @int64_to_float(i64 %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i64 %a to float + ret float %conv + } + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local double @int8_to_double(i8 signext %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i8 %a to double + ret double %conv + } + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local double @int16_to_double(i16 signext %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i16 %a to double + ret double %conv + } + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local double @int32_to_double(i32 %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i32 %a to double + ret double %conv + } + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local double @int64_to_double(i64 %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i64 %a to double + ret double %conv + } + + attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + + !llvm.module.flags = !{!0} + !llvm.ident = !{!1} + + !0 = !{i32 1, !"wchar_size", i32 4} + !1 = !{!"clang version 7.0.0 (http://llvm.org/git/clang.git a05f37359b23be7c068e19968c8f106edf6f2b34) (http://llvm.org/git/llvm.git d693de1fee74d455e20f96006aac50317ca1da6b)"} + +... +--- +name: int8_to_float +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.1.entry: + liveins: $edi + + ; CHECK-LABEL: name: int8_to_float + ; CHECK: liveins: $edi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]] + ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] + ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32) + ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) + ; CHECK: RET 0, implicit $xmm0 + %1:_(s32) = COPY $edi + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s32) = G_SITOFP %0(s8) + %3:_(s128) = G_ANYEXT %2(s32) + $xmm0 = COPY %3(s128) + RET 0, implicit $xmm0 + +... +--- +name: int16_to_float +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.1.entry: + liveins: $edi + + ; CHECK-LABEL: name: int16_to_float + ; CHECK: liveins: $edi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]] + ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] + ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32) + ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) + ; CHECK: RET 0, implicit $xmm0 + %1:_(s32) = COPY $edi + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s32) = G_SITOFP %0(s16) + %3:_(s128) = G_ANYEXT %2(s32) + $xmm0 = COPY %3(s128) + RET 0, implicit $xmm0 + +... +--- +name: int32_to_float +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1.entry: + liveins: $edi + + ; CHECK-LABEL: name: int32_to_float + ; CHECK: liveins: $edi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32) + ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) + ; CHECK: RET 0, implicit $xmm0 + %0:_(s32) = COPY $edi + %1:_(s32) = G_SITOFP %0(s32) + %2:_(s128) = G_ANYEXT %1(s32) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... +--- +name: int64_to_float +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1.entry: + liveins: $rdi + + ; CHECK-LABEL: name: int64_to_float + ; CHECK: liveins: $rdi + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi + ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s64) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32) + ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) + ; CHECK: RET 0, implicit $xmm0 + %0:_(s64) = COPY $rdi + %1:_(s32) = G_SITOFP %0(s64) + %2:_(s128) = G_ANYEXT %1(s32) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... +--- +name: int8_to_double +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.1.entry: + liveins: $edi + + ; CHECK-LABEL: name: int8_to_double + ; CHECK: liveins: $edi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]] + ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] + ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64) + ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) + ; CHECK: RET 0, implicit $xmm0 + %1:_(s32) = COPY $edi + %0:_(s8) = G_TRUNC %1(s32) + %2:_(s64) = G_SITOFP %0(s8) + %3:_(s128) = G_ANYEXT %2(s64) + $xmm0 = COPY %3(s128) + RET 0, implicit $xmm0 + +... +--- +name: int16_to_double +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.1.entry: + liveins: $edi + + ; CHECK-LABEL: name: int16_to_double + ; CHECK: liveins: $edi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]] + ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]] + ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64) + ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) + ; CHECK: RET 0, implicit $xmm0 + %1:_(s32) = COPY $edi + %0:_(s16) = G_TRUNC %1(s32) + %2:_(s64) = G_SITOFP %0(s16) + %3:_(s128) = G_ANYEXT %2(s64) + $xmm0 = COPY %3(s128) + RET 0, implicit $xmm0 + +... +--- +name: int32_to_double +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1.entry: + liveins: $edi + + ; CHECK-LABEL: name: int32_to_double + ; CHECK: liveins: $edi + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi + ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64) + ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) + ; CHECK: RET 0, implicit $xmm0 + %0:_(s32) = COPY $edi + %1:_(s64) = G_SITOFP %0(s32) + %2:_(s128) = G_ANYEXT %1(s64) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... +--- +name: int64_to_double +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.1.entry: + liveins: $rdi + + ; CHECK-LABEL: name: int64_to_double + ; CHECK: liveins: $rdi + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi + ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s64) + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64) + ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) + ; CHECK: RET 0, implicit $xmm0 + %0:_(s64) = COPY $rdi + %1:_(s64) = G_SITOFP %0(s64) + %2:_(s128) = G_ANYEXT %1(s64) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir new file mode 100644 index 0000000..896c2f4 --- /dev/null +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir @@ -0,0 +1,158 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- | + ; ModuleID = 'sitofp_legal.ll' + source_filename = "sitofp.c" + target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + target triple = "x86_64-unknown-linux-gnu" + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local float @int32_to_float(i32 %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i32 %a to float + ret float %conv + } + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local float @int64_to_float(i64 %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i64 %a to float + ret float %conv + } + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local double @int32_to_double(i32 %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i32 %a to double + ret double %conv + } + + ; Function Attrs: norecurse nounwind readnone uwtable + define dso_local double @int64_to_double(i64 %a) local_unnamed_addr #0 { + entry: + %conv = sitofp i64 %a to double + ret double %conv + } + + attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } + + !llvm.module.flags = !{!0} + !llvm.ident = !{!1} + + !0 = !{i32 1, !"wchar_size", i32 4} + !1 = !{!"clang version 7.0.0 (http://llvm.org/git/clang.git a05f37359b23be7c068e19968c8f106edf6f2b34) (http://llvm.org/git/llvm.git d693de1fee74d455e20f96006aac50317ca1da6b)"} + +... +--- +name: int32_to_float +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +body: | + bb.1.entry: + liveins: $edi + + ; CHECK-LABEL: name: int32_to_float + ; CHECK: liveins: $edi + ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK: [[CVTSI2SSrr:%[0-9]+]]:fr32 = CVTSI2SSrr [[COPY]] + ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SSrr]] + ; CHECK: $xmm0 = COPY [[COPY1]] + ; CHECK: RET 0, implicit $xmm0 + %0:gpr(s32) = COPY $edi + %1:vecr(s32) = G_SITOFP %0(s32) + %2:vecr(s128) = G_ANYEXT %1(s32) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... +--- +name: int64_to_float +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +body: | + bb.1.entry: + liveins: $rdi + + ; CHECK-LABEL: name: int64_to_float + ; CHECK: liveins: $rdi + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; CHECK: [[CVTSI642SSrr:%[0-9]+]]:fr32 = CVTSI642SSrr [[COPY]] + ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI642SSrr]] + ; CHECK: $xmm0 = COPY [[COPY1]] + ; CHECK: RET 0, implicit $xmm0 + %0:gpr(s64) = COPY $rdi + %1:vecr(s32) = G_SITOFP %0(s64) + %2:vecr(s128) = G_ANYEXT %1(s32) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... +--- +name: int32_to_double +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +body: | + bb.1.entry: + liveins: $edi + + ; CHECK-LABEL: name: int32_to_double + ; CHECK: liveins: $edi + ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr [[COPY]] + ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SDrr]] + ; CHECK: $xmm0 = COPY [[COPY1]] + ; CHECK: RET 0, implicit $xmm0 + %0:gpr(s32) = COPY $edi + %1:vecr(s64) = G_SITOFP %0(s32) + %2:vecr(s128) = G_ANYEXT %1(s64) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... +--- +name: int64_to_double +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: vecr } + - { id: 2, class: vecr } +body: | + bb.1.entry: + liveins: $rdi + + ; CHECK-LABEL: name: int64_to_double + ; CHECK: liveins: $rdi + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi + ; CHECK: [[CVTSI642SDrr:%[0-9]+]]:fr64 = CVTSI642SDrr [[COPY]] + ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI642SDrr]] + ; CHECK: $xmm0 = COPY [[COPY1]] + ; CHECK: RET 0, implicit $xmm0 + %0:gpr(s64) = COPY $rdi + %1:vecr(s64) = G_SITOFP %0(s64) + %2:vecr(s128) = G_ANYEXT %1(s64) + $xmm0 = COPY %2(s128) + RET 0, implicit $xmm0 + +... -- 2.7.4