From 48c97fa1ba7d6628352fc2433abd91a41f6c8171 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Mon, 7 Nov 2016 14:58:38 -0800 Subject: [PATCH] X86: Properly handle bad FPU opcode Since Bad_Opcode and FGRPd9_2 were the same in i386-dis.c, all Bad_Opcode entries in float_reg were displaced as FGRPd9_2. This patch adds an entry for Bad_Opcode in fgrps to avoid treating it as FGRPd9_2. gas/ PR binutils/20775 * testsuite/gas/i386/i386.exp: Run fpu-bad. * testsuite/gas/i386/fpu-bad.d: New file. * testsuite/gas/i386/fpu-bad.s: Likewise. opcodes/ PR binutils/20775 * i386-dis.c (FGRPd9_2): Replace 0 with 1. (FGRPd9_4): Replace 1 with 2. (FGRPd9_5): Replace 2 with 3. (FGRPd9_6): Replace 3 with 4. (FGRPd9_7): Replace 4 with 5. (FGRPda_5): Replace 5 with 6. (FGRPdb_4): Replace 6 with 7. (FGRPde_3): Replace 7 with 8. (FGRPdf_4): Replace 8 with 9. (fgrps): Add an entry for Bad_Opcode. --- gas/ChangeLog | 7 +++++++ gas/testsuite/gas/i386/fpu-bad.d | 11 +++++++++++ gas/testsuite/gas/i386/fpu-bad.s | 4 ++++ gas/testsuite/gas/i386/i386.exp | 1 + opcodes/ChangeLog | 14 ++++++++++++++ opcodes/i386-dis.c | 41 ++++++++++++++++++++++------------------ 6 files changed, 60 insertions(+), 18 deletions(-) create mode 100644 gas/testsuite/gas/i386/fpu-bad.d create mode 100644 gas/testsuite/gas/i386/fpu-bad.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 6cdfc69..e8481a3 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2016-11-07 H.J. Lu + + PR binutils/20775 + * testsuite/gas/i386/i386.exp: Run fpu-bad. + * testsuite/gas/i386/fpu-bad.d: New file. + * testsuite/gas/i386/fpu-bad.s: Likewise. + 2016-11-04 Nathan Sidwell gas/ diff --git a/gas/testsuite/gas/i386/fpu-bad.d b/gas/testsuite/gas/i386/fpu-bad.d new file mode 100644 index 0000000..ea1fe24 --- /dev/null +++ b/gas/testsuite/gas/i386/fpu-bad.d @@ -0,0 +1,11 @@ +#as: --32 +#objdump: -dw +#name: i386 fpu bad opcodes + +.*: +file format .* + +Disassembly of section .text: + +0+ : + +[a-f0-9]+: dd f0 \(bad\) +#pass diff --git a/gas/testsuite/gas/i386/fpu-bad.s b/gas/testsuite/gas/i386/fpu-bad.s new file mode 100644 index 0000000..a038170 --- /dev/null +++ b/gas/testsuite/gas/i386/fpu-bad.s @@ -0,0 +1,4 @@ + .text +start: + .byte 0xdd + .byte 0xf0 diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 11c342a..1b28fa1 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -378,6 +378,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "ptwrite-intel" run_list_test "avx512vl-1" "-al" run_list_test "avx512vl-2" "-al" + run_dump_test "fpu-bad" # These tests require support for 8 and 16 bit relocs, # so we only run them for ELF and COFF targets. diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b58ad90..438e770 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,17 @@ +2016-11-07 H.J. Lu + + PR binutils/20775 + * i386-dis.c (FGRPd9_2): Replace 0 with 1. + (FGRPd9_4): Replace 1 with 2. + (FGRPd9_5): Replace 2 with 3. + (FGRPd9_6): Replace 3 with 4. + (FGRPd9_7): Replace 4 with 5. + (FGRPda_5): Replace 5 with 6. + (FGRPdb_4): Replace 6 with 7. + (FGRPde_3): Replace 7 with 8. + (FGRPdf_4): Replace 8 with 9. + (fgrps): Add an entry for Bad_Opcode. + 2016-11-04 Andrew Burgess * arc-opc.c (arc_flag_operands): Add F_DI14. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 22f77aa..ec4a697 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -13830,15 +13830,15 @@ static const unsigned char float_mem_mode[] = { #define ST { OP_ST, 0 } #define STi { OP_STi, 0 } -#define FGRPd9_2 NULL, { { NULL, 0 } }, 0 -#define FGRPd9_4 NULL, { { NULL, 1 } }, 0 -#define FGRPd9_5 NULL, { { NULL, 2 } }, 0 -#define FGRPd9_6 NULL, { { NULL, 3 } }, 0 -#define FGRPd9_7 NULL, { { NULL, 4 } }, 0 -#define FGRPda_5 NULL, { { NULL, 5 } }, 0 -#define FGRPdb_4 NULL, { { NULL, 6 } }, 0 -#define FGRPde_3 NULL, { { NULL, 7 } }, 0 -#define FGRPdf_4 NULL, { { NULL, 8 } }, 0 +#define FGRPd9_2 NULL, { { NULL, 1 } }, 0 +#define FGRPd9_4 NULL, { { NULL, 2 } }, 0 +#define FGRPd9_5 NULL, { { NULL, 3 } }, 0 +#define FGRPd9_6 NULL, { { NULL, 4 } }, 0 +#define FGRPd9_7 NULL, { { NULL, 5 } }, 0 +#define FGRPda_5 NULL, { { NULL, 6 } }, 0 +#define FGRPdb_4 NULL, { { NULL, 7 } }, 0 +#define FGRPde_3 NULL, { { NULL, 8 } }, 0 +#define FGRPdf_4 NULL, { { NULL, 9 } }, 0 static const struct dis386 float_reg[][8] = { /* d8 */ @@ -13932,48 +13932,53 @@ static const struct dis386 float_reg[][8] = { }; static char *fgrps[][8] = { - /* d9_2 0 */ + /* Bad opcode 0 */ + { + "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, + + /* d9_2 1 */ { "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* d9_4 1 */ + /* d9_4 2 */ { "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", }, - /* d9_5 2 */ + /* d9_5 3 */ { "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", }, - /* d9_6 3 */ + /* d9_6 4 */ { "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", }, - /* d9_7 4 */ + /* d9_7 5 */ { "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", }, - /* da_5 5 */ + /* da_5 6 */ { "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* db_4 6 */ + /* db_4 7 */ { "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", }, - /* de_3 7 */ + /* de_3 8 */ { "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* df_4 8 */ + /* df_4 9 */ { "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, -- 2.7.4