From 48aad493e353db386ea8fc82f082220342e7e633 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 20 Dec 2019 20:31:53 +0900 Subject: [PATCH] dt-bindings: mtd: denali_dt: document reset property According to the Denali NAND Flash Memory Controller User's Guide, this IP has two reset signals. rst_n: reset most of FFs in the controller core reg_rst_n: reset all FFs in the register interface, and in the initialization sequencer This commit specifies these reset signals. It is possible to control them separately from the IP point of view although they might be often tied up together in actual SoC integration. At least for the upstream platforms, Altera/Intel SOCFPGA and Socionext UniPhier, the reset controller seems to provide only 1-bit control for the NAND controller. If it is the case, the resets property should reference to the same phandles for "nand" and "reg" resets, like this: resets = <&nand_rst>, <&nand_rst>; reset-names = "nand", "reg"; Signed-off-by: Masahiro Yamada Acked-by: Rob Herring Signed-off-by: Miquel Raynal --- Documentation/devicetree/bindings/mtd/denali-nand.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt index b32aed1..98916a8 100644 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt @@ -14,6 +14,11 @@ Required properties: interface clock, and the ECC circuit clock. - clock-names: should contain "nand", "nand_x", "ecc" +Optional properties: + - resets: may contain phandles to the controller core reset, the register + reset + - reset-names: may contain "nand", "reg" + Sub-nodes: Sub-nodes represent available NAND chips. @@ -46,6 +51,8 @@ nand: nand@ff900000 { reg-names = "nand_data", "denali_reg"; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&nand_rst>, <&nand_reg_rst>; + reset-names = "nand", "reg"; interrupts = <0 144 4>; nand@0 { -- 2.7.4