From 4858f06e7d92ed2ebdb29ccbc079c127e675a89c Mon Sep 17 00:00:00 2001 From: Yauheni Kaliuta Date: Wed, 8 Jun 2011 17:12:02 +0300 Subject: [PATCH] usb: musb: gadget: clear TXPKTRDY flag when set FLUSHFIFO Fixes mis-use of MUSB's hardware feature where it won't flush FIFOs when TXPKTRDY flag was set before and we are flushing setting both FLUSHFIFO and TXPKTRDY. In other words, we need to ensure that when we try to flush FIFOs, we don't accidentaly set TXPKTRDY bit too due to a read-back of the register. The MUSB Programming Guide says "May be set simultaneously with TxPktRdy to abort the packet that is currently being loaded into the FIFO". This is a situation where TXPKTRDY hasn't been set yet, but some data already loaded into the fifo. It looks, that if TXPKTRDY has been set before, and there is no loading in progress, but we set FLUSHFIFO with the TXPKTRDY, controller tries to use the same logic to abort loading and as the result just does nothing (because there is no packet been loaded currently) Signed-off-by: Yauheni Kaliuta [ balbi@ti.com : fixed one whitespace git complained about improved the commit log slightly ] Signed-off-by: Felipe Balbi --- drivers/usb/musb/musb_gadget.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c index 0a50a35..6aeb363 100644 --- a/drivers/usb/musb/musb_gadget.c +++ b/drivers/usb/musb/musb_gadget.c @@ -1524,6 +1524,12 @@ static void musb_gadget_fifo_flush(struct usb_ep *ep) csr = musb_readw(epio, MUSB_TXCSR); if (csr & MUSB_TXCSR_FIFONOTEMPTY) { csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; + /* + * Setting both TXPKTRDY and FLUSHFIFO makes controller + * to interrupt current FIFO loading, but not flushing + * the already loaded ones. + */ + csr &= ~MUSB_TXCSR_TXPKTRDY; musb_writew(epio, MUSB_TXCSR, csr); /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ musb_writew(epio, MUSB_TXCSR, csr); -- 2.7.4