From 48340fbe6a1a126298c4fe16dcd186d94e485203 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan <qiucofan@cn.ibm.com>
Date: Tue, 5 Jan 2021 11:25:18 +0800
Subject: [PATCH] [NFC] [PowerPC] Update vec_constants test to reflect more
 patterns

This patch uses update_llc_check script to update vec_constants.ll, and
add two cases to cover 'vsplti+vsldoi' with 16-bit and 24-bit offset.
---
 llvm/test/CodeGen/PowerPC/vec_constants.ll | 89 ++++++++++++++++++------------
 1 file changed, 54 insertions(+), 35 deletions(-)

diff --git a/llvm/test/CodeGen/PowerPC/vec_constants.ll b/llvm/test/CodeGen/PowerPC/vec_constants.ll
index d9257c0..71f448e 100644
--- a/llvm/test/CodeGen/PowerPC/vec_constants.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_constants.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
@@ -20,65 +21,83 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
 }
 
 define <4 x i32> @test_30() nounwind {
-	ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
-
 ; CHECK-LABEL: test_30:
-; CHECK: vspltisw
-; CHECK-NEXT: vadduwm
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisw 2, 15
+; CHECK-NEXT:    vadduwm 2, 2, 2
+; CHECK-NEXT:    blr
+	ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
 }
 
 define <4 x i32> @test_29() nounwind {
-	ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
-
 ; CHECK-LABEL: test_29:
-; CHECK: vspltisw
-; CHECK-NEXT: vspltisw
-; CHECK-NEXT: vsubuwm
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisw 3, -16
+; CHECK-NEXT:    vspltisw 2, 13
+; CHECK-NEXT:    vsubuwm 2, 2, 3
+; CHECK-NEXT:    blr
+	ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
 }
 
 define <8 x i16> @test_n30() nounwind {
-	ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
-
 ; CHECK-LABEL: test_n30:
-; CHECK: vspltish
-; CHECK-NEXT: vadduhm
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltish 2, -15
+; CHECK-NEXT:    vadduhm 2, 2, 2
+; CHECK-NEXT:    blr
+	ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
 }
 
 define <16 x i8> @test_n104() nounwind {
-	ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
-
 ; CHECK-LABEL: test_n104:
-; CHECK: vspltisb
-; CHECK-NEXT: vslb
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisb 2, -13
+; CHECK-NEXT:    vslb 2, 2, 2
+; CHECK-NEXT:    blr
+	ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
 }
 
 define <4 x i32> @test_vsldoi() nounwind {
-	ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
-
 ; CHECK-LABEL: test_vsldoi:
-; CHECK: vspltisw
-; CHECK-NEXT: vsldoi
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisw 2, 2
+; CHECK-NEXT:    vsldoi 2, 2, 2, 1
+; CHECK-NEXT:    blr
+	ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
 }
 
 define <8 x i16> @test_vsldoi_65023() nounwind {
+; CHECK-LABEL: test_vsldoi_65023:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltish 2, -3
+; CHECK-NEXT:    vsldoi 2, 2, 2, 1
+; CHECK-NEXT:    blr
 	ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
+}
 
-; CHECK-LABEL: test_vsldoi_65023:
-; CHECK: vspltish
-; CHECK-NEXT: vsldoi
-; CHECK-NEXT: blr
+define <4 x i32> @test_vsldoi_x16() nounwind {
+; CHECK-LABEL: test_vsldoi_x16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisw 2, -3
+; CHECK-NEXT:    vsldoi 2, 2, 2, 2
+; CHECK-NEXT:    blr
+	ret <4 x i32> <i32 -131073, i32 -131073, i32 -131073, i32 -131073>
 }
 
-define <4 x i32> @test_rol() nounwind {
-	ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
+define <4 x i32> @test_vsldoi_x24() nounwind {
+; CHECK-LABEL: test_vsldoi_x24:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisw 2, -3
+; CHECK-NEXT:    vsldoi 2, 2, 2, 3
+; CHECK-NEXT:    blr
+	ret <4 x i32> <i32 -33554433, i32 -33554433, i32 -33554433, i32 -33554433>
+}
 
+define <4 x i32> @test_rol() nounwind {
 ; CHECK-LABEL: test_rol:
-; CHECK: vspltisw
-; CHECK-NEXT: vrlw
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vspltisw 2, -12
+; CHECK-NEXT:    vrlw 2, 2, 2
+; CHECK-NEXT:    blr
+	ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
 }
-- 
2.7.4