From 47af1ac69af90f87ad6e365310db6d1e2b28be9e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 11 Aug 2020 20:38:40 -0400 Subject: [PATCH] AMDGPU: Correct definitions for global saddr instructions The VGPR component is a 32-bit offset, not 64-bits. I'm not sure what the correct syntax is for this. This maintains the vaddr position and leaves saddr in the end "off" position. This is particularly terrible for stores, since the operand order is now , , , splitting the pointer operands. I suppose this is a logical consequence from the mistake of not putting the data operand first. I'm not sure what sp3 does. --- llvm/lib/Target/AMDGPU/FLATInstructions.td | 16 +++++---- llvm/test/CodeGen/AMDGPU/sdwa-ops.mir | 30 ++++++++-------- llvm/test/MC/AMDGPU/flat-global.s | 40 +++++++++++----------- llvm/test/MC/AMDGPU/gfx1030_new.s | 2 +- llvm/test/MC/Disassembler/AMDGPU/flat_gfx9.txt | 12 +++---- .../MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt | 2 +- .../test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt | 14 ++++---- 7 files changed, 59 insertions(+), 57 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 3ee01d5..c180ea8 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -140,10 +140,11 @@ class FLAT_Load_Pseudo { let has_data = 0; let mayLoad = 1; @@ -161,9 +162,10 @@ class FLAT_Store_Pseudo { let mayLoad = 0; let mayStore = 1; diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-ops.mir b/llvm/test/CodeGen/AMDGPU/sdwa-ops.mir index 2546775..17d430c 100644 --- a/llvm/test/CodeGen/AMDGPU/sdwa-ops.mir +++ b/llvm/test/CodeGen/AMDGPU/sdwa-ops.mir @@ -29,19 +29,19 @@ body: | %63:vgpr_32, %65:sreg_64_xexec = nsw V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec %64:vgpr_32, dead %66:sreg_64_xexec = nuw V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %30, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) %171:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %173:vgpr_32, %175:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %171, 0, implicit $exec %174:vgpr_32, dead %176:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %175, 0, implicit $exec %172:vreg_64 = REG_SEQUENCE %173, %subreg.sub0, %174, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %30, %172, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %172, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -77,13 +77,13 @@ body: | %64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) %161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec %163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec %164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %30, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -113,7 +113,7 @@ body: | %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %66, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -143,7 +143,7 @@ body: | %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %65, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -172,7 +172,7 @@ body: | %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -201,7 +201,7 @@ body: | %30:vreg_64 = COPY $sgpr0_sgpr1 %63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %23, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -232,7 +232,7 @@ body: | %30:vreg_64 = COPY $sgpr0_sgpr1 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %24, 0, implicit $exec %62:vreg_64 = REG_SEQUENCE %23, %subreg.sub0, %23, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %30, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -263,7 +263,7 @@ body: | %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %31:vreg_64 = COPY $vcc %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -294,7 +294,7 @@ body: | %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %31:vreg_64 = COPY $vcc %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -325,7 +325,7 @@ body: | %32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %32, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %32.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -356,7 +356,7 @@ body: | %32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1 %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %32, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %32.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) ... @@ -386,5 +386,5 @@ body: | %31:vreg_64 = COPY killed $vcc %64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1 - GLOBAL_STORE_DWORDX2_SADDR %31, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) + GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8) diff --git a/llvm/test/MC/AMDGPU/flat-global.s b/llvm/test/MC/AMDGPU/flat-global.s index 83b0c4c..b771073 100644 --- a/llvm/test/MC/AMDGPU/flat-global.s +++ b/llvm/test/MC/AMDGPU/flat-global.s @@ -179,42 +179,42 @@ global_store_dwordx4 v[3:4], v[1:4], off dlc global_store_dword v[3:4], v1, off offset:12 // GFX10: encoding: [0x0c,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00] // GFX9: global_store_dword v[3:4], v1, off offset:12 ; encoding: [0x0c,0x80,0x70,0xdc,0x03,0x01,0x7f,0x00] -// VI-ERR: :36: error: not a valid operand +// VI-ERR: [[@LINE-3]]:36: error: not a valid operand -global_load_dword v1, v[3:4], s[2:3] +global_load_dword v1, v3, s[2:3] // GFX10: encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x02,0x01] -// GFX9: global_load_dword v1, v[3:4], s[2:3] ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x02,0x01] -// VI-ERR: instruction not supported on this GPU +// GFX9: global_load_dword v1, v3, s[2:3] ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x02,0x01] +// VI-ERR: [[@LINE-3]]:1: error: instruction not supported on this GPU -global_load_dword v1, v[3:4], s[2:3] offset:24 +global_load_dword v1, v3, s[2:3] offset:24 // GFX10: encoding: [0x18,0x80,0x30,0xdc,0x03,0x00,0x02,0x01] -// GFX9: global_load_dword v1, v[3:4], s[2:3] offset:24 ; encoding: [0x18,0x80,0x50,0xdc,0x03,0x00,0x02,0x01] -// VI-ERR: :38: error: not a valid operand. +// GFX9: global_load_dword v1, v3, s[2:3] offset:24 ; encoding: [0x18,0x80,0x50,0xdc,0x03,0x00,0x02,0x01] +// VI-ERR: [[@LINE-3]]:34: error: not a valid operand. -global_load_dword v1, v[3:4], s[2:3] offset:-8 +global_load_dword v1, v3, s[2:3] offset:-8 // GFX10: encoding: [0xf8,0x8f,0x30,0xdc,0x03,0x00,0x02,0x01] -// GFX9: global_load_dword v1, v[3:4], s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x50,0xdc,0x03,0x00,0x02,0x01] -// VI-ERR: :38: error: not a valid operand. +// GFX9: global_load_dword v1, v3, s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x50,0xdc,0x03,0x00,0x02,0x01] +// VI-ERR: [[@LINE-3]]:34: error: not a valid operand. -global_store_dword v[3:4], v1, s[2:3] +global_store_dword v3, v1, s[2:3] // GFX10: encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] -// GFX9: global_store_dword v[3:4], v1, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] +// GFX9: global_store_dword v3, v1, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] // VI-ERR: instruction not supported on this GPU -global_store_dword v[3:4], v1, s[2:3] offset:24 +global_store_dword v3, v1, s[2:3] offset:24 // GFX10: encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] -// GFX9: global_store_dword v[3:4], v1, s[2:3] offset:24 ; encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] -// VI-ERR: :39: error: not a valid operand. +// GFX9: global_store_dword v3, v1, s[2:3] offset:24 ; encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] +// VI-ERR: [[@LINE-3]]:35: error: not a valid operand. -global_store_dword v[3:4], v1, s[2:3] offset:-8 +global_store_dword v3, v1, s[2:3] offset:-8 // GFX10: encoding: [0xf8,0x8f,0x70,0xdc,0x03,0x01,0x02,0x00] -// GFX9: global_store_dword v[3:4], v1, s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x70,0xdc,0x03,0x01,0x02,0x00] -// VI-ERR: :39: error: not a valid operand. +// GFX9: global_store_dword v3, v1, s[2:3] offset:-8 ; encoding: [0xf8,0x9f,0x70,0xdc,0x03,0x01,0x02,0x00] +// VI-ERR: :35: error: not a valid operand. // XXX: Is this valid? -global_store_dword v[3:4], v1, exec +global_store_dword v3, v1, exec // GFX10: encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00] -// GFX9: global_store_dword v[3:4], v1, exec ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00] +// GFX9: global_store_dword v3, v1, exec ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00] // VI-ERR: instruction not supported on this GPU global_load_dword v1, v[3:4], s2 diff --git a/llvm/test/MC/AMDGPU/gfx1030_new.s b/llvm/test/MC/AMDGPU/gfx1030_new.s index 7125fd2..92dfbdd 100644 --- a/llvm/test/MC/AMDGPU/gfx1030_new.s +++ b/llvm/test/MC/AMDGPU/gfx1030_new.s @@ -10,7 +10,7 @@ global_load_dword_addtid v1, s[2:3] offset:16 glc slc dlc global_store_dword_addtid v1, s[2:3] offset:16 glc slc dlc // GFX10: encoding: [0x10,0x90,0x5f,0xdc,0x00,0x01,0x02,0x00] -global_store_dword v[254:255], v1, s[2:3] offset:16 +global_store_dword v254, v1, s[2:3] offset:16 // GFX10: encoding: [0x10,0x80,0x70,0xdc,0xfe,0x01,0x02,0x00] global_atomic_csub v2, v[0:1], v2, off offset:100 glc slc diff --git a/llvm/test/MC/Disassembler/AMDGPU/flat_gfx9.txt b/llvm/test/MC/Disassembler/AMDGPU/flat_gfx9.txt index 30be998..d090067 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/flat_gfx9.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/flat_gfx9.txt @@ -54,22 +54,22 @@ # CHECK: global_atomic_add v0, v[2:3], v4, s[0:1] offset:-1 glc ; encoding: [0xff,0x9f,0x09,0xdd,0x02,0x04,0x00,0x00] 0xff,0x9f,0x09,0xdd,0x02,0x04,0x00,0x00 -# CHECK: global_load_sbyte v0, v[2:3], s[0:1] ; encoding: [0x00,0x80,0x44,0xdc,0x02,0x00,0x00,0x00] +# CHECK: global_load_sbyte v0, v2, s[0:1] ; encoding: [0x00,0x80,0x44,0xdc,0x02,0x00,0x00,0x00] 0x00,0x80,0x44,0xdc,0x02,0x00,0x00,0x00 -# CHECK: global_load_sbyte v0, v[2:3], s[0:1] offset:4095 ; encoding: [0xff,0x8f,0x44,0xdc,0x02,0x00,0x00,0x00] +# CHECK: global_load_sbyte v0, v2, s[0:1] offset:4095 ; encoding: [0xff,0x8f,0x44,0xdc,0x02,0x00,0x00,0x00] 0xff,0x8f,0x44,0xdc,0x02,0x00,0x00,0x00 -# CHECK: global_load_sbyte v0, v[2:3], s[0:1] offset:-4096 ; encoding: [0x00,0x90,0x44,0xdc,0x02,0x00,0x00,0x00] +# CHECK: global_load_sbyte v0, v2, s[0:1] offset:-4096 ; encoding: [0x00,0x90,0x44,0xdc,0x02,0x00,0x00,0x00] 0x00,0x90,0x44,0xdc,0x02,0x00,0x00,0x00 -# CHECK: global_store_dwordx2 v[2:3], v[4:5], s[0:1] ; encoding: [0x00,0x80,0x74,0xdc,0x02,0x04,0x00,0x00] +# CHECK: global_store_dwordx2 v2, v[4:5], s[0:1] ; encoding: [0x00,0x80,0x74,0xdc,0x02,0x04,0x00,0x00] 0x00,0x80,0x74,0xdc,0x02,0x04,0x00,0x00 -# CHECK: global_store_dwordx2 v[2:3], v[4:5], s[0:1] offset:4095 ; encoding: [0xff,0x8f,0x74,0xdc,0x02,0x04,0x00,0x00] +# CHECK: global_store_dwordx2 v2, v[4:5], s[0:1] offset:4095 ; encoding: [0xff,0x8f,0x74,0xdc,0x02,0x04,0x00,0x00] 0xff,0x8f,0x74,0xdc,0x02,0x04,0x00,0x00 -# CHECK: global_store_dwordx2 v[2:3], v[4:5], s[0:1] offset:-4096 ; encoding: [0x00,0x90,0x74,0xdc,0x02,0x04,0x00,0x00] +# CHECK: global_store_dwordx2 v2, v[4:5], s[0:1] offset:-4096 ; encoding: [0x00,0x90,0x74,0xdc,0x02,0x04,0x00,0x00] 0x00,0x90,0x74,0xdc,0x02,0x04,0x00,0x00 # CHECK: scratch_load_dword v0, v0, off offset:-1 ; encoding: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x7f,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt index ba4348b..82e4561 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt @@ -10,7 +10,7 @@ # GFX10: global_store_dword_addtid v1, s[2:3] offset:16 glc slc dlc 0x10,0x90,0x5f,0xdc,0x00,0x01,0x02,0x00 -# GFX10: global_store_dword v[254:255], v1, s[2:3] offset:16 +# GFX10: global_store_dword v254, v1, s[2:3] offset:16 0x10,0x80,0x70,0xdc,0xfe,0x01,0x02,0x00 # GFX10: global_atomic_csub v2, v[0:1], v2, off offset:100 glc slc diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt index fe9986c..d8698ad 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt @@ -8237,13 +8237,13 @@ # GFX10: global_load_dword v1, v[3:4], off offset:2047 ; encoding: [0xff,0x87,0x30,0xdc,0x03,0x00,0x7d,0x01] 0xff,0x87,0x30,0xdc,0x03,0x00,0x7d,0x01 -# GFX10: global_load_dword v1, v[3:4], s[2:3] ; encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x02,0x01] +# GFX10: global_load_dword v1, v3, s[2:3] ; encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x02,0x01] 0x00,0x80,0x30,0xdc,0x03,0x00,0x02,0x01 -# GFX10: global_load_dword v1, v[3:4], s[2:3] offset:2040 ; encoding: [0xf8,0x87,0x30,0xdc,0x03,0x00,0x02,0x01] +# GFX10: global_load_dword v1, v3, s[2:3] offset:2040 ; encoding: [0xf8,0x87,0x30,0xdc,0x03,0x00,0x02,0x01] 0xf8,0x87,0x30,0xdc,0x03,0x00,0x02,0x01 -# GFX10: global_load_dword v1, v[3:4], s[2:3] offset:24 ; encoding: [0x18,0x80,0x30,0xdc,0x03,0x00,0x02,0x01] +# GFX10: global_load_dword v1, v3, s[2:3] offset:24 ; encoding: [0x18,0x80,0x30,0xdc,0x03,0x00,0x02,0x01] 0x18,0x80,0x30,0xdc,0x03,0x00,0x02,0x01 # GFX10: global_load_dwordx2 v[1:2], v[3:4], off ; encoding: [0x00,0x80,0x34,0xdc,0x03,0x00,0x7d,0x01] @@ -8315,7 +8315,7 @@ # GFX10: global_store_byte_d16_hi v[3:4], v1, off ; encoding: [0x00,0x80,0x64,0xdc,0x03,0x01,0x7d,0x00] 0x00,0x80,0x64,0xdc,0x03,0x01,0x7d,0x00 -# GFX10: global_store_dword v[3:4], v1, exec ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00] +# GFX10: global_store_dword v3, v1, exec ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00] 0x00,0x80,0x70,0xdc,0x03,0x01,0x7e,0x00 # GFX10: global_store_dword v[3:4], v1, off ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00] @@ -8327,13 +8327,13 @@ # GFX10: global_store_dword v[3:4], v1, off offset:12 ; encoding: [0x0c,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00] 0x0c,0x80,0x70,0xdc,0x03,0x01,0x7d,0x00 -# GFX10: global_store_dword v[3:4], v1, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] +# GFX10: global_store_dword v3, v1, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] 0x00,0x80,0x70,0xdc,0x03,0x01,0x02,0x00 -# GFX10: global_store_dword v[3:4], v1, s[2:3] offset:2040 ; encoding: [0xf8,0x87,0x70,0xdc,0x03,0x01,0x02,0x00] +# GFX10: global_store_dword v3, v1, s[2:3] offset:2040 ; encoding: [0xf8,0x87,0x70,0xdc,0x03,0x01,0x02,0x00] 0xf8,0x87,0x70,0xdc,0x03,0x01,0x02,0x00 -# GFX10: global_store_dword v[3:4], v1, s[2:3] offset:24 ; encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] +# GFX10: global_store_dword v3, v1, s[2:3] offset:24 ; encoding: [0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00] 0x18,0x80,0x70,0xdc,0x03,0x01,0x02,0x00 # GFX10: global_store_dwordx2 v[3:4], v[1:2], off ; encoding: [0x00,0x80,0x74,0xdc,0x03,0x01,0x7d,0x00] -- 2.7.4