From 47195029414940da30c9f9bfbe6a97ac0d33192a Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@quicinc.com>
Date: Thu, 21 Mar 2019 17:14:22 +0000
Subject: [PATCH] Add more rotate tests, including ORs of rotates

This is a part of https://reviews.llvm.org/D47735.

llvm-svn: 356683
---
 llvm/test/CodeGen/Hexagon/rotate-multi.ll |  90 +++++++++++++++++++++
 llvm/test/CodeGen/Hexagon/rotate.ll       |  24 ++++++
 llvm/test/CodeGen/X86/rotate-multi.ll     | 130 ++++++++++++++++++++++++++++++
 3 files changed, 244 insertions(+)
 create mode 100644 llvm/test/CodeGen/Hexagon/rotate-multi.ll
 create mode 100644 llvm/test/CodeGen/X86/rotate-multi.ll

diff --git a/llvm/test/CodeGen/Hexagon/rotate-multi.ll b/llvm/test/CodeGen/Hexagon/rotate-multi.ll
new file mode 100644
index 0000000..74e3187
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/rotate-multi.ll
@@ -0,0 +1,90 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; OR of two rotates of %a0(r0).
+; CHECK-LABEL: f0:
+; CHECK: r[[R00:[0-9]+]] = rol(r0,#7)
+; CHECK: r[[R00]] |= rol(r0,#9)
+define i32 @f0(i32 %a0) #0 {
+b0:
+  %v0 = shl i32 %a0, 7
+  %v1 = lshr i32 %a0, 25
+  %v2 = or i32 %v0, %v1
+  %v3 = shl i32 %a0, 9
+  %v4 = lshr i32 %a0, 23
+  %v5 = or i32 %v3, %v4
+  %v6 = or i32 %v2, %v5
+  ret i32 %v6
+}
+
+; OR of two rotates of %a0(r0) with an extra input %a1(r1).
+; CHECK-LABEL: f1:
+; CHECK: r1 |= asl(r0,#7)
+; CHECK: r1 |= rol(r0,#9)
+define i32 @f1(i32 %a0, i32 %a1) #0 {
+b0:
+  %v0 = shl i32 %a0, 7
+  %v1 = lshr i32 %a0, 25
+  %v2 = or i32 %v0, %a1
+  %v3 = shl i32 %a0, 9
+  %v4 = lshr i32 %a0, 23
+  %v5 = or i32 %v3, %v4
+  %v6 = or i32 %v2, %v5
+  %v7 = or i32 %v6, %v1
+  ret i32 %v6
+}
+
+; OR of two rotates of two different inputs: %a0(r0) and %a1(r1).
+; CHECK-LABEL: f2:
+; CHECK: r[[R20:[0-9]+]] = asl(r0,#11)
+; CHECK: r[[R21:[0-9]+]] = lsr(r0,#21)
+; CHECK: r[[R22:[0-9]+]] = lsr(r1,#13)
+; CHECK: r[[R20]] |= asl(r1,#19)
+; CHECK: r[[R20]] |= or(r[[R21]],r[[R22]])
+define i32 @f2(i32 %a0, i32 %a1) #0 {
+  %v0 = shl i32 %a0, 11
+  %v1 = lshr i32 %a0, 21
+  %v2 = shl i32 %a1, 19
+  %v3 = lshr i32 %a1, 13
+  %v4 = or i32 %v0, %v2
+  %v5 = or i32 %v1, %v3
+  %v6 = or i32 %v4, %v5
+  ret i32 %v6
+}
+
+; ORs of multiple shifts of the same value with only one pair actually
+; matching a rotate.
+; CHECK-LABEL: f3:
+; CHECK: r[[R30:[0-9]+]] = asl(r0,#3)
+; CHECK: r[[R30]] |= asl(r0,#5)
+; CHECK: r[[R30]] |= asl(r0,#7)
+; CHECK: r[[R30]] |= asl(r0,#13)
+; CHECK: r[[R30]] |= asl(r0,#19)
+; CHECK: r[[R30]] |= lsr(r0,#2)
+; CHECK: r[[R30]] |= lsr(r0,#15)
+; CHECK: r[[R30]] |= lsr(r0,#23)
+; CHECK: r[[R30]] |= lsr(r0,#25)
+; CHECK: r[[R30]] |= lsr(r0,#30)
+define i32 @f3(i32 %a0) #0 {
+  %v0 = shl i32 %a0, 3
+  %v1 = shl i32 %a0, 5
+  %v2 = shl i32 %a0, 7      ; rotate
+  %v3 = shl i32 %a0, 13
+  %v4 = shl i32 %a0, 19
+  %v5 = lshr i32 %a0, 2
+  %v6 = lshr i32 %a0, 15
+  %v7 = lshr i32 %a0, 23
+  %v8 = lshr i32 %a0, 25    ; rotate
+  %v9 = lshr i32 %a0, 30
+  %v10 = or i32  %v0, %v1
+  %v11 = or i32 %v10, %v2
+  %v12 = or i32 %v11, %v3
+  %v13 = or i32 %v12, %v4
+  %v14 = or i32 %v13, %v5
+  %v15 = or i32 %v14, %v6
+  %v16 = or i32 %v15, %v7
+  %v17 = or i32 %v16, %v8
+  %v18 = or i32 %v17, %v9
+  ret i32 %v18
+}
+
+attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="-packets" }
diff --git a/llvm/test/CodeGen/Hexagon/rotate.ll b/llvm/test/CodeGen/Hexagon/rotate.ll
index 3015a5a..101d68b 100644
--- a/llvm/test/CodeGen/Hexagon/rotate.ll
+++ b/llvm/test/CodeGen/Hexagon/rotate.ll
@@ -134,6 +134,18 @@ b0:
   ret i32 %v3
 }
 
+; CHECK-LABEL: f11
+; CHECK: r0 |= lsr(r1,#25)
+; CHECK: r0 |= asl(r1,#7)
+define i32 @f11(i32 %a0, i32 %a1) #0 {
+b0:
+  %v0 = shl i32 %a1, 7
+  %v1 = lshr i32 %a1, 25
+  %v2 = or i32 %v1, %a0
+  %v3 = or i32 %v2, %v0
+  ret i32 %v3
+}
+
 ; CHECK-LABEL: f12
 ; CHECK: r0 ^= rol(r1,#7)
 define i32 @f12(i32 %a0, i32 %a1) #0 {
@@ -178,6 +190,18 @@ b0:
   ret i64 %v3
 }
 
+; CHECK-LABEL: f16
+; CHECK: r1:0 |= lsr(r3:2,#57)
+; CHECK: r1:0 |= asl(r3:2,#7)
+define i64 @f16(i64 %a0, i64 %a1) #0 {
+b0:
+  %v0 = shl i64 %a1, 7
+  %v1 = lshr i64 %a1, 57
+  %v2 = or i64 %v1, %a0
+  %v3 = or i64 %v2, %v0
+  ret i64 %v3
+}
+
 ; CHECK-LABEL: f17
 ; CHECK: r1:0 ^= rol(r3:2,#7)
 define i64 @f17(i64 %a0, i64 %a1) #0 {
diff --git a/llvm/test/CodeGen/X86/rotate-multi.ll b/llvm/test/CodeGen/X86/rotate-multi.ll
new file mode 100644
index 0000000..e68c522
--- /dev/null
+++ b/llvm/test/CodeGen/X86/rotate-multi.ll
@@ -0,0 +1,130 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
+
+; OR of two rotates of %a0(edi).
+define i32 @f0(i32 %a0) #0 {
+; CHECK-LABEL: f0:
+; CHECK:       # %bb.0: # %b0
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    movl %edi, %ecx
+; CHECK-NEXT:    roll $7, %ecx
+; CHECK-NEXT:    roll $9, %eax
+; CHECK-NEXT:    orl %ecx, %eax
+; CHECK-NEXT:    retq
+b0:
+  %v0 = shl i32 %a0, 7
+  %v1 = lshr i32 %a0, 25
+  %v2 = or i32 %v0, %v1
+  %v3 = shl i32 %a0, 9
+  %v4 = lshr i32 %a0, 23
+  %v5 = or i32 %v3, %v4
+  %v6 = or i32 %v2, %v5
+  ret i32 %v6
+}
+
+; OR of two rotates of %a0(edi) with an extra input %a1(esi).
+define i32 @f1(i32 %a0, i32 %a1) #0 {
+; CHECK-LABEL: f1:
+; CHECK:       # %bb.0: # %b0
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    movl %edi, %ecx
+; CHECK-NEXT:    shll $7, %ecx
+; CHECK-NEXT:    roll $9, %eax
+; CHECK-NEXT:    orl %esi, %eax
+; CHECK-NEXT:    orl %ecx, %eax
+; CHECK-NEXT:    retq
+b0:
+  %v0 = shl i32 %a0, 7
+  %v1 = lshr i32 %a0, 25
+  %v2 = or i32 %v0, %a1
+  %v3 = shl i32 %a0, 9
+  %v4 = lshr i32 %a0, 23
+  %v5 = or i32 %v3, %v4
+  %v6 = or i32 %v2, %v5
+  %v7 = or i32 %v6, %v1
+  ret i32 %v6
+}
+
+; OR of two rotates of two different inputs: %a0(edi) and %a1(esi).
+define i32 @f2(i32 %a0, i32 %a1) #0 {
+; CHECK-LABEL: f2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    movl %edi, %ecx
+; CHECK-NEXT:    shll $11, %ecx
+; CHECK-NEXT:    shrl $21, %edi
+; CHECK-NEXT:    movl %esi, %edx
+; CHECK-NEXT:    shll $19, %edx
+; CHECK-NEXT:    shrl $13, %eax
+; CHECK-NEXT:    orl %edi, %eax
+; CHECK-NEXT:    orl %edx, %eax
+; CHECK-NEXT:    orl %ecx, %eax
+; CHECK-NEXT:    retq
+  %v0 = shl i32 %a0, 11
+  %v1 = lshr i32 %a0, 21
+  %v2 = shl i32 %a1, 19
+  %v3 = lshr i32 %a1, 13
+  %v4 = or i32 %v0, %v2
+  %v5 = or i32 %v1, %v3
+  %v6 = or i32 %v4, %v5
+  ret i32 %v6
+}
+
+; ORs of multiple shifts of the same value with only one pair actually
+; matching a rotate.
+define i32 @f3(i32 %a0) #0 {
+; CHECK-LABEL: f3:
+; CHECK:       # %bb.0: # %b0
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT:    leal (,%rdi,8), %eax
+; CHECK-NEXT:    movl %edi, %ecx
+; CHECK-NEXT:    shll $5, %ecx
+; CHECK-NEXT:    movl %edi, %edx
+; CHECK-NEXT:    shll $7, %edx
+; CHECK-NEXT:    orl %ecx, %edx
+; CHECK-NEXT:    movl %edi, %ecx
+; CHECK-NEXT:    shll $13, %ecx
+; CHECK-NEXT:    orl %edx, %ecx
+; CHECK-NEXT:    movl %edi, %edx
+; CHECK-NEXT:    shll $19, %edx
+; CHECK-NEXT:    orl %ecx, %edx
+; CHECK-NEXT:    movl %edi, %ecx
+; CHECK-NEXT:    shrl $2, %ecx
+; CHECK-NEXT:    orl %edx, %ecx
+; CHECK-NEXT:    movl %edi, %edx
+; CHECK-NEXT:    shrl $15, %edx
+; CHECK-NEXT:    orl %ecx, %edx
+; CHECK-NEXT:    movl %edi, %ecx
+; CHECK-NEXT:    shrl $23, %ecx
+; CHECK-NEXT:    orl %edx, %ecx
+; CHECK-NEXT:    movl %edi, %edx
+; CHECK-NEXT:    shrl $25, %edx
+; CHECK-NEXT:    orl %ecx, %edx
+; CHECK-NEXT:    shrl $30, %edi
+; CHECK-NEXT:    orl %edx, %edi
+; CHECK-NEXT:    orl %edi, %eax
+; CHECK-NEXT:    retq
+b0:
+  %v0 = shl i32 %a0, 3
+  %v1 = shl i32 %a0, 5
+  %v2 = shl i32 %a0, 7      ; rotate
+  %v3 = shl i32 %a0, 13
+  %v4 = shl i32 %a0, 19
+  %v5 = lshr i32 %a0, 2
+  %v6 = lshr i32 %a0, 15
+  %v7 = lshr i32 %a0, 23
+  %v8 = lshr i32 %a0, 25    ; rotate
+  %v9 = lshr i32 %a0, 30
+  %v10 = or i32  %v0, %v1
+  %v11 = or i32 %v10, %v2
+  %v12 = or i32 %v11, %v3
+  %v13 = or i32 %v12, %v4
+  %v14 = or i32 %v13, %v5
+  %v15 = or i32 %v14, %v6
+  %v16 = or i32 %v15, %v7
+  %v17 = or i32 %v16, %v8
+  %v18 = or i32 %v17, %v9
+  ret i32 %v18
+}
+
+attributes #0 = { readnone nounwind }
-- 
2.7.4