From 4705148c5e8a94b59285fc8740ac56a380041b94 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 15 May 2023 01:07:28 -0400 Subject: [PATCH] ac/surface: clean up and move the PIPE_CONFIG helper to ac_surface.c This will be used by following commits. Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_gpu_info.c | 50 +++----------------------------------------- src/amd/common/ac_surface.c | 26 +++++++++++++++++++++++ src/amd/common/ac_surface.h | 1 + 3 files changed, 30 insertions(+), 47 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index fd4e81d..0ff553c 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -26,6 +26,7 @@ #include "ac_gpu_info.h" #include "ac_shader_util.h" #include "ac_debug.h" +#include "ac_surface.h" #include "addrlib/src/amdgpu_asic_addr.h" #include "sid.h" @@ -350,52 +351,6 @@ static const char *amdgpu_get_marketing_name(amdgpu_device_handle dev) #define CIK_TILE_MODE_COLOR_2D 14 -#define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f) -#define CIK__PIPE_CONFIG__ADDR_SURF_P2 0 -#define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4 -#define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5 -#define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6 -#define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7 -#define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8 -#define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9 -#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10 -#define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11 -#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12 -#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13 -#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14 -#define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16 -#define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17 - -static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info) -{ - unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D]; - - switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) { - case CIK__PIPE_CONFIG__ADDR_SURF_P2: - return 2; - case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16: - case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16: - case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32: - case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32: - return 4; - case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16: - case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16: - case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16: - case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16: - case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16: - case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32: - case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32: - return 8; - case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16: - case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16: - return 16; - default: - fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n"); - assert(!"this should never occur"); - return 2; - } -} - static bool has_syncobj(int fd) { uint64_t value; @@ -1129,7 +1084,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info) info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(info->gb_addr_config); info->pipe_interleave_bytes = 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config); } else { - info->num_tile_pipes = cik_get_num_tile_pipes(&amdinfo); + unsigned pipe_config = G_009910_PIPE_CONFIG(amdinfo.gb_tile_mode[CIK_TILE_MODE_COLOR_2D]); + info->num_tile_pipes = ac_pipe_config_to_num_pipes(pipe_config); info->pipe_interleave_bytes = 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config); } info->r600_has_virtual_memory = true; diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index a14c1b6..f709127 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -96,6 +96,32 @@ struct ac_addrlib { simple_mtx_t lock; }; +unsigned ac_pipe_config_to_num_pipes(unsigned pipe_config) +{ + switch (pipe_config) { + case V_009910_ADDR_SURF_P2: + return 2; + case V_009910_ADDR_SURF_P4_8x16: + case V_009910_ADDR_SURF_P4_16x16: + case V_009910_ADDR_SURF_P4_16x32: + case V_009910_ADDR_SURF_P4_32x32: + return 4; + case V_009910_ADDR_SURF_P8_16x16_8x16: + case V_009910_ADDR_SURF_P8_16x32_8x16: + case V_009910_ADDR_SURF_P8_32x32_8x16: + case V_009910_ADDR_SURF_P8_16x32_16x16: + case V_009910_ADDR_SURF_P8_32x32_16x16: + case V_009910_ADDR_SURF_P8_32x32_16x32: + case V_009910_ADDR_SURF_P8_32x64_32x32: + return 8; + case V_009910_ADDR_SURF_P16_32x32_8x16: + case V_009910_ADDR_SURF_P16_32x32_16x16: + return 16; + default: + unreachable("invalid pipe_config"); + } +} + bool ac_modifier_has_dcc(uint64_t modifier) { return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 070773b..28ab810 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -440,6 +440,7 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf const struct ac_surf_config *config, enum radeon_surf_mode mode, struct radeon_surf *surf); void ac_surface_zero_dcc_fields(struct radeon_surf *surf); +unsigned ac_pipe_config_to_num_pipes(unsigned pipe_config); void ac_surface_apply_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, uint64_t tiling_flags, enum radeon_surf_mode *mode); -- 2.7.4