From 466056db8fe5e3cec2e789dd08b1a499f703f079 Mon Sep 17 00:00:00 2001
From: "keith.zhao" <keith.zhao@starfivetech.com>
Date: Mon, 4 Jul 2022 18:14:04 +0800
Subject: [PATCH] riscv:driver:drm:DC8200
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1、update dts for vout rgb driver

Signed-off-by:keith.zhao <keith.zhao@statfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi      |  0
 arch/riscv/boot/dts/starfive/jh7110-evb-pinctrl.dtsi | 10 +++++-----
 arch/riscv/boot/dts/starfive/jh7110.dtsi             | 10 ++++++----
 3 files changed, 11 insertions(+), 9 deletions(-)
 mode change 100755 => 100644 arch/riscv/boot/dts/starfive/jh7110-common.dtsi
 mode change 100755 => 100644 arch/riscv/boot/dts/starfive/jh7110-evb-pinctrl.dtsi
 mode change 100755 => 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
old mode 100755
new mode 100644
diff --git a/arch/riscv/boot/dts/starfive/jh7110-evb-pinctrl.dtsi b/arch/riscv/boot/dts/starfive/jh7110-evb-pinctrl.dtsi
old mode 100755
new mode 100644
index 7c797c5..5ba8ab8
--- a/arch/riscv/boot/dts/starfive/jh7110-evb-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-evb-pinctrl.dtsi
@@ -1201,11 +1201,11 @@
 			sf,pinmux = <PAD_GPIO60_FUNC_SEL 1>;
 			sf,pin-ioconfig = <IO(GPIO_IE(0))>;
 		};
-		//rgb-25-pins {
-		//	sf,pins = <PAD_GPIO61>;
-		//	sf,pinmux = <PAD_GPIO61_FUNC_SEL 1>;
-		//	sf,pin-ioconfig = <IO(GPIO_IE(0))>;
-		//};
+		rgb-25-pins {
+			sf,pins = <PAD_GPIO61>;
+			sf,pinmux = <PAD_GPIO61_FUNC_SEL 1>;
+			sf,pin-ioconfig = <IO(GPIO_IE(0))>;
+		};
 		rgb-26-pins {
 			sf,pins = <PAD_GPIO62>;
 			sf,pinmux = <PAD_GPIO62_FUNC_SEL 1>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
old mode 100755
new mode 100644
index 439e599..e2c655f
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -1534,16 +1534,18 @@
 				 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
 				 <&clkvout JH7110_U0_DC8200_CLK_AHB>,
 				 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
-				 <&clkgen JH7110_DOM_VOUT_TOP_LCD_CLK>,
+				 <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
 				 <&hdmitx0_pixelclk>,
-				 <&clkvout JH7110_DC8200_PIX0>;
+				 <&clkvout JH7110_DC8200_PIX0>,
+				 <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
+				 <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
 			clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
 					"noc_disp","noc_isp","noc_stg","vout_src",
 					"top_vout_axi","ahb1","top_vout_ahb",
 					"top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
 					"axi_clk","core_clk","vout_ahb",
-					"vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0";
-
+					"vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
+					"dc8200_pix0_out","dc8200_pix1_out";
 			resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
 				 <&rstgen RSTN_U0_DC8200_AXI>,
 				 <&rstgen RSTN_U0_DC8200_AHB>,
-- 
2.7.4