From 463412e930b248dab06e0f51d92a8cf0e71072fc Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 24 Apr 2023 18:09:14 -0700 Subject: [PATCH] [RISCV] Add test case showing duplicated reduction due to missing one use check. NFC We don't check that the extract_vector_elt has one use in combineBinOpToReduce. --- llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll index 2326db8..a42f418 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll @@ -260,6 +260,25 @@ entry: ret float %res } +define float @reduce_fadd3(float %x, <4 x float> %v, ptr %rdxptr) { +; CHECK-LABEL: reduce_fadd3: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vmv.s.x v9, zero +; CHECK-NEXT: vfredusum.vs v9, v8, v9 +; CHECK-NEXT: vfmv.s.f v10, fa0 +; CHECK-NEXT: vfredusum.vs v8, v8, v10 +; CHECK-NEXT: vfmv.f.s fa0, v8 +; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; CHECK-NEXT: vse32.v v9, (a0) +; CHECK-NEXT: ret +entry: + %rdx = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.0, <4 x float> %v) + %res = fadd fast float %rdx, %x + store float %rdx, ptr %rdxptr + ret float %res +} + define float @reduce_fmax(float %x, <4 x float> %v) { ; CHECK-LABEL: reduce_fmax: ; CHECK: # %bb.0: # %entry -- 2.7.4