From 454258671dbb8b528432073a091610f31b58b8c8 Mon Sep 17 00:00:00 2001 From: Dylan McKay Date: Sat, 1 Sep 2018 12:23:00 +0000 Subject: [PATCH] [AVR] Redefine the 'LSL' instruction as an alias of 'ADD' The 'LSL Rd' instruction is equivalent to 'ADD Rd, Rd'. llvm-svn: 341278 --- llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp | 6 ++++-- llvm/lib/Target/AVR/AVRISelLowering.cpp | 3 ++- llvm/lib/Target/AVR/AVRInstrInfo.td | 20 +++++++++++++------- llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir | 2 +- llvm/test/CodeGen/AVR/pseudo/SEXT.mir | 2 +- llvm/test/CodeGen/AVR/pseudo/ZEXT.mir | 2 +- 6 files changed, 22 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp index 9ebe2dd..536a547 100644 --- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp @@ -1251,13 +1251,14 @@ bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { bool DstIsDead = MI.getOperand(0).isDead(); bool DstIsKill = MI.getOperand(1).isKill(); bool ImpIsDead = MI.getOperand(2).isDead(); - OpLo = AVR::LSLRd; + OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd TRI->splitReg(DstReg, DstLoReg, DstHiReg); // Low part buildMI(MBB, MBBI, OpLo) .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) + .addReg(DstLoReg) .addReg(DstLoReg, getKillRegState(DstIsKill)); auto MIBHI = buildMI(MBB, MBBI, OpHi) @@ -1388,8 +1389,9 @@ template <> bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { .addReg(SrcReg, getKillRegState(SrcIsKill)); } - buildMI(MBB, MBBI, AVR::LSLRd) + buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr .addReg(DstHiReg, RegState::Define) + .addReg(DstHiReg) .addReg(DstHiReg, RegState::Kill); auto SBC = buildMI(MBB, MBBI, AVR::SBCRdRr) diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp index 43f54d8..57fc978 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -1441,8 +1441,9 @@ MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI, default: llvm_unreachable("Invalid shift opcode!"); case AVR::Lsl8: - Opc = AVR::LSLRd; + Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd RC = &AVR::GPR8RegClass; + HasRepeatedOperand = true; break; case AVR::Lsl16: Opc = AVR::LSLWRd; diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td index 7fdb0e0..ec4b6c9 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.td +++ b/llvm/lib/Target/AVR/AVRInstrInfo.td @@ -1632,12 +1632,7 @@ def LATZRd : FZRd<0b111, let Constraints = "$src = $rd", Defs = [SREG] in { - def LSLRd : FRdRr<0b0000, - 0b11, - (outs GPR8:$rd), - (ins GPR8:$src), - "lsl\t$rd", - [(set i8:$rd, (AVRlsl i8:$src)), (implicit SREG)]>; + // 8-bit LSL is an alias of ADD Rd, Rd def LSLWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), @@ -1755,6 +1750,12 @@ Defs = [SREG] in // Clears all bits in a register. def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8:$rd, GPR8:$rd)>; +// LSL Rd +// Alias for ADD Rd, Rd +// -------------- +// Logical shift left one bit. +def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8:$rd, GPR8:$rd)>; + def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8:$rd, GPR8:$rd)>; // SER Rd @@ -2098,5 +2099,10 @@ def : Pat<(shl i16:$src1, (i8 1)), // Lowering of 'tst' node to 'TST' instruction. // TST is an alias of AND Rd, Rd. def : Pat<(AVRtst i8:$rd), - (ANDRdRr $rd, $rd)>; + (ANDRdRr GPR8:$rd, GPR8:$rd)>; + +// Lowering of 'lsl' node to 'LSL' instruction. +// LSL is an alias of 'ADD Rd, Rd' +def : Pat<(AVRlsl i8:$rd), + (ADDRdRr GPR8:$rd, GPR8:$rd)>; diff --git a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir index 854b350..b260e70 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir @@ -15,7 +15,7 @@ body: | ; CHECK-LABEL: test - ; CHECK: $r14 = LSLRd $r14, implicit-def $sreg + ; CHECK: $r14 = ADDRdRr $r14, $r14, implicit-def $sreg ; CHECK-NEXT: $r15 = ADCRdRr $r15, $r15, implicit-def $sreg, implicit killed $sreg $r15r14 = LSLWRd $r15r14, implicit-def $sreg diff --git a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir index 116ea21..b7077a3 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir @@ -17,7 +17,7 @@ body: | ; CHECK: $r14 = MOVRdRr $r31 ; CHECK-NEXT: $r15 = MOVRdRr $r31 - ; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg + ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg $r15r14 = SEXT $r31, implicit-def $sreg diff --git a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir index 116ea21..b7077a3 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir @@ -17,7 +17,7 @@ body: | ; CHECK: $r14 = MOVRdRr $r31 ; CHECK-NEXT: $r15 = MOVRdRr $r31 - ; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg + ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg $r15r14 = SEXT $r31, implicit-def $sreg -- 2.7.4