From 44f6d694b38a6294503da3464c778b021c2da42d Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 13 Aug 2016 01:43:46 +0000 Subject: [PATCH] AMDGPU/R600: Remove macros llvm-svn: 278588 --- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h | 8 -------- llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp | 16 ++++++++-------- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 4 ++-- llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 24 ++++++++---------------- llvm/lib/Target/AMDGPU/R600InstrInfo.h | 17 +++++++++++++++-- 5 files changed, 33 insertions(+), 36 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h index a59eafa..001e037 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h @@ -23,11 +23,6 @@ #define GET_INSTRINFO_OPERAND_ENUM #include "AMDGPUGenInstrInfo.inc" -#define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT -#define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT -#define OPCODE_IS_ZERO AMDGPU::PRED_SETE -#define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE - namespace llvm { class AMDGPUSubtarget; @@ -67,7 +62,4 @@ namespace AMDGPU { } // End llvm namespace -#define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63) -#define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62) - #endif diff --git a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp index 236942c..5ad80f6 100644 --- a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp @@ -430,17 +430,17 @@ void AMDGPUCFGStructurizer::reversePredicateSetter( continue; if (I->getOpcode() == AMDGPU::PRED_X) { switch (I->getOperand(2).getImm()) { - case OPCODE_IS_ZERO_INT: - I->getOperand(2).setImm(OPCODE_IS_NOT_ZERO_INT); + case AMDGPU::PRED_SETE_INT: + I->getOperand(2).setImm(AMDGPU::PRED_SETNE_INT); return; - case OPCODE_IS_NOT_ZERO_INT: - I->getOperand(2).setImm(OPCODE_IS_ZERO_INT); + case AMDGPU::PRED_SETNE_INT: + I->getOperand(2).setImm(AMDGPU::PRED_SETE_INT); return; - case OPCODE_IS_ZERO: - I->getOperand(2).setImm(OPCODE_IS_NOT_ZERO); + case AMDGPU::PRED_SETE: + I->getOperand(2).setImm(AMDGPU::PRED_SETNE); return; - case OPCODE_IS_NOT_ZERO: - I->getOperand(2).setImm(OPCODE_IS_ZERO); + case AMDGPU::PRED_SETNE: + I->getOperand(2).setImm(AMDGPU::PRED_SETE); return; default: llvm_unreachable("PRED_X Opcode invalid!"); diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index 560fe0a..ad3f481 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -328,7 +328,7 @@ R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X), AMDGPU::PREDICATE_BIT) .addOperand(MI.getOperand(1)) - .addImm(OPCODE_IS_NOT_ZERO) + .addImm(AMDGPU::PRED_SETNE) .addImm(0); // Flags TII->addFlag(*NewMI, 0, MO_FLAG_PUSH); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND)) @@ -342,7 +342,7 @@ R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X), AMDGPU::PREDICATE_BIT) .addOperand(MI.getOperand(1)) - .addImm(OPCODE_IS_NOT_ZERO_INT) + .addImm(AMDGPU::PRED_SETNE_INT) .addImm(0); // Flags TII->addFlag(*NewMI, 0, MO_FLAG_PUSH); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND)) diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index 573b187..e29fc46 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -910,17 +910,17 @@ bool R600InstrInfo::ReverseBranchCondition(SmallVectorImpl &Cond) const { MachineOperand &MO = Cond[1]; switch (MO.getImm()) { - case OPCODE_IS_ZERO_INT: - MO.setImm(OPCODE_IS_NOT_ZERO_INT); + case AMDGPU::PRED_SETE_INT: + MO.setImm(AMDGPU::PRED_SETNE_INT); break; - case OPCODE_IS_NOT_ZERO_INT: - MO.setImm(OPCODE_IS_ZERO_INT); + case AMDGPU::PRED_SETNE_INT: + MO.setImm(AMDGPU::PRED_SETE_INT); break; - case OPCODE_IS_ZERO: - MO.setImm(OPCODE_IS_NOT_ZERO); + case AMDGPU::PRED_SETE: + MO.setImm(AMDGPU::PRED_SETNE); break; - case OPCODE_IS_NOT_ZERO: - MO.setImm(OPCODE_IS_ZERO); + case AMDGPU::PRED_SETNE: + MO.setImm(AMDGPU::PRED_SETE); break; default: return true; @@ -1478,11 +1478,3 @@ void R600InstrInfo::clearFlag(MachineInstr &MI, unsigned Operand, FlagOp.setImm(InstFlags); } } - -bool R600InstrInfo::isRegisterStore(const MachineInstr &MI) const { - return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE; -} - -bool R600InstrInfo::isRegisterLoad(const MachineInstr &MI) const { - return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD; -} diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h index feaca98..d967b8a 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h @@ -19,6 +19,14 @@ #include "R600RegisterInfo.h" namespace llvm { + +namespace R600InstrFlags { +enum { + REGISTER_STORE = UINT64_C(1) << 62, + REGISTER_LOAD = UINT64_C(1) << 63 +}; +} + class AMDGPUTargetMachine; class DFAPacketizer; class MachineFunction; @@ -301,8 +309,13 @@ public: void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const; // Helper functions that check the opcode for status information - bool isRegisterStore(const MachineInstr &MI) const; - bool isRegisterLoad(const MachineInstr &MI) const; + bool isRegisterStore(const MachineInstr &MI) const { + return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE; + } + + bool isRegisterLoad(const MachineInstr &MI) const { + return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD; + } }; namespace AMDGPU { -- 2.7.4