From 44b4a640d1a729dbd358fce04f61ba0c4706bf10 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Sergey=20Vostokov/AI=20Tools=20Lab=20/SRR/Staff=20Engineer/?= =?utf8?q?=EC=82=BC=EC=84=B1=EC=A0=84=EC=9E=90?= Date: Tue, 26 Jun 2018 06:51:58 +0300 Subject: [PATCH] Add section "SW Quality Verification" to SDD (#315) * Add section "SW Quality Verification" to SDD This commit adds the section "SW Quality Verification" to SW Development Document. This section contains only plans. Signed-off-by: Sergey Vostokov * Add version info in the title table * fix format * remove table name --- doc/project/development_document.md | 84 ++++++++++++++++++++++++++++++------- 1 file changed, 70 insertions(+), 14 deletions(-) diff --git a/doc/project/development_document.md b/doc/project/development_document.md index 49320fe..8315dd3 100644 --- a/doc/project/development_document.md +++ b/doc/project/development_document.md @@ -2,11 +2,12 @@ **Revision history** -| Ver. | Date | Contents | Author | Approver | -| ---- | ---------- | -------------------------- | --------------- | ------------ | -| 0.1 | 2018.04.12 | Initial version | Vostokov Sergey | Sung-Jae Lee | -| 0.2 | 2018.04.16 | SE member in-charge review | Ilya Lopatin | | -| 1.0 | 2018.04.17 | Final Execution DR version | Vostokov Sergey | Sung-Jae Lee | +| Ver. | Date | Contents | Author | Approver | +| ---- | ---------- | --------------------------- | --------------- | ------------ | +| 0.1 | 2018.04.12 | Initial version | Vostokov Sergey | Sung-Jae Lee | +| 0.2 | 2018.04.16 | SE member in-charge review | Ilya Lopatin | | +| 1.0 | 2018.04.17 | Final Execution DR version | Vostokov Sergey | Sung-Jae Lee | +| 1.1 | 2018.04.17 | Add SW Quality Verification | Vostokov Sergey | Sung-Jae Lee | **Terminology and Abbreviation** @@ -35,10 +36,11 @@ The main goal of the project is to develop a compiler for neural networks to pro The development scope includes the following components: - - Develop importer module to parse, verify and represent NN Model for further optimization and compilation + - Develop importer module to parse, verify and represent NN model for further optimization and compilation - Develop code emitters to produce executable binary for CPU and GPU -2018 year goals: + +**2018 year goals:** - Support TensorFlow Lite NN model format - Support Caffe NN model format @@ -56,15 +58,13 @@ The development scope includes the following components: | Tizen device | Odroid XU4 | Reference board | | SmartMachine target | Microvision mv8890, exynos8890 | Reference device | -Table 1-1. Target Model - ### Assumptions, Dependencies and Constraints ---+++ @@ -87,7 +87,11 @@ Table 1-1. Target Model - + @@ -121,7 +125,6 @@ Table 1-1. Target Model
- www.tizen.org
- wiki.tizen.org
- developer.tizen.org
SmartMachine OS Platform
-Table 1-2. Assumptions, Dependecies and the Constraints ## Development Plan And Result @@ -189,6 +192,59 @@ SW Repository: | 10.2018 Execution | Test report | SW System Test Document (result), SW Unit Test Report | | 12.2018 Completion | Project Completion | Project Completion Report | +## SW Quality Verification + +### SW Verification + +| No | Verification Item | Quality Goal | Tool | Phase | Development Team Member in Charge | Result | Note | +| -- | -------------------------------- | ------------------------------------------ | -------- | --------- | --------------------------------- | ------ | ---- | +| 1 | Open source License Verification | Clear violations of open source obligation | ProtexIP | Execution | Vostokov Sergey | | | +| 2 | Potential Defect | Fix all defects | Svace | Test | Vostokov Sergey | | | +| 3 | System Defect | Fix Critical/ Major defects | Github | Test | Vostokov Sergey | | | + +### Static Analysis + +| No | Activity | Schedule | Result | Comment | +| -- | --------------------------- | ---------- | ------ | ------- | +| 1 | SA Verification I (SVACE) | 28.09.2018 | | | +| 2 | SA Verification II (SVACE) | 30.11.2018 | | | +| 2 | SA Verification III (SVACE) | 31.12.2018 | | | + +### Coding Standard + +| No | Activity | Schedule | Result | Comment | +| -- | ----------------------------------------------------- | -------- | ------ | ------- | +| 1 | Coding standard enforcement with `clang-format` tool. | Regular | | | + + +### Convergence (integration testing) + +Out of scope since the integration with other SW is not required by SW +Requirement Specification. + +### Dynamic Analysis + +| No | Activity | Schedule | Result | Comment | +| -- | ------------------- | ---------- | ------ | ------- | +| 1 | DA Verification I | 28.09.2018 | | | +| 2 | DA Verification II | 30.11.2018 | | | +| 2 | DA Verification III | 31.12.2018 | | | + + +### Architecture Analysis + +SW architecture verification is managed by HQ. + +### SW Security + +Out of the project scope since the project is not related to SW security. + +### Code Review + +| No | Activity | Schedule | Result | Comment | +| -- | ----------- | -------- | ------ | ------------------------------------------------------------------- | +| 1 | Code review | Regular | | All code is reviewed manually using `github` tool before committing | + ## Risk Management | Priority | Risk Description | Risk Reduction Solution | Schedule | Result | Responsibility | -- 2.7.4