From 448ae8ea39c742c20ce00d715fcb7b6fbc56481f Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Fri, 26 Aug 2016 15:30:41 +0800 Subject: [PATCH] gpu: ipu-v3: Do not wait for DMFC FIFO to clear when disabling DMFC channel According to basic tests, it looks there is no issue if we don't wait for DMFC FIFO to clear when disabling DMFC channel. NXP BSP doesn't do that, either. This patch is needed to avoid the annoying warning caused by a timeout on waiting for the FIFO to clear after we add the new DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET flag to the imx-drm driver which changes the procedure to disable display channel slightly. Cc: Philipp Zabel Cc: David Airlie Cc: Russell King Cc: Peter Senna Tschudin Cc: Lucas Stach Cc: Daniel Vetter Signed-off-by: Liu Ying Signed-off-by: Philipp Zabel --- drivers/gpu/ipu-v3/ipu-dmfc.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/gpu/ipu-v3/ipu-dmfc.c b/drivers/gpu/ipu-v3/ipu-dmfc.c index 42705bb..a40f211 100644 --- a/drivers/gpu/ipu-v3/ipu-dmfc.c +++ b/drivers/gpu/ipu-v3/ipu-dmfc.c @@ -123,20 +123,6 @@ int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc) } EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel); -static void ipu_dmfc_wait_fifos(struct ipu_dmfc_priv *priv) -{ - unsigned long timeout = jiffies + msecs_to_jiffies(1000); - - while ((readl(priv->base + DMFC_STAT) & 0x02fff000) != 0x02fff000) { - if (time_after(jiffies, timeout)) { - dev_warn(priv->dev, - "Timeout waiting for DMFC FIFOs to clear\n"); - break; - } - cpu_relax(); - } -} - void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc) { struct ipu_dmfc_priv *priv = dmfc->priv; @@ -145,10 +131,8 @@ void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc) priv->use_count--; - if (!priv->use_count) { - ipu_dmfc_wait_fifos(priv); + if (!priv->use_count) ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN); - } if (priv->use_count < 0) priv->use_count = 0; -- 2.7.4