From 446a1e961a07bf1f495bf06e7c08363f0b6fa3de Mon Sep 17 00:00:00 2001 From: rearnsha Date: Wed, 4 Nov 2009 14:09:55 +0000 Subject: [PATCH] 2009-11-04 Richard Earnshaw PR target/40835 * arm.md (peephole2 patterns for move and compare): New. 2009-11-04 Wei Guozhi PR target/40835 * gcc.target/arm/pr40835: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@153895 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 5 ++++ gcc/config/arm/arm.md | 40 +++++++++++++++++++++++++ gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/gcc.target/arm/pr40835.c | 55 ++++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/pr40835.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8afa6d1..1367409 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2009-11-04 Richard Earnshaw + + PR target/40835 + * arm.md (peephole2 patterns for move and compare): New. + 2009-11-04 Nick Clifton * defaults.h (CONSTANT_ADDRESS_P): Provide a default definition. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b8bf700..fbc52f4 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6770,6 +6770,7 @@ (const_int 6) (const_int 8))))] ) + (define_insn "*movsi_cbranchsi4" [(set (pc) (if_then_else @@ -6833,6 +6834,45 @@ (const_int 10)))))] ) +(define_peephole2 + [(set (match_operand:SI 0 "low_register_operand" "") + (match_operand:SI 1 "low_register_operand" "")) + (set (pc) + (if_then_else (match_operator 2 "arm_comparison_operator" + [(match_dup 1) (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "TARGET_THUMB1" + [(parallel + [(set (pc) + (if_then_else (match_op_dup 2 [(match_dup 1) (const_int 0)]) + (label_ref (match_dup 3)) + (pc))) + (set (match_dup 0) (match_dup 1))])] + "" +) + +;; Sigh! This variant shouldn't be needed, but combine often fails to +;; merge cases like this because the op1 is a hard register in +;; CLASS_LIKELY_SPILLED_P. +(define_peephole2 + [(set (match_operand:SI 0 "low_register_operand" "") + (match_operand:SI 1 "low_register_operand" "")) + (set (pc) + (if_then_else (match_operator 2 "arm_comparison_operator" + [(match_dup 0) (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "TARGET_THUMB1" + [(parallel + [(set (pc) + (if_then_else (match_op_dup 2 [(match_dup 1) (const_int 0)]) + (label_ref (match_dup 3)) + (pc))) + (set (match_dup 0) (match_dup 1))])] + "" +) + (define_insn "*negated_cbranchsi4" [(set (pc) (if_then_else diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5ef448c..62d1625 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2009-11-04 Wei Guozhi + + PR target/40835 + * gcc.target/arm/pr40835: New testcase. + 2009-11-04 Revital Eres * gcc.target/powerpc/vsx-vectorize-3.c: Adjust tetcase following diff --git a/gcc/testsuite/gcc.target/arm/pr40835.c b/gcc/testsuite/gcc.target/arm/pr40835.c new file mode 100644 index 0000000..baf9403 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr40835.c @@ -0,0 +1,55 @@ +/* { dg-options "-mthumb -Os -march=armv5te" } */ +/* { dg-final { scan-assembler-not "cmp" } } */ + +int bar(); +void goo(int, int); + +void eq() +{ + int v = bar(); + if (v == 0) + return; + goo(1, v); +} + +void ge() +{ + int v = bar(); + if (v >= 0) + return; + goo(1, v); +} + +void gt() +{ + int v = bar(); + if (v > 0) + return; + goo(1, v); +} + +void lt() +{ + int v = bar(); + if (v < 0) + return; + goo(1, v); +} + +void le() +{ + int v = bar(); + if (v <= 0) + return; + goo(1, v); +} + +unsigned int foo(); + +void leu() +{ + unsigned int v = foo(); + if (v <= 0) + return; + goo(1, v); +} -- 2.7.4